arch/arm64/boot/dts/microchip/sparx5_pcb125.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
   4  */
   5
   6 /dts-v1/;
   7 #include "sparx5_pcb_common.dtsi"
   8
   9 / {
  10         model = "Sparx5 PCB125 Reference Board";
  11         compatible = "microchip,sparx5-pcb125", "microchip,sparx5";
  12
  13         memory@0 {
  14                 device_type = "memory";
  15                 reg = <0x00000000 0x00000000 0x10000000>;
  16         };
  17 };
  18
  19 &gpio {
  20         emmc_pins: emmc-pins {
  21                 /* NB: No "GPIO_35", "GPIO_36", "GPIO_37"
  22                  * (N/A: CARD_nDETECT, CARD_WP, CARD_LED)
  23                  */
  24                 pins = "GPIO_34", "GPIO_38", "GPIO_39",
  25                         "GPIO_40", "GPIO_41", "GPIO_42",
  26                         "GPIO_43", "GPIO_44", "GPIO_45",
  27                         "GPIO_46", "GPIO_47";
  28                 drive-strength = <3>;
  29                 function = "emmc";
  30         };
  31 };
  32
  33 &sdhci0 {
  34         status = "okay";
  35         bus-width = <8>;
  36         non-removable;
  37         pinctrl-0 = <&emmc_pins>;
  38         max-frequency = <8000000>;
  39         microchip,clock-delay = <10>;
  40 };
  41
  42 &spi0 {
  43         status = "okay";
  44         spi@0 {
  45                 compatible = "spi-mux";
  46                 mux-controls = <&mux>;
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49                 reg = <0>;      /* CS0 */
  50                 spi-flash@9 {
  51                         compatible = "jedec,spi-nor";
  52                         spi-max-frequency = <8000000>;
  53                         reg = <0x9>;    /* SPI */
  54                 };
  55         };
  56         spi@1 {
  57                 compatible = "spi-mux";
  58                 mux-controls = <&mux 0>;
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61                 reg = <1>; /* CS1 */
  62                 spi-flash@9 {
  63                         compatible = "spi-nand";
  64                         pinctrl-0 = <&cs1_pins>;
  65                         pinctrl-names = "default";
  66                         spi-max-frequency = <8000000>;
  67                         reg = <0x9>;    /* SPI */
  68                 };
  69         };
  70 };
  71
  72 &sgpio0 {
  73         status = "okay";
  74         microchip,sgpio-port-ranges = <0 23>;
  75 };
  76
  77 &i2c1 {
  78         status = "okay";
  79 };