| blob | d37ec42a1caa7b5a273eec9125f5c202f7544871 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774a1-sysc.h>
13 #define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
15 / {
16 compatible = "renesas,r8a774a1";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 i2c3 = &i2c3;
25 i2c4 = &i2c4;
26 i2c5 = &i2c5;
27 i2c6 = &i2c6;
28 i2c7 = &i2c_dvfs;
29 };
31 /*
32 * The external audio clocks are configured as 0 Hz fixed frequency
33 * clocks by default.
34 * Boards that provide audio clocks should override them.
35 */
36 audio_clk_a: audio_clk_a {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <0>;
40 };
42 audio_clk_b: audio_clk_b {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <0>;
46 };
48 audio_clk_c: audio_clk_c {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <0>;
52 };
54 /* External CAN clock - to be overridden by boards that provide it */
55 can_clk: can {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 };
61 cluster0_opp: opp_table0 {
62 compatible = "operating-points-v2";
63 opp-shared;
65 opp-500000000 {
66 opp-hz = /bits/ 64 <500000000>;
67 opp-microvolt = <820000>;
68 clock-latency-ns = <300000>;
69 };
70 opp-1000000000 {
71 opp-hz = /bits/ 64 <1000000000>;
72 opp-microvolt = <820000>;
73 clock-latency-ns = <300000>;
74 };
75 opp-1500000000 {
76 opp-hz = /bits/ 64 <1500000000>;
77 opp-microvolt = <820000>;
78 clock-latency-ns = <300000>;
79 };
80 };
82 cluster1_opp: opp_table1 {
83 compatible = "operating-points-v2";
84 opp-shared;
86 opp-800000000 {
87 opp-hz = /bits/ 64 <800000000>;
88 opp-microvolt = <820000>;
89 clock-latency-ns = <300000>;
90 };
91 opp-1000000000 {
92 opp-hz = /bits/ 64 <1000000000>;
93 opp-microvolt = <820000>;
94 clock-latency-ns = <300000>;
95 };
96 opp-1200000000 {
97 opp-hz = /bits/ 64 <1200000000>;
98 opp-microvolt = <820000>;
99 clock-latency-ns = <300000>;
100 };
101 };
103 cpus {
104 #address-cells = <1>;
105 #size-cells = <0>;
107 cpu-map {
108 cluster0 {
109 core0 {
110 cpu = <&a57_0>;
111 };
112 core1 {
113 cpu = <&a57_1>;
114 };
115 };
117 cluster1 {
118 core0 {
119 cpu = <&a53_0>;
120 };
121 core1 {
122 cpu = <&a53_1>;
123 };
124 core2 {
125 cpu = <&a53_2>;
126 };
127 core3 {
128 cpu = <&a53_3>;
129 };
130 };
131 };
133 a57_0: cpu@0 {
134 compatible = "arm,cortex-a57";
135 reg = <0x0>;
136 device_type = "cpu";
137 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
138 next-level-cache = <&L2_CA57>;
139 enable-method = "psci";
140 dynamic-power-coefficient = <854>;
141 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
142 operating-points-v2 = <&cluster0_opp>;
143 capacity-dmips-mhz = <1024>;
144 #cooling-cells = <2>;
145 };
147 a57_1: cpu@1 {
148 compatible = "arm,cortex-a57";
149 reg = <0x1>;
150 device_type = "cpu";
151 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
152 next-level-cache = <&L2_CA57>;
153 enable-method = "psci";
154 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
155 operating-points-v2 = <&cluster0_opp>;
156 capacity-dmips-mhz = <1024>;
157 #cooling-cells = <2>;
158 };
160 a53_0: cpu@100 {
161 compatible = "arm,cortex-a53";
162 reg = <0x100>;
163 device_type = "cpu";
164 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
165 next-level-cache = <&L2_CA53>;
166 enable-method = "psci";
167 #cooling-cells = <2>;
168 dynamic-power-coefficient = <277>;
169 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
170 operating-points-v2 = <&cluster1_opp>;
171 capacity-dmips-mhz = <560>;
172 };
174 a53_1: cpu@101 {
175 compatible = "arm,cortex-a53";
176 reg = <0x101>;
177 device_type = "cpu";
178 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
179 next-level-cache = <&L2_CA53>;
180 enable-method = "psci";
181 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
182 operating-points-v2 = <&cluster1_opp>;
183 capacity-dmips-mhz = <560>;
184 };
186 a53_2: cpu@102 {
187 compatible = "arm,cortex-a53";
188 reg = <0x102>;
189 device_type = "cpu";
190 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
191 next-level-cache = <&L2_CA53>;
192 enable-method = "psci";
193 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
194 operating-points-v2 = <&cluster1_opp>;
195 capacity-dmips-mhz = <560>;
196 };
198 a53_3: cpu@103 {
199 compatible = "arm,cortex-a53";
200 reg = <0x103>;
201 device_type = "cpu";
202 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
203 next-level-cache = <&L2_CA53>;
204 enable-method = "psci";
205 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
206 operating-points-v2 = <&cluster1_opp>;
207 capacity-dmips-mhz = <560>;
208 };
210 L2_CA57: cache-controller-0 {
211 compatible = "cache";
212 power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
213 cache-unified;
214 cache-level = <2>;
215 };
217 L2_CA53: cache-controller-1 {
218 compatible = "cache";
219 power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
220 cache-unified;
221 cache-level = <2>;
222 };
223 };
225 extal_clk: extal {
226 compatible = "fixed-clock";
227 #clock-cells = <0>;
228 /* This value must be overridden by the board */
229 clock-frequency = <0>;
230 };
232 extalr_clk: extalr {
233 compatible = "fixed-clock";
234 #clock-cells = <0>;
235 /* This value must be overridden by the board */
236 clock-frequency = <0>;
237 };
239 /* External PCIe clock - can be overridden by the board */
240 pcie_bus_clk: pcie_bus {
241 compatible = "fixed-clock";
242 #clock-cells = <0>;
243 clock-frequency = <0>;
244 };
246 pmu_a53 {
247 compatible = "arm,cortex-a53-pmu";
248 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
249 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
250 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
251 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
252 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
253 };
255 pmu_a57 {
256 compatible = "arm,cortex-a57-pmu";
257 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
258 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
259 interrupt-affinity = <&a57_0>, <&a57_1>;
260 };
262 psci {
263 compatible = "arm,psci-1.0", "arm,psci-0.2";
264 method = "smc";
265 };
267 /* External SCIF clock - to be overridden by boards that provide it */
268 scif_clk: scif {
269 compatible = "fixed-clock";
270 #clock-cells = <0>;
271 clock-frequency = <0>;
272 };
274 soc {
275 compatible = "simple-bus";
276 interrupt-parent = <&gic>;
277 #address-cells = <2>;
278 #size-cells = <2>;
279 ranges;
281 rwdt: watchdog@e6020000 {
282 compatible = "renesas,r8a774a1-wdt",
283 "renesas,rcar-gen3-wdt";
284 reg = <0 0xe6020000 0 0x0c>;
285 clocks = <&cpg CPG_MOD 402>;
286 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
287 resets = <&cpg 402>;
288 status = "disabled";
289 };
291 gpio0: gpio@e6050000 {
292 compatible = "renesas,gpio-r8a774a1",
293 "renesas,rcar-gen3-gpio";
294 reg = <0 0xe6050000 0 0x50>;
295 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
296 #gpio-cells = <2>;
297 gpio-controller;
298 gpio-ranges = <&pfc 0 0 16>;
299 #interrupt-cells = <2>;
300 interrupt-controller;
301 clocks = <&cpg CPG_MOD 912>;
302 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
303 resets = <&cpg 912>;
304 };
306 gpio1: gpio@e6051000 {
307 compatible = "renesas,gpio-r8a774a1",
308 "renesas,rcar-gen3-gpio";
309 reg = <0 0xe6051000 0 0x50>;
310 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
311 #gpio-cells = <2>;
312 gpio-controller;
313 gpio-ranges = <&pfc 0 32 29>;
314 #interrupt-cells = <2>;
315 interrupt-controller;
316 clocks = <&cpg CPG_MOD 911>;
317 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
318 resets = <&cpg 911>;
319 };
321 gpio2: gpio@e6052000 {
322 compatible = "renesas,gpio-r8a774a1",
323 "renesas,rcar-gen3-gpio";
324 reg = <0 0xe6052000 0 0x50>;
325 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
326 #gpio-cells = <2>;
327 gpio-controller;
328 gpio-ranges = <&pfc 0 64 15>;
329 #interrupt-cells = <2>;
330 interrupt-controller;
331 clocks = <&cpg CPG_MOD 910>;
332 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
333 resets = <&cpg 910>;
334 };
336 gpio3: gpio@e6053000 {
337 compatible = "renesas,gpio-r8a774a1",
338 "renesas,rcar-gen3-gpio";
339 reg = <0 0xe6053000 0 0x50>;
340 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
341 #gpio-cells = <2>;
342 gpio-controller;
343 gpio-ranges = <&pfc 0 96 16>;
344 #interrupt-cells = <2>;
345 interrupt-controller;
346 clocks = <&cpg CPG_MOD 909>;
347 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
348 resets = <&cpg 909>;
349 };
351 gpio4: gpio@e6054000 {
352 compatible = "renesas,gpio-r8a774a1",
353 "renesas,rcar-gen3-gpio";
354 reg = <0 0xe6054000 0 0x50>;
355 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
356 #gpio-cells = <2>;
357 gpio-controller;
358 gpio-ranges = <&pfc 0 128 18>;
359 #interrupt-cells = <2>;
360 interrupt-controller;
361 clocks = <&cpg CPG_MOD 908>;
362 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
363 resets = <&cpg 908>;
364 };
366 gpio5: gpio@e6055000 {
367 compatible = "renesas,gpio-r8a774a1",
368 "renesas,rcar-gen3-gpio";
369 reg = <0 0xe6055000 0 0x50>;
370 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
371 #gpio-cells = <2>;
372 gpio-controller;
373 gpio-ranges = <&pfc 0 160 26>;
374 #interrupt-cells = <2>;
375 interrupt-controller;
376 clocks = <&cpg CPG_MOD 907>;
377 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
378 resets = <&cpg 907>;
379 };
381 gpio6: gpio@e6055400 {
382 compatible = "renesas,gpio-r8a774a1",
383 "renesas,rcar-gen3-gpio";
384 reg = <0 0xe6055400 0 0x50>;
385 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
386 #gpio-cells = <2>;
387 gpio-controller;
388 gpio-ranges = <&pfc 0 192 32>;
389 #interrupt-cells = <2>;
390 interrupt-controller;
391 clocks = <&cpg CPG_MOD 906>;
392 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
393 resets = <&cpg 906>;
394 };
396 gpio7: gpio@e6055800 {
397 compatible = "renesas,gpio-r8a774a1",
398 "renesas,rcar-gen3-gpio";
399 reg = <0 0xe6055800 0 0x50>;
400 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
401 #gpio-cells = <2>;
402 gpio-controller;
403 gpio-ranges = <&pfc 0 224 4>;
404 #interrupt-cells = <2>;
405 interrupt-controller;
406 clocks = <&cpg CPG_MOD 905>;
407 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
408 resets = <&cpg 905>;
409 };
411 pfc: pinctrl@e6060000 {
412 compatible = "renesas,pfc-r8a774a1";
413 reg = <0 0xe6060000 0 0x50c>;
414 };
416 cmt0: timer@e60f0000 {
417 compatible = "renesas,r8a774a1-cmt0",
418 "renesas,rcar-gen3-cmt0";
419 reg = <0 0xe60f0000 0 0x1004>;
420 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&cpg CPG_MOD 303>;
423 clock-names = "fck";
424 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
425 resets = <&cpg 303>;
426 status = "disabled";
427 };
429 cmt1: timer@e6130000 {
430 compatible = "renesas,r8a774a1-cmt1",
431 "renesas,rcar-gen3-cmt1";
432 reg = <0 0xe6130000 0 0x1004>;
433 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&cpg CPG_MOD 302>;
442 clock-names = "fck";
443 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
444 resets = <&cpg 302>;
445 status = "disabled";
446 };
448 cmt2: timer@e6140000 {
449 compatible = "renesas,r8a774a1-cmt1",
450 "renesas,rcar-gen3-cmt1";
451 reg = <0 0xe6140000 0 0x1004>;
452 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 301>;
461 clock-names = "fck";
462 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
463 resets = <&cpg 301>;
464 status = "disabled";
465 };
467 cmt3: timer@e6148000 {
468 compatible = "renesas,r8a774a1-cmt1",
469 "renesas,rcar-gen3-cmt1";
470 reg = <0 0xe6148000 0 0x1004>;
471 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cpg CPG_MOD 300>;
480 clock-names = "fck";
481 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
482 resets = <&cpg 300>;
483 status = "disabled";
484 };
486 cpg: clock-controller@e6150000 {
487 compatible = "renesas,r8a774a1-cpg-mssr";
488 reg = <0 0xe6150000 0 0x0bb0>;
489 clocks = <&extal_clk>, <&extalr_clk>;
490 clock-names = "extal", "extalr";
491 #clock-cells = <2>;
492 #power-domain-cells = <0>;
493 #reset-cells = <1>;
494 };
496 rst: reset-controller@e6160000 {
497 compatible = "renesas,r8a774a1-rst";
498 reg = <0 0xe6160000 0 0x018c>;
499 };
501 sysc: system-controller@e6180000 {
502 compatible = "renesas,r8a774a1-sysc";
503 reg = <0 0xe6180000 0 0x0400>;
504 #power-domain-cells = <1>;
505 };
507 tsc: thermal@e6198000 {
508 compatible = "renesas,r8a774a1-thermal";
509 reg = <0 0xe6198000 0 0x100>,
510 <0 0xe61a0000 0 0x100>,
511 <0 0xe61a8000 0 0x100>;
512 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&cpg CPG_MOD 522>;
516 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
517 resets = <&cpg 522>;
518 #thermal-sensor-cells = <1>;
519 };
521 intc_ex: interrupt-controller@e61c0000 {
522 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
523 #interrupt-cells = <2>;
524 interrupt-controller;
525 reg = <0 0xe61c0000 0 0x200>;
526 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cpg CPG_MOD 407>;
533 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
534 resets = <&cpg 407>;
535 };
537 tmu0: timer@e61e0000 {
538 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
539 reg = <0 0xe61e0000 0 0x30>;
540 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cpg CPG_MOD 125>;
544 clock-names = "fck";
545 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
546 resets = <&cpg 125>;
547 status = "disabled";
548 };
550 tmu1: timer@e6fc0000 {
551 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
552 reg = <0 0xe6fc0000 0 0x30>;
553 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&cpg CPG_MOD 124>;
557 clock-names = "fck";
558 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
559 resets = <&cpg 124>;
560 status = "disabled";
561 };
563 tmu2: timer@e6fd0000 {
564 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
565 reg = <0 0xe6fd0000 0 0x30>;
566 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&cpg CPG_MOD 123>;
570 clock-names = "fck";
571 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
572 resets = <&cpg 123>;
573 status = "disabled";
574 };
576 tmu3: timer@e6fe0000 {
577 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
578 reg = <0 0xe6fe0000 0 0x30>;
579 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&cpg CPG_MOD 122>;
583 clock-names = "fck";
584 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
585 resets = <&cpg 122>;
586 status = "disabled";
587 };
589 tmu4: timer@ffc00000 {
590 compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
591 reg = <0 0xffc00000 0 0x30>;
592 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&cpg CPG_MOD 121>;
596 clock-names = "fck";
597 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
598 resets = <&cpg 121>;
599 status = "disabled";
600 };
602 i2c0: i2c@e6500000 {
603 #address-cells = <1>;
604 #size-cells = <0>;
605 compatible = "renesas,i2c-r8a774a1",
606 "renesas,rcar-gen3-i2c";
607 reg = <0 0xe6500000 0 0x40>;
608 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&cpg CPG_MOD 931>;
610 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
611 resets = <&cpg 931>;
612 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
613 <&dmac2 0x91>, <&dmac2 0x90>;
614 dma-names = "tx", "rx", "tx", "rx";
615 i2c-scl-internal-delay-ns = <110>;
616 status = "disabled";
617 };
619 i2c1: i2c@e6508000 {
620 #address-cells = <1>;
621 #size-cells = <0>;
622 compatible = "renesas,i2c-r8a774a1",
623 "renesas,rcar-gen3-i2c";
624 reg = <0 0xe6508000 0 0x40>;
625 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&cpg CPG_MOD 930>;
627 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
628 resets = <&cpg 930>;
629 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
630 <&dmac2 0x93>, <&dmac2 0x92>;
631 dma-names = "tx", "rx", "tx", "rx";
632 i2c-scl-internal-delay-ns = <6>;
633 status = "disabled";
634 };
636 i2c2: i2c@e6510000 {
637 #address-cells = <1>;
638 #size-cells = <0>;
639 compatible = "renesas,i2c-r8a774a1",
640 "renesas,rcar-gen3-i2c";
641 reg = <0 0xe6510000 0 0x40>;
642 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&cpg CPG_MOD 929>;
644 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
645 resets = <&cpg 929>;
646 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
647 <&dmac2 0x95>, <&dmac2 0x94>;
648 dma-names = "tx", "rx", "tx", "rx";
649 i2c-scl-internal-delay-ns = <6>;
650 status = "disabled";
651 };
653 i2c3: i2c@e66d0000 {
654 #address-cells = <1>;
655 #size-cells = <0>;
656 compatible = "renesas,i2c-r8a774a1",
657 "renesas,rcar-gen3-i2c";
658 reg = <0 0xe66d0000 0 0x40>;
659 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&cpg CPG_MOD 928>;
661 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
662 resets = <&cpg 928>;
663 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
664 dma-names = "tx", "rx";
665 i2c-scl-internal-delay-ns = <110>;
666 status = "disabled";
667 };
669 i2c4: i2c@e66d8000 {
670 #address-cells = <1>;
671 #size-cells = <0>;
672 compatible = "renesas,i2c-r8a774a1",
673 "renesas,rcar-gen3-i2c";
674 reg = <0 0xe66d8000 0 0x40>;
675 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&cpg CPG_MOD 927>;
677 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
678 resets = <&cpg 927>;
679 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
680 dma-names = "tx", "rx";
681 i2c-scl-internal-delay-ns = <110>;
682 status = "disabled";
683 };
685 i2c5: i2c@e66e0000 {
686 #address-cells = <1>;
687 #size-cells = <0>;
688 compatible = "renesas,i2c-r8a774a1",
689 "renesas,rcar-gen3-i2c";
690 reg = <0 0xe66e0000 0 0x40>;
691 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&cpg CPG_MOD 919>;
693 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
694 resets = <&cpg 919>;
695 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
696 dma-names = "tx", "rx";
697 i2c-scl-internal-delay-ns = <110>;
698 status = "disabled";
699 };
701 i2c6: i2c@e66e8000 {
702 #address-cells = <1>;
703 #size-cells = <0>;
704 compatible = "renesas,i2c-r8a774a1",
705 "renesas,rcar-gen3-i2c";
706 reg = <0 0xe66e8000 0 0x40>;
707 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&cpg CPG_MOD 918>;
709 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
710 resets = <&cpg 918>;
711 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
712 dma-names = "tx", "rx";
713 i2c-scl-internal-delay-ns = <6>;
714 status = "disabled";
715 };
717 i2c_dvfs: i2c@e60b0000 {
718 #address-cells = <1>;
719 #size-cells = <0>;
720 compatible = "renesas,iic-r8a774a1",
721 "renesas,rcar-gen3-iic",
722 "renesas,rmobile-iic";
723 reg = <0 0xe60b0000 0 0x425>;
724 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&cpg CPG_MOD 926>;
726 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
727 resets = <&cpg 926>;
728 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
729 dma-names = "tx", "rx";
730 status = "disabled";
731 };
733 hscif0: serial@e6540000 {
734 compatible = "renesas,hscif-r8a774a1",
735 "renesas,rcar-gen3-hscif",
736 "renesas,hscif";
737 reg = <0 0xe6540000 0 0x60>;
738 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&cpg CPG_MOD 520>,
740 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
741 <&scif_clk>;
742 clock-names = "fck", "brg_int", "scif_clk";
743 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
744 <&dmac2 0x31>, <&dmac2 0x30>;
745 dma-names = "tx", "rx", "tx", "rx";
746 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
747 resets = <&cpg 520>;
748 status = "disabled";
749 };
751 hscif1: serial@e6550000 {
752 compatible = "renesas,hscif-r8a774a1",
753 "renesas,rcar-gen3-hscif",
754 "renesas,hscif";
755 reg = <0 0xe6550000 0 0x60>;
756 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&cpg CPG_MOD 519>,
758 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
759 <&scif_clk>;
760 clock-names = "fck", "brg_int", "scif_clk";
761 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
762 <&dmac2 0x33>, <&dmac2 0x32>;
763 dma-names = "tx", "rx", "tx", "rx";
764 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
765 resets = <&cpg 519>;
766 status = "disabled";
767 };
769 hscif2: serial@e6560000 {
770 compatible = "renesas,hscif-r8a774a1",
771 "renesas,rcar-gen3-hscif",
772 "renesas,hscif";
773 reg = <0 0xe6560000 0 0x60>;
774 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&cpg CPG_MOD 518>,
776 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
777 <&scif_clk>;
778 clock-names = "fck", "brg_int", "scif_clk";
779 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
780 <&dmac2 0x35>, <&dmac2 0x34>;
781 dma-names = "tx", "rx", "tx", "rx";
782 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
783 resets = <&cpg 518>;
784 status = "disabled";
785 };
787 hscif3: serial@e66a0000 {
788 compatible = "renesas,hscif-r8a774a1",
789 "renesas,rcar-gen3-hscif",
790 "renesas,hscif";
791 reg = <0 0xe66a0000 0 0x60>;
792 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&cpg CPG_MOD 517>,
794 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
795 <&scif_clk>;
796 clock-names = "fck", "brg_int", "scif_clk";
797 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
798 dma-names = "tx", "rx";
799 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
800 resets = <&cpg 517>;
801 status = "disabled";
802 };
804 hscif4: serial@e66b0000 {
805 compatible = "renesas,hscif-r8a774a1",
806 "renesas,rcar-gen3-hscif",
807 "renesas,hscif";
808 reg = <0 0xe66b0000 0 0x60>;
809 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&cpg CPG_MOD 516>,
811 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
812 <&scif_clk>;
813 clock-names = "fck", "brg_int", "scif_clk";
814 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
815 dma-names = "tx", "rx";
816 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
817 resets = <&cpg 516>;
818 status = "disabled";
819 };
821 hsusb: usb@e6590000 {
822 compatible = "renesas,usbhs-r8a774a1",
823 "renesas,rcar-gen3-usbhs";
824 reg = <0 0xe6590000 0 0x200>;
825 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
827 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
828 <&usb_dmac1 0>, <&usb_dmac1 1>;
829 dma-names = "ch0", "ch1", "ch2", "ch3";
830 renesas,buswait = <11>;
831 phys = <&usb2_phy0 3>;
832 phy-names = "usb";
833 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
834 resets = <&cpg 704>, <&cpg 703>;
835 status = "disabled";
836 };
838 usb_dmac0: dma-controller@e65a0000 {
839 compatible = "renesas,r8a774a1-usb-dmac",
840 "renesas,usb-dmac";
841 reg = <0 0xe65a0000 0 0x100>;
842 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
843 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
844 interrupt-names = "ch0", "ch1";
845 clocks = <&cpg CPG_MOD 330>;
846 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
847 resets = <&cpg 330>;
848 #dma-cells = <1>;
849 dma-channels = <2>;
850 };
852 usb_dmac1: dma-controller@e65b0000 {
853 compatible = "renesas,r8a774a1-usb-dmac",
854 "renesas,usb-dmac";
855 reg = <0 0xe65b0000 0 0x100>;
856 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
858 interrupt-names = "ch0", "ch1";
859 clocks = <&cpg CPG_MOD 331>;
860 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
861 resets = <&cpg 331>;
862 #dma-cells = <1>;
863 dma-channels = <2>;
864 };
866 usb3_phy0: usb-phy@e65ee000 {
867 compatible = "renesas,r8a774a1-usb3-phy",
868 "renesas,rcar-gen3-usb3-phy";
869 reg = <0 0xe65ee000 0 0x90>;
870 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
871 <&usb_extal_clk>;
872 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
873 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
874 resets = <&cpg 328>;
875 #phy-cells = <0>;
876 status = "disabled";
877 };
879 dmac0: dma-controller@e6700000 {
880 compatible = "renesas,dmac-r8a774a1",
881 "renesas,rcar-dmac";
882 reg = <0 0xe6700000 0 0x10000>;
883 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
886 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
887 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
893 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
894 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
895 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
900 interrupt-names = "error",
901 "ch0", "ch1", "ch2", "ch3",
902 "ch4", "ch5", "ch6", "ch7",
903 "ch8", "ch9", "ch10", "ch11",
904 "ch12", "ch13", "ch14", "ch15";
905 clocks = <&cpg CPG_MOD 219>;
906 clock-names = "fck";
907 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
908 resets = <&cpg 219>;
909 #dma-cells = <1>;
910 dma-channels = <16>;
911 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
912 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
913 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
914 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
915 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
916 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
917 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
918 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
919 };
921 dmac1: dma-controller@e7300000 {
922 compatible = "renesas,dmac-r8a774a1",
923 "renesas,rcar-dmac";
924 reg = <0 0xe7300000 0 0x10000>;
925 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
942 interrupt-names = "error",
943 "ch0", "ch1", "ch2", "ch3",
944 "ch4", "ch5", "ch6", "ch7",
945 "ch8", "ch9", "ch10", "ch11",
946 "ch12", "ch13", "ch14", "ch15";
947 clocks = <&cpg CPG_MOD 218>;
948 clock-names = "fck";
949 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
950 resets = <&cpg 218>;
951 #dma-cells = <1>;
952 dma-channels = <16>;
953 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
954 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
955 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
956 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
957 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
958 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
959 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
960 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
961 };
963 dmac2: dma-controller@e7310000 {
964 compatible = "renesas,dmac-r8a774a1",
965 "renesas,rcar-dmac";
966 reg = <0 0xe7310000 0 0x10000>;
967 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
984 interrupt-names = "error",
985 "ch0", "ch1", "ch2", "ch3",
986 "ch4", "ch5", "ch6", "ch7",
987 "ch8", "ch9", "ch10", "ch11",
988 "ch12", "ch13", "ch14", "ch15";
989 clocks = <&cpg CPG_MOD 217>;
990 clock-names = "fck";
991 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
992 resets = <&cpg 217>;
993 #dma-cells = <1>;
994 dma-channels = <16>;
995 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
996 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
997 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
998 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
999 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1000 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1001 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1002 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1003 };
1005 ipmmu_ds0: iommu@e6740000 {
1006 compatible = "renesas,ipmmu-r8a774a1";
1007 reg = <0 0xe6740000 0 0x1000>;
1008 renesas,ipmmu-main = <&ipmmu_mm 0>;
1009 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1010 #iommu-cells = <1>;
1011 };
1013 ipmmu_ds1: iommu@e7740000 {
1014 compatible = "renesas,ipmmu-r8a774a1";
1015 reg = <0 0xe7740000 0 0x1000>;
1016 renesas,ipmmu-main = <&ipmmu_mm 1>;
1017 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1018 #iommu-cells = <1>;
1019 };
1021 ipmmu_hc: iommu@e6570000 {
1022 compatible = "renesas,ipmmu-r8a774a1";
1023 reg = <0 0xe6570000 0 0x1000>;
1024 renesas,ipmmu-main = <&ipmmu_mm 2>;
1025 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1026 #iommu-cells = <1>;
1027 };
1029 ipmmu_mm: iommu@e67b0000 {
1030 compatible = "renesas,ipmmu-r8a774a1";
1031 reg = <0 0xe67b0000 0 0x1000>;
1032 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1034 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1035 #iommu-cells = <1>;
1036 };
1038 ipmmu_mp: iommu@ec670000 {
1039 compatible = "renesas,ipmmu-r8a774a1";
1040 reg = <0 0xec670000 0 0x1000>;
1041 renesas,ipmmu-main = <&ipmmu_mm 4>;
1042 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1043 #iommu-cells = <1>;
1044 };
1046 ipmmu_pv0: iommu@fd800000 {
1047 compatible = "renesas,ipmmu-r8a774a1";
1048 reg = <0 0xfd800000 0 0x1000>;
1049 renesas,ipmmu-main = <&ipmmu_mm 5>;
1050 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1051 #iommu-cells = <1>;
1052 };
1054 ipmmu_pv1: iommu@fd950000 {
1055 compatible = "renesas,ipmmu-r8a774a1";
1056 reg = <0 0xfd950000 0 0x1000>;
1057 renesas,ipmmu-main = <&ipmmu_mm 6>;
1058 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1059 #iommu-cells = <1>;
1060 };
1062 ipmmu_vc0: iommu@fe6b0000 {
1063 compatible = "renesas,ipmmu-r8a774a1";
1064 reg = <0 0xfe6b0000 0 0x1000>;
1065 renesas,ipmmu-main = <&ipmmu_mm 8>;
1066 power-domains = <&sysc R8A774A1_PD_A3VC>;
1067 #iommu-cells = <1>;
1068 };
1070 ipmmu_vi0: iommu@febd0000 {
1071 compatible = "renesas,ipmmu-r8a774a1";
1072 reg = <0 0xfebd0000 0 0x1000>;
1073 renesas,ipmmu-main = <&ipmmu_mm 9>;
1074 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1075 #iommu-cells = <1>;
1076 };
1078 avb: ethernet@e6800000 {
1079 compatible = "renesas,etheravb-r8a774a1",
1080 "renesas,etheravb-rcar-gen3";
1081 reg = <0 0xe6800000 0 0x800>;
1082 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1083 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1084 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1085 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1086 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1087 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1089 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1090 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1091 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1092 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1093 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1094 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1100 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1101 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1102 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1103 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1107 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1108 "ch4", "ch5", "ch6", "ch7",
1109 "ch8", "ch9", "ch10", "ch11",
1110 "ch12", "ch13", "ch14", "ch15",
1111 "ch16", "ch17", "ch18", "ch19",
1112 "ch20", "ch21", "ch22", "ch23",
1113 "ch24";
1114 clocks = <&cpg CPG_MOD 812>;
1115 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1116 resets = <&cpg 812>;
1117 phy-mode = "rgmii";
1118 rx-internal-delay-ps = <0>;
1119 tx-internal-delay-ps = <0>;
1120 iommus = <&ipmmu_ds0 16>;
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 status = "disabled";
1124 };
1126 can0: can@e6c30000 {
1127 compatible = "renesas,can-r8a774a1",
1128 "renesas,rcar-gen3-can";
1129 reg = <0 0xe6c30000 0 0x1000>;
1130 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1131 clocks = <&cpg CPG_MOD 916>,
1132 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1133 <&can_clk>;
1134 clock-names = "clkp1", "clkp2", "can_clk";
1135 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1136 assigned-clock-rates = <40000000>;
1137 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1138 resets = <&cpg 916>;
1139 status = "disabled";
1140 };
1142 can1: can@e6c38000 {
1143 compatible = "renesas,can-r8a774a1",
1144 "renesas,rcar-gen3-can";
1145 reg = <0 0xe6c38000 0 0x1000>;
1146 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1147 clocks = <&cpg CPG_MOD 915>,
1148 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1149 <&can_clk>;
1150 clock-names = "clkp1", "clkp2", "can_clk";
1151 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1152 assigned-clock-rates = <40000000>;
1153 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1154 resets = <&cpg 915>;
1155 status = "disabled";
1156 };
1158 canfd: can@e66c0000 {
1159 compatible = "renesas,r8a774a1-canfd",
1160 "renesas,rcar-gen3-canfd";
1161 reg = <0 0xe66c0000 0 0x8000>;
1162 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1164 clocks = <&cpg CPG_MOD 914>,
1165 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
1166 <&can_clk>;
1167 clock-names = "fck", "canfd", "can_clk";
1168 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
1169 assigned-clock-rates = <40000000>;
1170 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1171 resets = <&cpg 914>;
1172 status = "disabled";
1174 channel0 {
1175 status = "disabled";
1176 };
1178 channel1 {
1179 status = "disabled";
1180 };
1181 };
1183 pwm0: pwm@e6e30000 {
1184 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1185 reg = <0 0xe6e30000 0 0x8>;
1186 #pwm-cells = <2>;
1187 clocks = <&cpg CPG_MOD 523>;
1188 resets = <&cpg 523>;
1189 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1190 status = "disabled";
1191 };
1193 pwm1: pwm@e6e31000 {
1194 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1195 reg = <0 0xe6e31000 0 0x8>;
1196 #pwm-cells = <2>;
1197 clocks = <&cpg CPG_MOD 523>;
1198 resets = <&cpg 523>;
1199 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1200 status = "disabled";
1201 };
1203 pwm2: pwm@e6e32000 {
1204 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1205 reg = <0 0xe6e32000 0 0x8>;
1206 #pwm-cells = <2>;
1207 clocks = <&cpg CPG_MOD 523>;
1208 resets = <&cpg 523>;
1209 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1210 status = "disabled";
1211 };
1213 pwm3: pwm@e6e33000 {
1214 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1215 reg = <0 0xe6e33000 0 0x8>;
1216 #pwm-cells = <2>;
1217 clocks = <&cpg CPG_MOD 523>;
1218 resets = <&cpg 523>;
1219 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1220 status = "disabled";
1221 };
1223 pwm4: pwm@e6e34000 {
1224 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1225 reg = <0 0xe6e34000 0 0x8>;
1226 #pwm-cells = <2>;
1227 clocks = <&cpg CPG_MOD 523>;
1228 resets = <&cpg 523>;
1229 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1230 status = "disabled";
1231 };
1233 pwm5: pwm@e6e35000 {
1234 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1235 reg = <0 0xe6e35000 0 0x8>;
1236 #pwm-cells = <2>;
1237 clocks = <&cpg CPG_MOD 523>;
1238 resets = <&cpg 523>;
1239 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1240 status = "disabled";
1241 };
1243 pwm6: pwm@e6e36000 {
1244 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
1245 reg = <0 0xe6e36000 0 0x8>;
1246 #pwm-cells = <2>;
1247 clocks = <&cpg CPG_MOD 523>;
1248 resets = <&cpg 523>;
1249 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1250 status = "disabled";
1251 };
1253 scif0: serial@e6e60000 {
1254 compatible = "renesas,scif-r8a774a1",
1255 "renesas,rcar-gen3-scif", "renesas,scif";
1256 reg = <0 0xe6e60000 0 0x40>;
1257 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&cpg CPG_MOD 207>,
1259 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1260 <&scif_clk>;
1261 clock-names = "fck", "brg_int", "scif_clk";
1262 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1263 <&dmac2 0x51>, <&dmac2 0x50>;
1264 dma-names = "tx", "rx", "tx", "rx";
1265 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1266 resets = <&cpg 207>;
1267 status = "disabled";
1268 };
1270 scif1: serial@e6e68000 {
1271 compatible = "renesas,scif-r8a774a1",
1272 "renesas,rcar-gen3-scif", "renesas,scif";
1273 reg = <0 0xe6e68000 0 0x40>;
1274 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1275 clocks = <&cpg CPG_MOD 206>,
1276 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1277 <&scif_clk>;
1278 clock-names = "fck", "brg_int", "scif_clk";
1279 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1280 <&dmac2 0x53>, <&dmac2 0x52>;
1281 dma-names = "tx", "rx", "tx", "rx";
1282 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1283 resets = <&cpg 206>;
1284 status = "disabled";
1285 };
1287 scif2: serial@e6e88000 {
1288 compatible = "renesas,scif-r8a774a1",
1289 "renesas,rcar-gen3-scif", "renesas,scif";
1290 reg = <0 0xe6e88000 0 0x40>;
1291 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&cpg CPG_MOD 310>,
1293 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1294 <&scif_clk>;
1295 clock-names = "fck", "brg_int", "scif_clk";
1296 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1297 <&dmac2 0x13>, <&dmac2 0x12>;
1298 dma-names = "tx", "rx", "tx", "rx";
1299 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1300 resets = <&cpg 310>;
1301 status = "disabled";
1302 };
1304 scif3: serial@e6c50000 {
1305 compatible = "renesas,scif-r8a774a1",
1306 "renesas,rcar-gen3-scif", "renesas,scif";
1307 reg = <0 0xe6c50000 0 0x40>;
1308 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1309 clocks = <&cpg CPG_MOD 204>,
1310 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1311 <&scif_clk>;
1312 clock-names = "fck", "brg_int", "scif_clk";
1313 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1314 dma-names = "tx", "rx";
1315 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1316 resets = <&cpg 204>;
1317 status = "disabled";
1318 };
1320 scif4: serial@e6c40000 {
1321 compatible = "renesas,scif-r8a774a1",
1322 "renesas,rcar-gen3-scif", "renesas,scif";
1323 reg = <0 0xe6c40000 0 0x40>;
1324 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1325 clocks = <&cpg CPG_MOD 203>,
1326 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1327 <&scif_clk>;
1328 clock-names = "fck", "brg_int", "scif_clk";
1329 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1330 dma-names = "tx", "rx";
1331 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1332 resets = <&cpg 203>;
1333 status = "disabled";
1334 };
1336 scif5: serial@e6f30000 {
1337 compatible = "renesas,scif-r8a774a1",
1338 "renesas,rcar-gen3-scif", "renesas,scif";
1339 reg = <0 0xe6f30000 0 0x40>;
1340 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1341 clocks = <&cpg CPG_MOD 202>,
1342 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
1343 <&scif_clk>;
1344 clock-names = "fck", "brg_int", "scif_clk";
1345 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1346 <&dmac2 0x5b>, <&dmac2 0x5a>;
1347 dma-names = "tx", "rx", "tx", "rx";
1348 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1349 resets = <&cpg 202>;
1350 status = "disabled";
1351 };
1353 msiof0: spi@e6e90000 {
1354 compatible = "renesas,msiof-r8a774a1",
1355 "renesas,rcar-gen3-msiof";
1356 reg = <0 0xe6e90000 0 0x0064>;
1357 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&cpg CPG_MOD 211>;
1359 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1360 <&dmac2 0x41>, <&dmac2 0x40>;
1361 dma-names = "tx", "rx", "tx", "rx";
1362 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1363 resets = <&cpg 211>;
1364 #address-cells = <1>;
1365 #size-cells = <0>;
1366 status = "disabled";
1367 };
1369 msiof1: spi@e6ea0000 {
1370 compatible = "renesas,msiof-r8a774a1",
1371 "renesas,rcar-gen3-msiof";
1372 reg = <0 0xe6ea0000 0 0x0064>;
1373 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1374 clocks = <&cpg CPG_MOD 210>;
1375 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1376 <&dmac2 0x43>, <&dmac2 0x42>;
1377 dma-names = "tx", "rx", "tx", "rx";
1378 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1379 resets = <&cpg 210>;
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1382 status = "disabled";
1383 };
1385 msiof2: spi@e6c00000 {
1386 compatible = "renesas,msiof-r8a774a1",
1387 "renesas,rcar-gen3-msiof";
1388 reg = <0 0xe6c00000 0 0x0064>;
1389 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1390 clocks = <&cpg CPG_MOD 209>;
1391 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1392 dma-names = "tx", "rx";
1393 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1394 resets = <&cpg 209>;
1395 #address-cells = <1>;
1396 #size-cells = <0>;
1397 status = "disabled";
1398 };
1400 msiof3: spi@e6c10000 {
1401 compatible = "renesas,msiof-r8a774a1",
1402 "renesas,rcar-gen3-msiof";
1403 reg = <0 0xe6c10000 0 0x0064>;
1404 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1405 clocks = <&cpg CPG_MOD 208>;
1406 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1407 dma-names = "tx", "rx";
1408 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1409 resets = <&cpg 208>;
1410 #address-cells = <1>;
1411 #size-cells = <0>;
1412 status = "disabled";
1413 };
1415 vin0: video@e6ef0000 {
1416 compatible = "renesas,vin-r8a774a1";
1417 reg = <0 0xe6ef0000 0 0x1000>;
1418 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&cpg CPG_MOD 811>;
1420 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1421 resets = <&cpg 811>;
1422 renesas,id = <0>;
1423 status = "disabled";
1425 ports {
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1429 port@1 {
1430 #address-cells = <1>;
1431 #size-cells = <0>;
1433 reg = <1>;
1435 vin0csi20: endpoint@0 {
1436 reg = <0>;
1437 remote-endpoint = <&csi20vin0>;
1438 };
1439 vin0csi40: endpoint@2 {
1440 reg = <2>;
1441 remote-endpoint = <&csi40vin0>;
1442 };
1443 };
1444 };
1445 };
1447 vin1: video@e6ef1000 {
1448 compatible = "renesas,vin-r8a774a1";
1449 reg = <0 0xe6ef1000 0 0x1000>;
1450 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1451 clocks = <&cpg CPG_MOD 810>;
1452 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1453 resets = <&cpg 810>;
1454 renesas,id = <1>;
1455 status = "disabled";
1457 ports {
1458 #address-cells = <1>;
1459 #size-cells = <0>;
1461 port@1 {
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1465 reg = <1>;
1467 vin1csi20: endpoint@0 {
1468 reg = <0>;
1469 remote-endpoint = <&csi20vin1>;
1470 };
1471 vin1csi40: endpoint@2 {
1472 reg = <2>;
1473 remote-endpoint = <&csi40vin1>;
1474 };
1475 };
1476 };
1477 };
1479 vin2: video@e6ef2000 {
1480 compatible = "renesas,vin-r8a774a1";
1481 reg = <0 0xe6ef2000 0 0x1000>;
1482 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1483 clocks = <&cpg CPG_MOD 809>;
1484 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1485 resets = <&cpg 809>;
1486 renesas,id = <2>;
1487 status = "disabled";
1489 ports {
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1493 port@1 {
1494 #address-cells = <1>;
1495 #size-cells = <0>;
1497 reg = <1>;
1499 vin2csi20: endpoint@0 {
1500 reg = <0>;
1501 remote-endpoint = <&csi20vin2>;
1502 };
1503 vin2csi40: endpoint@2 {
1504 reg = <2>;
1505 remote-endpoint = <&csi40vin2>;
1506 };
1507 };
1508 };
1509 };
1511 vin3: video@e6ef3000 {
1512 compatible = "renesas,vin-r8a774a1";
1513 reg = <0 0xe6ef3000 0 0x1000>;
1514 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1515 clocks = <&cpg CPG_MOD 808>;
1516 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1517 resets = <&cpg 808>;
1518 renesas,id = <3>;
1519 status = "disabled";
1521 ports {
1522 #address-cells = <1>;
1523 #size-cells = <0>;
1525 port@1 {
1526 #address-cells = <1>;
1527 #size-cells = <0>;
1529 reg = <1>;
1531 vin3csi20: endpoint@0 {
1532 reg = <0>;
1533 remote-endpoint = <&csi20vin3>;
1534 };
1535 vin3csi40: endpoint@2 {
1536 reg = <2>;
1537 remote-endpoint = <&csi40vin3>;
1538 };
1539 };
1540 };
1541 };
1543 vin4: video@e6ef4000 {
1544 compatible = "renesas,vin-r8a774a1";
1545 reg = <0 0xe6ef4000 0 0x1000>;
1546 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1547 clocks = <&cpg CPG_MOD 807>;
1548 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1549 resets = <&cpg 807>;
1550 renesas,id = <4>;
1551 status = "disabled";
1553 ports {
1554 #address-cells = <1>;
1555 #size-cells = <0>;
1557 port@1 {
1558 #address-cells = <1>;
1559 #size-cells = <0>;
1561 reg = <1>;
1563 vin4csi20: endpoint@0 {
1564 reg = <0>;
1565 remote-endpoint = <&csi20vin4>;
1566 };
1567 vin4csi40: endpoint@2 {
1568 reg = <2>;
1569 remote-endpoint = <&csi40vin4>;
1570 };
1571 };
1572 };
1573 };
1575 vin5: video@e6ef5000 {
1576 compatible = "renesas,vin-r8a774a1";
1577 reg = <0 0xe6ef5000 0 0x1000>;
1578 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1579 clocks = <&cpg CPG_MOD 806>;
1580 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1581 resets = <&cpg 806>;
1582 renesas,id = <5>;
1583 status = "disabled";
1585 ports {
1586 #address-cells = <1>;
1587 #size-cells = <0>;
1589 port@1 {
1590 #address-cells = <1>;
1591 #size-cells = <0>;
1593 reg = <1>;
1595 vin5csi20: endpoint@0 {
1596 reg = <0>;
1597 remote-endpoint = <&csi20vin5>;
1598 };
1599 vin5csi40: endpoint@2 {
1600 reg = <2>;
1601 remote-endpoint = <&csi40vin5>;
1602 };
1603 };
1604 };
1605 };
1607 vin6: video@e6ef6000 {
1608 compatible = "renesas,vin-r8a774a1";
1609 reg = <0 0xe6ef6000 0 0x1000>;
1610 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1611 clocks = <&cpg CPG_MOD 805>;
1612 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1613 resets = <&cpg 805>;
1614 renesas,id = <6>;
1615 status = "disabled";
1617 ports {
1618 #address-cells = <1>;
1619 #size-cells = <0>;
1621 port@1 {
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1625 reg = <1>;
1627 vin6csi20: endpoint@0 {
1628 reg = <0>;
1629 remote-endpoint = <&csi20vin6>;
1630 };
1631 vin6csi40: endpoint@2 {
1632 reg = <2>;
1633 remote-endpoint = <&csi40vin6>;
1634 };
1635 };
1636 };
1637 };
1639 vin7: video@e6ef7000 {
1640 compatible = "renesas,vin-r8a774a1";
1641 reg = <0 0xe6ef7000 0 0x1000>;
1642 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1643 clocks = <&cpg CPG_MOD 804>;
1644 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1645 resets = <&cpg 804>;
1646 renesas,id = <7>;
1647 status = "disabled";
1649 ports {
1650 #address-cells = <1>;
1651 #size-cells = <0>;
1653 port@1 {
1654 #address-cells = <1>;
1655 #size-cells = <0>;
1657 reg = <1>;
1659 vin7csi20: endpoint@0 {
1660 reg = <0>;
1661 remote-endpoint = <&csi20vin7>;
1662 };
1663 vin7csi40: endpoint@2 {
1664 reg = <2>;
1665 remote-endpoint = <&csi40vin7>;
1666 };
1667 };
1668 };
1669 };
1671 rcar_sound: sound@ec500000 {
1672 /*
1673 * #sound-dai-cells is required
1674 *
1675 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1676 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1677 */
1678 /*
1679 * #clock-cells is required for audio_clkout0/1/2/3
1680 *
1681 * clkout : #clock-cells = <0>; <&rcar_sound>;
1682 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1683 */
1684 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
1685 reg = <0 0xec500000 0 0x1000>, /* SCU */
1686 <0 0xec5a0000 0 0x100>, /* ADG */
1687 <0 0xec540000 0 0x1000>, /* SSIU */
1688 <0 0xec541000 0 0x280>, /* SSI */
1689 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1690 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1692 clocks = <&cpg CPG_MOD 1005>,
1693 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1694 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1695 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1696 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1697 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1698 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1699 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1700 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1701 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1702 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1703 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1704 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1705 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1706 <&audio_clk_a>, <&audio_clk_b>,
1707 <&audio_clk_c>,
1708 <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
1709 clock-names = "ssi-all",
1710 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1711 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1712 "ssi.1", "ssi.0",
1713 "src.9", "src.8", "src.7", "src.6",
1714 "src.5", "src.4", "src.3", "src.2",
1715 "src.1", "src.0",
1716 "mix.1", "mix.0",
1717 "ctu.1", "ctu.0",
1718 "dvc.0", "dvc.1",
1719 "clk_a", "clk_b", "clk_c", "clk_i";
1720 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
1721 resets = <&cpg 1005>,
1722 <&cpg 1006>, <&cpg 1007>,
1723 <&cpg 1008>, <&cpg 1009>,
1724 <&cpg 1010>, <&cpg 1011>,
1725 <&cpg 1012>, <&cpg 1013>,
1726 <&cpg 1014>, <&cpg 1015>;
1727 reset-names = "ssi-all",
1728 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1729 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1730 "ssi.1", "ssi.0";
1731 status = "disabled";
1733 rcar_sound,ctu {
1734 ctu00: ctu-0 { };
1735 ctu01: ctu-1 { };
1736 ctu02: ctu-2 { };
1737 ctu03: ctu-3 { };
1738 ctu10: ctu-4 { };
1739 ctu11: ctu-5 { };
1740 ctu12: ctu-6 { };
1741 ctu13: ctu-7 { };
1742 };
1744 rcar_sound,dvc {
1745 dvc0: dvc-0 {
1746 dmas = <&audma1 0xbc>;
1747 dma-names = "tx";
1748 };
1749 dvc1: dvc-1 {
1750 dmas = <&audma1 0xbe>;
1751 dma-names = "tx";
1752 };
1753 };
1755 rcar_sound,mix {
1756 mix0: mix-0 { };
1757 mix1: mix-1 { };
1758 };
1760 rcar_sound,src {
1761 src0: src-0 {
1762 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1763 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1764 dma-names = "rx", "tx";
1765 };
1766 src1: src-1 {
1767 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1768 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1769 dma-names = "rx", "tx";
1770 };
1771 src2: src-2 {
1772 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1773 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1774 dma-names = "rx", "tx";
1775 };
1776 src3: src-3 {
1777 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1778 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1779 dma-names = "rx", "tx";
1780 };
1781 src4: src-4 {
1782 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1783 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1784 dma-names = "rx", "tx";
1785 };
1786 src5: src-5 {
1787 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1788 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1789 dma-names = "rx", "tx";
1790 };
1791 src6: src-6 {
1792 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1793 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1794 dma-names = "rx", "tx";
1795 };
1796 src7: src-7 {
1797 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1798 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1799 dma-names = "rx", "tx";
1800 };
1801 src8: src-8 {
1802 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1803 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1804 dma-names = "rx", "tx";
1805 };
1806 src9: src-9 {
1807 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1808 dmas = <&audma0 0x97>, <&audma1 0xba>;
1809 dma-names = "rx", "tx";
1810 };
1811 };
1813 rcar_sound,ssi {
1814 ssi0: ssi-0 {
1815 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1816 dmas = <&audma0 0x01>, <&audma1 0x02>;
1817 dma-names = "rx", "tx";
1818 };
1819 ssi1: ssi-1 {
1820 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1821 dmas = <&audma0 0x03>, <&audma1 0x04>;
1822 dma-names = "rx", "tx";
1823 };
1824 ssi2: ssi-2 {
1825 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1826 dmas = <&audma0 0x05>, <&audma1 0x06>;
1827 dma-names = "rx", "tx";
1828 };
1829 ssi3: ssi-3 {
1830 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1831 dmas = <&audma0 0x07>, <&audma1 0x08>;
1832 dma-names = "rx", "tx";
1833 };
1834 ssi4: ssi-4 {
1835 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1836 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1837 dma-names = "rx", "tx";
1838 };
1839 ssi5: ssi-5 {
1840 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1842 dma-names = "rx", "tx";
1843 };
1844 ssi6: ssi-6 {
1845 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1846 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1847 dma-names = "rx", "tx";
1848 };
1849 ssi7: ssi-7 {
1850 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1851 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1852 dma-names = "rx", "tx";
1853 };
1854 ssi8: ssi-8 {
1855 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1856 dmas = <&audma0 0x11>, <&audma1 0x12>;
1857 dma-names = "rx", "tx";
1858 };
1859 ssi9: ssi-9 {
1860 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1861 dmas = <&audma0 0x13>, <&audma1 0x14>;
1862 dma-names = "rx", "tx";
1863 };
1864 };
1866 rcar_sound,ssiu {
1867 ssiu00: ssiu-0 {
1868 dmas = <&audma0 0x15>, <&audma1 0x16>;
1869 dma-names = "rx", "tx";
1870 };
1871 ssiu01: ssiu-1 {
1872 dmas = <&audma0 0x35>, <&audma1 0x36>;
1873 dma-names = "rx", "tx";
1874 };
1875 ssiu02: ssiu-2 {
1876 dmas = <&audma0 0x37>, <&audma1 0x38>;
1877 dma-names = "rx", "tx";
1878 };
1879 ssiu03: ssiu-3 {
1880 dmas = <&audma0 0x47>, <&audma1 0x48>;
1881 dma-names = "rx", "tx";
1882 };
1883 ssiu04: ssiu-4 {
1884 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1885 dma-names = "rx", "tx";
1886 };
1887 ssiu05: ssiu-5 {
1888 dmas = <&audma0 0x43>, <&audma1 0x44>;
1889 dma-names = "rx", "tx";
1890 };
1891 ssiu06: ssiu-6 {
1892 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1893 dma-names = "rx", "tx";
1894 };
1895 ssiu07: ssiu-7 {
1896 dmas = <&audma0 0x53>, <&audma1 0x54>;
1897 dma-names = "rx", "tx";
1898 };
1899 ssiu10: ssiu-8 {
1900 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1901 dma-names = "rx", "tx";
1902 };
1903 ssiu11: ssiu-9 {
1904 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1905 dma-names = "rx", "tx";
1906 };
1907 ssiu12: ssiu-10 {
1908 dmas = <&audma0 0x57>, <&audma1 0x58>;
1909 dma-names = "rx", "tx";
1910 };
1911 ssiu13: ssiu-11 {
1912 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1913 dma-names = "rx", "tx";
1914 };
1915 ssiu14: ssiu-12 {
1916 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1917 dma-names = "rx", "tx";
1918 };
1919 ssiu15: ssiu-13 {
1920 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1921 dma-names = "rx", "tx";
1922 };
1923 ssiu16: ssiu-14 {
1924 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1925 dma-names = "rx", "tx";
1926 };
1927 ssiu17: ssiu-15 {
1928 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1929 dma-names = "rx", "tx";
1930 };
1931 ssiu20: ssiu-16 {
1932 dmas = <&audma0 0x63>, <&audma1 0x64>;
1933 dma-names = "rx", "tx";
1934 };
1935 ssiu21: ssiu-17 {
1936 dmas = <&audma0 0x67>, <&audma1 0x68>;
1937 dma-names = "rx", "tx";
1938 };
1939 ssiu22: ssiu-18 {
1940 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1941 dma-names = "rx", "tx";
1942 };
1943 ssiu23: ssiu-19 {
1944 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1945 dma-names = "rx", "tx";
1946 };
1947 ssiu24: ssiu-20 {
1948 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1949 dma-names = "rx", "tx";
1950 };
1951 ssiu25: ssiu-21 {
1952 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1953 dma-names = "rx", "tx";
1954 };
1955 ssiu26: ssiu-22 {
1956 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1957 dma-names = "rx", "tx";
1958 };
1959 ssiu27: ssiu-23 {
1960 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1961 dma-names = "rx", "tx";
1962 };
1963 ssiu30: ssiu-24 {
1964 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1965 dma-names = "rx", "tx";
1966 };
1967 ssiu31: ssiu-25 {
1968 dmas = <&audma0 0x21>, <&audma1 0x22>;
1969 dma-names = "rx", "tx";
1970 };
1971 ssiu32: ssiu-26 {
1972 dmas = <&audma0 0x23>, <&audma1 0x24>;
1973 dma-names = "rx", "tx";
1974 };
1975 ssiu33: ssiu-27 {
1976 dmas = <&audma0 0x25>, <&audma1 0x26>;
1977 dma-names = "rx", "tx";
1978 };
1979 ssiu34: ssiu-28 {
1980 dmas = <&audma0 0x27>, <&audma1 0x28>;
1981 dma-names = "rx", "tx";
1982 };
1983 ssiu35: ssiu-29 {
1984 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1985 dma-names = "rx", "tx";
1986 };
1987 ssiu36: ssiu-30 {
1988 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1989 dma-names = "rx", "tx";
1990 };
1991 ssiu37: ssiu-31 {
1992 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1993 dma-names = "rx", "tx";
1994 };
1995 ssiu40: ssiu-32 {
1996 dmas = <&audma0 0x71>, <&audma1 0x72>;
1997 dma-names = "rx", "tx";
1998 };
1999 ssiu41: ssiu-33 {
2000 dmas = <&audma0 0x17>, <&audma1 0x18>;
2001 dma-names = "rx", "tx";
2002 };
2003 ssiu42: ssiu-34 {
2004 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2005 dma-names = "rx", "tx";
2006 };
2007 ssiu43: ssiu-35 {
2008 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2009 dma-names = "rx", "tx";
2010 };
2011 ssiu44: ssiu-36 {
2012 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2013 dma-names = "rx", "tx";
2014 };
2015 ssiu45: ssiu-37 {
2016 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2017 dma-names = "rx", "tx";
2018 };
2019 ssiu46: ssiu-38 {
2020 dmas = <&audma0 0x31>, <&audma1 0x32>;
2021 dma-names = "rx", "tx";
2022 };
2023 ssiu47: ssiu-39 {
2024 dmas = <&audma0 0x33>, <&audma1 0x34>;
2025 dma-names = "rx", "tx";
2026 };
2027 ssiu50: ssiu-40 {
2028 dmas = <&audma0 0x73>, <&audma1 0x74>;
2029 dma-names = "rx", "tx";
2030 };
2031 ssiu60: ssiu-41 {
2032 dmas = <&audma0 0x75>, <&audma1 0x76>;
2033 dma-names = "rx", "tx";
2034 };
2035 ssiu70: ssiu-42 {
2036 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2037 dma-names = "rx", "tx";
2038 };
2039 ssiu80: ssiu-43 {
2040 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2041 dma-names = "rx", "tx";
2042 };
2043 ssiu90: ssiu-44 {
2044 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2045 dma-names = "rx", "tx";
2046 };
2047 ssiu91: ssiu-45 {
2048 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2049 dma-names = "rx", "tx";
2050 };
2051 ssiu92: ssiu-46 {
2052 dmas = <&audma0 0x81>, <&audma1 0x82>;
2053 dma-names = "rx", "tx";
2054 };
2055 ssiu93: ssiu-47 {
2056 dmas = <&audma0 0x83>, <&audma1 0x84>;
2057 dma-names = "rx", "tx";
2058 };
2059 ssiu94: ssiu-48 {
2060 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2061 dma-names = "rx", "tx";
2062 };
2063 ssiu95: ssiu-49 {
2064 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2065 dma-names = "rx", "tx";
2066 };
2067 ssiu96: ssiu-50 {
2068 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2069 dma-names = "rx", "tx";
2070 };
2071 ssiu97: ssiu-51 {
2072 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2073 dma-names = "rx", "tx";
2074 };
2075 };
2076 };
2078 audma0: dma-controller@ec700000 {
2079 compatible = "renesas,dmac-r8a774a1",
2080 "renesas,rcar-dmac";
2081 reg = <0 0xec700000 0 0x10000>;
2082 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2083 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2084 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2085 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2086 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2087 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2088 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2089 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2090 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2091 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2092 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2093 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2094 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2095 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2096 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2098 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2099 interrupt-names = "error",
2100 "ch0", "ch1", "ch2", "ch3",
2101 "ch4", "ch5", "ch6", "ch7",
2102 "ch8", "ch9", "ch10", "ch11",
2103 "ch12", "ch13", "ch14", "ch15";
2104 clocks = <&cpg CPG_MOD 502>;
2105 clock-names = "fck";
2106 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2107 resets = <&cpg 502>;
2108 #dma-cells = <1>;
2109 dma-channels = <16>;
2110 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2111 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2112 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2113 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2114 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2115 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2116 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2117 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
2118 };
2120 audma1: dma-controller@ec720000 {
2121 compatible = "renesas,dmac-r8a774a1",
2122 "renesas,rcar-dmac";
2123 reg = <0 0xec720000 0 0x10000>;
2124 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2125 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2126 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2127 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2128 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2129 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2130 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2131 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2132 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2133 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2134 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2135 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2136 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2137 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2138 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2139 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2140 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2141 interrupt-names = "error",
2142 "ch0", "ch1", "ch2", "ch3",
2143 "ch4", "ch5", "ch6", "ch7",
2144 "ch8", "ch9", "ch10", "ch11",
2145 "ch12", "ch13", "ch14", "ch15";
2146 clocks = <&cpg CPG_MOD 501>;
2147 clock-names = "fck";
2148 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2149 resets = <&cpg 501>;
2150 #dma-cells = <1>;
2151 dma-channels = <16>;
2152 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2153 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2154 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2155 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2156 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2157 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2158 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2159 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
2160 };
2162 xhci0: usb@ee000000 {
2163 compatible = "renesas,xhci-r8a774a1",
2164 "renesas,rcar-gen3-xhci";
2165 reg = <0 0xee000000 0 0xc00>;
2166 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2167 clocks = <&cpg CPG_MOD 328>;
2168 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2169 resets = <&cpg 328>;
2170 status = "disabled";
2171 };
2173 usb3_peri0: usb@ee020000 {
2174 compatible = "renesas,r8a774a1-usb3-peri",
2175 "renesas,rcar-gen3-usb3-peri";
2176 reg = <0 0xee020000 0 0x400>;
2177 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2178 clocks = <&cpg CPG_MOD 328>;
2179 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2180 resets = <&cpg 328>;
2181 status = "disabled";
2182 };
2184 ohci0: usb@ee080000 {
2185 compatible = "generic-ohci";
2186 reg = <0 0xee080000 0 0x100>;
2187 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2188 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2189 phys = <&usb2_phy0 1>;
2190 phy-names = "usb";
2191 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2192 resets = <&cpg 703>, <&cpg 704>;
2193 status = "disabled";
2194 };
2196 ohci1: usb@ee0a0000 {
2197 compatible = "generic-ohci";
2198 reg = <0 0xee0a0000 0 0x100>;
2199 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2200 clocks = <&cpg CPG_MOD 702>;
2201 phys = <&usb2_phy1 1>;
2202 phy-names = "usb";
2203 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2204 resets = <&cpg 702>;
2205 status = "disabled";
2206 };
2208 ehci0: usb@ee080100 {
2209 compatible = "generic-ehci";
2210 reg = <0 0xee080100 0 0x100>;
2211 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2212 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2213 phys = <&usb2_phy0 2>;
2214 phy-names = "usb";
2215 companion = <&ohci0>;
2216 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2217 resets = <&cpg 703>, <&cpg 704>;
2218 status = "disabled";
2219 };
2221 ehci1: usb@ee0a0100 {
2222 compatible = "generic-ehci";
2223 reg = <0 0xee0a0100 0 0x100>;
2224 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2225 clocks = <&cpg CPG_MOD 702>;
2226 phys = <&usb2_phy1 2>;
2227 phy-names = "usb";
2228 companion = <&ohci1>;
2229 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2230 resets = <&cpg 702>;
2231 status = "disabled";
2232 };
2234 usb2_phy0: usb-phy@ee080200 {
2235 compatible = "renesas,usb2-phy-r8a774a1",
2236 "renesas,rcar-gen3-usb2-phy";
2237 reg = <0 0xee080200 0 0x700>;
2238 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2239 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2240 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2241 resets = <&cpg 703>, <&cpg 704>;
2242 #phy-cells = <1>;
2243 status = "disabled";
2244 };
2246 usb2_phy1: usb-phy@ee0a0200 {
2247 compatible = "renesas,usb2-phy-r8a774a1",
2248 "renesas,rcar-gen3-usb2-phy";
2249 reg = <0 0xee0a0200 0 0x700>;
2250 clocks = <&cpg CPG_MOD 702>;
2251 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2252 resets = <&cpg 702>;
2253 #phy-cells = <1>;
2254 status = "disabled";
2255 };
2257 sdhi0: mmc@ee100000 {
2258 compatible = "renesas,sdhi-r8a774a1",
2259 "renesas,rcar-gen3-sdhi";
2260 reg = <0 0xee100000 0 0x2000>;
2261 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2262 clocks = <&cpg CPG_MOD 314>;
2263 max-frequency = <200000000>;
2264 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2265 resets = <&cpg 314>;
2266 status = "disabled";
2267 };
2269 sdhi1: mmc@ee120000 {
2270 compatible = "renesas,sdhi-r8a774a1",
2271 "renesas,rcar-gen3-sdhi";
2272 reg = <0 0xee120000 0 0x2000>;
2273 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2274 clocks = <&cpg CPG_MOD 313>;
2275 max-frequency = <200000000>;
2276 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2277 resets = <&cpg 313>;
2278 status = "disabled";
2279 };
2281 sdhi2: mmc@ee140000 {
2282 compatible = "renesas,sdhi-r8a774a1",
2283 "renesas,rcar-gen3-sdhi";
2284 reg = <0 0xee140000 0 0x2000>;
2285 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2286 clocks = <&cpg CPG_MOD 312>;
2287 max-frequency = <200000000>;
2288 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2289 resets = <&cpg 312>;
2290 status = "disabled";
2291 };
2293 sdhi3: mmc@ee160000 {
2294 compatible = "renesas,sdhi-r8a774a1",
2295 "renesas,rcar-gen3-sdhi";
2296 reg = <0 0xee160000 0 0x2000>;
2297 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2298 clocks = <&cpg CPG_MOD 311>;
2299 max-frequency = <200000000>;
2300 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2301 resets = <&cpg 311>;
2302 status = "disabled";
2303 };
2305 gic: interrupt-controller@f1010000 {
2306 compatible = "arm,gic-400";
2307 #interrupt-cells = <3>;
2308 #address-cells = <0>;
2309 interrupt-controller;
2310 reg = <0x0 0xf1010000 0 0x1000>,
2311 <0x0 0xf1020000 0 0x20000>,
2312 <0x0 0xf1040000 0 0x20000>,
2313 <0x0 0xf1060000 0 0x20000>;
2314 interrupts = <GIC_PPI 9
2315 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2316 clocks = <&cpg CPG_MOD 408>;
2317 clock-names = "clk";
2318 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2319 resets = <&cpg 408>;
2320 };
2322 pciec0: pcie@fe000000 {
2323 compatible = "renesas,pcie-r8a774a1",
2324 "renesas,pcie-rcar-gen3";
2325 reg = <0 0xfe000000 0 0x80000>;
2326 #address-cells = <3>;
2327 #size-cells = <2>;
2328 bus-range = <0x00 0xff>;
2329 device_type = "pci";
2330 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2331 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2332 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2333 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2334 /* Map all possible DDR as inbound ranges */
2335 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2336 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2337 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2338 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2339 #interrupt-cells = <1>;
2340 interrupt-map-mask = <0 0 0 0>;
2341 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2342 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2343 clock-names = "pcie", "pcie_bus";
2344 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2345 resets = <&cpg 319>;
2346 status = "disabled";
2347 };
2349 pciec1: pcie@ee800000 {
2350 compatible = "renesas,pcie-r8a774a1",
2351 "renesas,pcie-rcar-gen3";
2352 reg = <0 0xee800000 0 0x80000>;
2353 #address-cells = <3>;
2354 #size-cells = <2>;
2355 bus-range = <0x00 0xff>;
2356 device_type = "pci";
2357 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2358 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2359 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2360 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2361 /* Map all possible DDR as inbound ranges */
2362 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2363 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2364 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2365 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2366 #interrupt-cells = <1>;
2367 interrupt-map-mask = <0 0 0 0>;
2368 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2369 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2370 clock-names = "pcie", "pcie_bus";
2371 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2372 resets = <&cpg 318>;
2373 status = "disabled";
2374 };
2376 pciec0_ep: pcie-ep@fe000000 {
2377 compatible = "renesas,r8a774a1-pcie-ep",
2378 "renesas,rcar-gen3-pcie-ep";
2379 reg = <0x0 0xfe000000 0 0x80000>,
2380 <0x0 0xfe100000 0 0x100000>,
2381 <0x0 0xfe200000 0 0x200000>,
2382 <0x0 0x30000000 0 0x8000000>,
2383 <0x0 0x38000000 0 0x8000000>;
2384 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2385 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2386 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2387 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2388 clocks = <&cpg CPG_MOD 319>;
2389 clock-names = "pcie";
2390 resets = <&cpg 319>;
2391 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2392 status = "disabled";
2393 };
2395 pciec1_ep: pcie-ep@ee800000 {
2396 compatible = "renesas,r8a774a1-pcie-ep",
2397 "renesas,rcar-gen3-pcie-ep";
2398 reg = <0x0 0xee800000 0 0x80000>,
2399 <0x0 0xee900000 0 0x100000>,
2400 <0x0 0xeea00000 0 0x200000>,
2401 <0x0 0xc0000000 0 0x8000000>,
2402 <0x0 0xc8000000 0 0x8000000>;
2403 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2404 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2405 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2406 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2407 clocks = <&cpg CPG_MOD 318>;
2408 clock-names = "pcie";
2409 resets = <&cpg 318>;
2410 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2411 status = "disabled";
2412 };
2414 fdp1@fe940000 {
2415 compatible = "renesas,fdp1";
2416 reg = <0 0xfe940000 0 0x2400>;
2417 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2418 clocks = <&cpg CPG_MOD 119>;
2419 power-domains = <&sysc R8A774A1_PD_A3VC>;
2420 resets = <&cpg 119>;
2421 renesas,fcp = <&fcpf0>;
2422 };
2424 fcpf0: fcp@fe950000 {
2425 compatible = "renesas,fcpf";
2426 reg = <0 0xfe950000 0 0x200>;
2427 clocks = <&cpg CPG_MOD 615>;
2428 power-domains = <&sysc R8A774A1_PD_A3VC>;
2429 resets = <&cpg 615>;
2430 };
2432 fcpvb0: fcp@fe96f000 {
2433 compatible = "renesas,fcpv";
2434 reg = <0 0xfe96f000 0 0x200>;
2435 clocks = <&cpg CPG_MOD 607>;
2436 power-domains = <&sysc R8A774A1_PD_A3VC>;
2437 resets = <&cpg 607>;
2438 };
2440 fcpvd0: fcp@fea27000 {
2441 compatible = "renesas,fcpv";
2442 reg = <0 0xfea27000 0 0x200>;
2443 clocks = <&cpg CPG_MOD 603>;
2444 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2445 resets = <&cpg 603>;
2446 iommus = <&ipmmu_vi0 8>;
2447 };
2449 fcpvd1: fcp@fea2f000 {
2450 compatible = "renesas,fcpv";
2451 reg = <0 0xfea2f000 0 0x200>;
2452 clocks = <&cpg CPG_MOD 602>;
2453 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2454 resets = <&cpg 602>;
2455 iommus = <&ipmmu_vi0 9>;
2456 };
2458 fcpvd2: fcp@fea37000 {
2459 compatible = "renesas,fcpv";
2460 reg = <0 0xfea37000 0 0x200>;
2461 clocks = <&cpg CPG_MOD 601>;
2462 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2463 resets = <&cpg 601>;
2464 iommus = <&ipmmu_vi0 10>;
2465 };
2467 fcpvi0: fcp@fe9af000 {
2468 compatible = "renesas,fcpv";
2469 reg = <0 0xfe9af000 0 0x200>;
2470 clocks = <&cpg CPG_MOD 611>;
2471 power-domains = <&sysc R8A774A1_PD_A3VC>;
2472 resets = <&cpg 611>;
2473 iommus = <&ipmmu_vc0 19>;
2474 };
2476 vspb: vsp@fe960000 {
2477 compatible = "renesas,vsp2";
2478 reg = <0 0xfe960000 0 0x8000>;
2479 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2480 clocks = <&cpg CPG_MOD 626>;
2481 power-domains = <&sysc R8A774A1_PD_A3VC>;
2482 resets = <&cpg 626>;
2484 renesas,fcp = <&fcpvb0>;
2485 };
2487 vspd0: vsp@fea20000 {
2488 compatible = "renesas,vsp2";
2489 reg = <0 0xfea20000 0 0x5000>;
2490 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2491 clocks = <&cpg CPG_MOD 623>;
2492 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2493 resets = <&cpg 623>;
2495 renesas,fcp = <&fcpvd0>;
2496 };
2498 vspd1: vsp@fea28000 {
2499 compatible = "renesas,vsp2";
2500 reg = <0 0xfea28000 0 0x5000>;
2501 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2502 clocks = <&cpg CPG_MOD 622>;
2503 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2504 resets = <&cpg 622>;
2506 renesas,fcp = <&fcpvd1>;
2507 };
2509 vspd2: vsp@fea30000 {
2510 compatible = "renesas,vsp2";
2511 reg = <0 0xfea30000 0 0x5000>;
2512 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2513 clocks = <&cpg CPG_MOD 621>;
2514 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2515 resets = <&cpg 621>;
2517 renesas,fcp = <&fcpvd2>;
2518 };
2520 vspi0: vsp@fe9a0000 {
2521 compatible = "renesas,vsp2";
2522 reg = <0 0xfe9a0000 0 0x8000>;
2523 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2524 clocks = <&cpg CPG_MOD 631>;
2525 power-domains = <&sysc R8A774A1_PD_A3VC>;
2526 resets = <&cpg 631>;
2528 renesas,fcp = <&fcpvi0>;
2529 };
2531 csi20: csi2@fea80000 {
2532 compatible = "renesas,r8a774a1-csi2";
2533 reg = <0 0xfea80000 0 0x10000>;
2534 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2535 clocks = <&cpg CPG_MOD 714>;
2536 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2537 resets = <&cpg 714>;
2538 status = "disabled";
2540 ports {
2541 #address-cells = <1>;
2542 #size-cells = <0>;
2544 port@1 {
2545 #address-cells = <1>;
2546 #size-cells = <0>;
2548 reg = <1>;
2550 csi20vin0: endpoint@0 {
2551 reg = <0>;
2552 remote-endpoint = <&vin0csi20>;
2553 };
2554 csi20vin1: endpoint@1 {
2555 reg = <1>;
2556 remote-endpoint = <&vin1csi20>;
2557 };
2558 csi20vin2: endpoint@2 {
2559 reg = <2>;
2560 remote-endpoint = <&vin2csi20>;
2561 };
2562 csi20vin3: endpoint@3 {
2563 reg = <3>;
2564 remote-endpoint = <&vin3csi20>;
2565 };
2566 csi20vin4: endpoint@4 {
2567 reg = <4>;
2568 remote-endpoint = <&vin4csi20>;
2569 };
2570 csi20vin5: endpoint@5 {
2571 reg = <5>;
2572 remote-endpoint = <&vin5csi20>;
2573 };
2574 csi20vin6: endpoint@6 {
2575 reg = <6>;
2576 remote-endpoint = <&vin6csi20>;
2577 };
2578 csi20vin7: endpoint@7 {
2579 reg = <7>;
2580 remote-endpoint = <&vin7csi20>;
2581 };
2582 };
2583 };
2584 };
2586 csi40: csi2@feaa0000 {
2587 compatible = "renesas,r8a774a1-csi2";
2588 reg = <0 0xfeaa0000 0 0x10000>;
2589 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2590 clocks = <&cpg CPG_MOD 716>;
2591 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2592 resets = <&cpg 716>;
2593 status = "disabled";
2595 ports {
2596 #address-cells = <1>;
2597 #size-cells = <0>;
2599 port@1 {
2600 #address-cells = <1>;
2601 #size-cells = <0>;
2603 reg = <1>;
2605 csi40vin0: endpoint@0 {
2606 reg = <0>;
2607 remote-endpoint = <&vin0csi40>;
2608 };
2609 csi40vin1: endpoint@1 {
2610 reg = <1>;
2611 remote-endpoint = <&vin1csi40>;
2612 };
2613 csi40vin2: endpoint@2 {
2614 reg = <2>;
2615 remote-endpoint = <&vin2csi40>;
2616 };
2617 csi40vin3: endpoint@3 {
2618 reg = <3>;
2619 remote-endpoint = <&vin3csi40>;
2620 };
2621 csi40vin4: endpoint@4 {
2622 reg = <4>;
2623 remote-endpoint = <&vin4csi40>;
2624 };
2625 csi40vin5: endpoint@5 {
2626 reg = <5>;
2627 remote-endpoint = <&vin5csi40>;
2628 };
2629 csi40vin6: endpoint@6 {
2630 reg = <6>;
2631 remote-endpoint = <&vin6csi40>;
2632 };
2633 csi40vin7: endpoint@7 {
2634 reg = <7>;
2635 remote-endpoint = <&vin7csi40>;
2636 };
2637 };
2639 };
2640 };
2642 hdmi0: hdmi@fead0000 {
2643 compatible = "renesas,r8a774a1-hdmi",
2644 "renesas,rcar-gen3-hdmi";
2645 reg = <0 0xfead0000 0 0x10000>;
2646 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2647 clocks = <&cpg CPG_MOD 729>,
2648 <&cpg CPG_CORE R8A774A1_CLK_HDMI>;
2649 clock-names = "iahb", "isfr";
2650 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2651 resets = <&cpg 729>;
2652 status = "disabled";
2654 ports {
2655 #address-cells = <1>;
2656 #size-cells = <0>;
2657 port@0 {
2658 reg = <0>;
2659 dw_hdmi0_in: endpoint {
2660 remote-endpoint = <&du_out_hdmi0>;
2661 };
2662 };
2663 port@1 {
2664 reg = <1>;
2665 };
2666 port@2 {
2667 /* HDMI sound */
2668 reg = <2>;
2669 };
2670 };
2671 };
2673 du: display@feb00000 {
2674 compatible = "renesas,du-r8a774a1";
2675 reg = <0 0xfeb00000 0 0x70000>;
2676 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2677 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2678 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2679 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2680 <&cpg CPG_MOD 722>;
2681 clock-names = "du.0", "du.1", "du.2";
2682 resets = <&cpg 724>, <&cpg 722>;
2683 reset-names = "du.0", "du.2";
2684 status = "disabled";
2686 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2688 ports {
2689 #address-cells = <1>;
2690 #size-cells = <0>;
2692 port@0 {
2693 reg = <0>;
2694 du_out_rgb: endpoint {
2695 };
2696 };
2697 port@1 {
2698 reg = <1>;
2699 du_out_hdmi0: endpoint {
2700 remote-endpoint = <&dw_hdmi0_in>;
2701 };
2702 };
2703 port@2 {
2704 reg = <2>;
2705 du_out_lvds0: endpoint {
2706 remote-endpoint = <&lvds0_in>;
2707 };
2708 };
2709 };
2710 };
2712 lvds0: lvds@feb90000 {
2713 compatible = "renesas,r8a774a1-lvds";
2714 reg = <0 0xfeb90000 0 0x14>;
2715 clocks = <&cpg CPG_MOD 727>;
2716 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
2717 resets = <&cpg 727>;
2718 status = "disabled";
2720 ports {
2721 #address-cells = <1>;
2722 #size-cells = <0>;
2724 port@0 {
2725 reg = <0>;
2726 lvds0_in: endpoint {
2727 remote-endpoint = <&du_out_lvds0>;
2728 };
2729 };
2730 port@1 {
2731 reg = <1>;
2732 lvds0_out: endpoint {
2733 };
2734 };
2735 };
2736 };
2738 prr: chipid@fff00044 {
2739 compatible = "renesas,prr";
2740 reg = <0 0xfff00044 0 4>;
2741 };
2742 };
2744 thermal-zones {
2745 sensor_thermal1: sensor-thermal1 {
2746 polling-delay-passive = <250>;
2747 polling-delay = <1000>;
2748 thermal-sensors = <&tsc 0>;
2749 sustainable-power = <3874>;
2751 trips {
2752 sensor1_crit: sensor1-crit {
2753 temperature = <120000>;
2754 hysteresis = <1000>;
2755 type = "critical";
2756 };
2757 };
2758 };
2760 sensor_thermal2: sensor-thermal2 {
2761 polling-delay-passive = <250>;
2762 polling-delay = <1000>;
2763 thermal-sensors = <&tsc 1>;
2764 sustainable-power = <3874>;
2766 trips {
2767 sensor2_crit: sensor2-crit {
2768 temperature = <120000>;
2769 hysteresis = <1000>;
2770 type = "critical";
2771 };
2772 };
2773 };
2775 sensor_thermal3: sensor-thermal3 {
2776 polling-delay-passive = <250>;
2777 polling-delay = <1000>;
2778 thermal-sensors = <&tsc 2>;
2779 sustainable-power = <3874>;
2781 cooling-maps {
2782 map0 {
2783 trip = <&target>;
2784 cooling-device = <&a57_0 0 2>;
2785 contribution = <1024>;
2786 };
2787 map1 {
2788 trip = <&target>;
2789 cooling-device = <&a53_0 0 2>;
2790 contribution = <1024>;
2791 };
2792 };
2793 trips {
2794 target: trip-point1 {
2795 temperature = <100000>;
2796 hysteresis = <1000>;
2797 type = "passive";
2798 };
2800 sensor3_crit: sensor3-crit {
2801 temperature = <120000>;
2802 hysteresis = <1000>;
2803 type = "critical";
2804 };
2805 };
2806 };
2807 };
2809 timer {
2810 compatible = "arm,armv8-timer";
2811 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2812 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2813 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2814 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
2815 };
2817 /* External USB clocks - can be overridden by the board */
2818 usb3s0_clk: usb3s0 {
2819 compatible = "fixed-clock";
2820 #clock-cells = <0>;
2821 clock-frequency = <0>;
2822 };
2824 usb_extal_clk: usb_extal {
2825 compatible = "fixed-clock";
2826 #clock-cells = <0>;
2827 clock-frequency = <0>;
2828 };
2829 };