| blob | 1333b02d623a5762aac6f6e8dccc551b07c998c0 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774e1-sysc.h>
13 #define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4
15 / {
16 compatible = "renesas,r8a774e1";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 /*
21 * The external audio clocks are configured as 0 Hz fixed frequency
22 * clocks by default.
23 * Boards that provide audio clocks should override them.
24 */
25 audio_clk_a: audio_clk_a {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
29 };
31 audio_clk_b: audio_clk_b {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <0>;
35 };
37 audio_clk_c: audio_clk_c {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <0>;
41 };
43 /* External CAN clock - to be overridden by boards that provide it */
44 can_clk: can {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <0>;
48 };
50 cluster0_opp: opp_table0 {
51 compatible = "operating-points-v2";
52 opp-shared;
54 opp-500000000 {
55 opp-hz = /bits/ 64 <500000000>;
56 opp-microvolt = <820000>;
57 clock-latency-ns = <300000>;
58 };
59 opp-1000000000 {
60 opp-hz = /bits/ 64 <1000000000>;
61 opp-microvolt = <820000>;
62 clock-latency-ns = <300000>;
63 };
64 opp-1500000000 {
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <820000>;
67 clock-latency-ns = <300000>;
68 opp-suspend;
69 };
70 };
72 cluster1_opp: opp_table1 {
73 compatible = "operating-points-v2";
74 opp-shared;
76 opp-800000000 {
77 opp-hz = /bits/ 64 <800000000>;
78 opp-microvolt = <820000>;
79 clock-latency-ns = <300000>;
80 };
81 opp-1000000000 {
82 opp-hz = /bits/ 64 <1000000000>;
83 opp-microvolt = <820000>;
84 clock-latency-ns = <300000>;
85 };
86 opp-1200000000 {
87 opp-hz = /bits/ 64 <1200000000>;
88 opp-microvolt = <820000>;
89 clock-latency-ns = <300000>;
90 };
91 };
93 cpus {
94 #address-cells = <1>;
95 #size-cells = <0>;
97 cpu-map {
98 cluster0 {
99 core0 {
100 cpu = <&a57_0>;
101 };
102 core1 {
103 cpu = <&a57_1>;
104 };
105 core2 {
106 cpu = <&a57_2>;
107 };
108 core3 {
109 cpu = <&a57_3>;
110 };
111 };
113 cluster1 {
114 core0 {
115 cpu = <&a53_0>;
116 };
117 core1 {
118 cpu = <&a53_1>;
119 };
120 core2 {
121 cpu = <&a53_2>;
122 };
123 core3 {
124 cpu = <&a53_3>;
125 };
126 };
127 };
129 a57_0: cpu@0 {
130 compatible = "arm,cortex-a57";
131 reg = <0x0>;
132 device_type = "cpu";
133 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
134 next-level-cache = <&L2_CA57>;
135 enable-method = "psci";
136 cpu-idle-states = <&CPU_SLEEP_0>;
137 dynamic-power-coefficient = <854>;
138 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
139 operating-points-v2 = <&cluster0_opp>;
140 capacity-dmips-mhz = <1024>;
141 #cooling-cells = <2>;
142 };
144 a57_1: cpu@1 {
145 compatible = "arm,cortex-a57";
146 reg = <0x1>;
147 device_type = "cpu";
148 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
149 next-level-cache = <&L2_CA57>;
150 enable-method = "psci";
151 cpu-idle-states = <&CPU_SLEEP_0>;
152 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
153 operating-points-v2 = <&cluster0_opp>;
154 capacity-dmips-mhz = <1024>;
155 #cooling-cells = <2>;
156 };
158 a57_2: cpu@2 {
159 compatible = "arm,cortex-a57";
160 reg = <0x2>;
161 device_type = "cpu";
162 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
163 next-level-cache = <&L2_CA57>;
164 enable-method = "psci";
165 cpu-idle-states = <&CPU_SLEEP_0>;
166 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
167 operating-points-v2 = <&cluster0_opp>;
168 capacity-dmips-mhz = <1024>;
169 #cooling-cells = <2>;
170 };
172 a57_3: cpu@3 {
173 compatible = "arm,cortex-a57";
174 reg = <0x3>;
175 device_type = "cpu";
176 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
177 next-level-cache = <&L2_CA57>;
178 enable-method = "psci";
179 cpu-idle-states = <&CPU_SLEEP_0>;
180 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
181 operating-points-v2 = <&cluster0_opp>;
182 capacity-dmips-mhz = <1024>;
183 #cooling-cells = <2>;
184 };
186 a53_0: cpu@100 {
187 compatible = "arm,cortex-a53";
188 reg = <0x100>;
189 device_type = "cpu";
190 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
191 next-level-cache = <&L2_CA53>;
192 enable-method = "psci";
193 cpu-idle-states = <&CPU_SLEEP_1>;
194 #cooling-cells = <2>;
195 dynamic-power-coefficient = <277>;
196 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
197 operating-points-v2 = <&cluster1_opp>;
198 capacity-dmips-mhz = <535>;
199 };
201 a53_1: cpu@101 {
202 compatible = "arm,cortex-a53";
203 reg = <0x101>;
204 device_type = "cpu";
205 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
206 next-level-cache = <&L2_CA53>;
207 enable-method = "psci";
208 cpu-idle-states = <&CPU_SLEEP_1>;
209 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
210 operating-points-v2 = <&cluster1_opp>;
211 capacity-dmips-mhz = <535>;
212 };
214 a53_2: cpu@102 {
215 compatible = "arm,cortex-a53";
216 reg = <0x102>;
217 device_type = "cpu";
218 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
219 next-level-cache = <&L2_CA53>;
220 enable-method = "psci";
221 cpu-idle-states = <&CPU_SLEEP_1>;
222 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
223 operating-points-v2 = <&cluster1_opp>;
224 capacity-dmips-mhz = <535>;
225 };
227 a53_3: cpu@103 {
228 compatible = "arm,cortex-a53";
229 reg = <0x103>;
230 device_type = "cpu";
231 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
232 next-level-cache = <&L2_CA53>;
233 enable-method = "psci";
234 cpu-idle-states = <&CPU_SLEEP_1>;
235 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
236 operating-points-v2 = <&cluster1_opp>;
237 capacity-dmips-mhz = <535>;
238 };
240 L2_CA57: cache-controller-0 {
241 compatible = "cache";
242 power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
243 cache-unified;
244 cache-level = <2>;
245 };
247 L2_CA53: cache-controller-1 {
248 compatible = "cache";
249 power-domains = <&sysc R8A774E1_PD_CA53_SCU>;
250 cache-unified;
251 cache-level = <2>;
252 };
254 idle-states {
255 entry-method = "psci";
257 CPU_SLEEP_0: cpu-sleep-0 {
258 compatible = "arm,idle-state";
259 arm,psci-suspend-param = <0x0010000>;
260 local-timer-stop;
261 entry-latency-us = <400>;
262 exit-latency-us = <500>;
263 min-residency-us = <4000>;
264 };
266 CPU_SLEEP_1: cpu-sleep-1 {
267 compatible = "arm,idle-state";
268 arm,psci-suspend-param = <0x0010000>;
269 local-timer-stop;
270 entry-latency-us = <700>;
271 exit-latency-us = <700>;
272 min-residency-us = <5000>;
273 };
274 };
275 };
277 extal_clk: extal {
278 compatible = "fixed-clock";
279 #clock-cells = <0>;
280 /* This value must be overridden by the board */
281 clock-frequency = <0>;
282 };
284 extalr_clk: extalr {
285 compatible = "fixed-clock";
286 #clock-cells = <0>;
287 /* This value must be overridden by the board */
288 clock-frequency = <0>;
289 };
291 /* External PCIe clock - can be overridden by the board */
292 pcie_bus_clk: pcie_bus {
293 compatible = "fixed-clock";
294 #clock-cells = <0>;
295 clock-frequency = <0>;
296 };
298 pmu_a53 {
299 compatible = "arm,cortex-a53-pmu";
300 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
301 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
302 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
303 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
304 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
305 };
307 pmu_a57 {
308 compatible = "arm,cortex-a57-pmu";
309 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
310 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
311 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
312 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
313 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
314 };
316 psci {
317 compatible = "arm,psci-1.0", "arm,psci-0.2";
318 method = "smc";
319 };
321 /* External SCIF clock - to be overridden by boards that provide it */
322 scif_clk: scif {
323 compatible = "fixed-clock";
324 #clock-cells = <0>;
325 clock-frequency = <0>;
326 };
328 soc {
329 compatible = "simple-bus";
330 interrupt-parent = <&gic>;
331 #address-cells = <2>;
332 #size-cells = <2>;
333 ranges;
335 rwdt: watchdog@e6020000 {
336 compatible = "renesas,r8a774e1-wdt",
337 "renesas,rcar-gen3-wdt";
338 reg = <0 0xe6020000 0 0x0c>;
339 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&cpg CPG_MOD 402>;
341 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
342 resets = <&cpg 402>;
343 status = "disabled";
344 };
346 gpio0: gpio@e6050000 {
347 compatible = "renesas,gpio-r8a774e1",
348 "renesas,rcar-gen3-gpio";
349 reg = <0 0xe6050000 0 0x50>;
350 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
351 #gpio-cells = <2>;
352 gpio-controller;
353 gpio-ranges = <&pfc 0 0 16>;
354 #interrupt-cells = <2>;
355 interrupt-controller;
356 clocks = <&cpg CPG_MOD 912>;
357 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
358 resets = <&cpg 912>;
359 };
361 gpio1: gpio@e6051000 {
362 compatible = "renesas,gpio-r8a774e1",
363 "renesas,rcar-gen3-gpio";
364 reg = <0 0xe6051000 0 0x50>;
365 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
366 #gpio-cells = <2>;
367 gpio-controller;
368 gpio-ranges = <&pfc 0 32 29>;
369 #interrupt-cells = <2>;
370 interrupt-controller;
371 clocks = <&cpg CPG_MOD 911>;
372 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
373 resets = <&cpg 911>;
374 };
376 gpio2: gpio@e6052000 {
377 compatible = "renesas,gpio-r8a774e1",
378 "renesas,rcar-gen3-gpio";
379 reg = <0 0xe6052000 0 0x50>;
380 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
381 #gpio-cells = <2>;
382 gpio-controller;
383 gpio-ranges = <&pfc 0 64 15>;
384 #interrupt-cells = <2>;
385 interrupt-controller;
386 clocks = <&cpg CPG_MOD 910>;
387 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
388 resets = <&cpg 910>;
389 };
391 gpio3: gpio@e6053000 {
392 compatible = "renesas,gpio-r8a774e1",
393 "renesas,rcar-gen3-gpio";
394 reg = <0 0xe6053000 0 0x50>;
395 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
396 #gpio-cells = <2>;
397 gpio-controller;
398 gpio-ranges = <&pfc 0 96 16>;
399 #interrupt-cells = <2>;
400 interrupt-controller;
401 clocks = <&cpg CPG_MOD 909>;
402 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
403 resets = <&cpg 909>;
404 };
406 gpio4: gpio@e6054000 {
407 compatible = "renesas,gpio-r8a774e1",
408 "renesas,rcar-gen3-gpio";
409 reg = <0 0xe6054000 0 0x50>;
410 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
411 #gpio-cells = <2>;
412 gpio-controller;
413 gpio-ranges = <&pfc 0 128 18>;
414 #interrupt-cells = <2>;
415 interrupt-controller;
416 clocks = <&cpg CPG_MOD 908>;
417 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
418 resets = <&cpg 908>;
419 };
421 gpio5: gpio@e6055000 {
422 compatible = "renesas,gpio-r8a774e1",
423 "renesas,rcar-gen3-gpio";
424 reg = <0 0xe6055000 0 0x50>;
425 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
426 #gpio-cells = <2>;
427 gpio-controller;
428 gpio-ranges = <&pfc 0 160 26>;
429 #interrupt-cells = <2>;
430 interrupt-controller;
431 clocks = <&cpg CPG_MOD 907>;
432 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
433 resets = <&cpg 907>;
434 };
436 gpio6: gpio@e6055400 {
437 compatible = "renesas,gpio-r8a774e1",
438 "renesas,rcar-gen3-gpio";
439 reg = <0 0xe6055400 0 0x50>;
440 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
441 #gpio-cells = <2>;
442 gpio-controller;
443 gpio-ranges = <&pfc 0 192 32>;
444 #interrupt-cells = <2>;
445 interrupt-controller;
446 clocks = <&cpg CPG_MOD 906>;
447 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
448 resets = <&cpg 906>;
449 };
451 gpio7: gpio@e6055800 {
452 compatible = "renesas,gpio-r8a774e1",
453 "renesas,rcar-gen3-gpio";
454 reg = <0 0xe6055800 0 0x50>;
455 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
456 #gpio-cells = <2>;
457 gpio-controller;
458 gpio-ranges = <&pfc 0 224 4>;
459 #interrupt-cells = <2>;
460 interrupt-controller;
461 clocks = <&cpg CPG_MOD 905>;
462 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
463 resets = <&cpg 905>;
464 };
466 pfc: pinctrl@e6060000 {
467 compatible = "renesas,pfc-r8a774e1";
468 reg = <0 0xe6060000 0 0x50c>;
469 };
471 cmt0: timer@e60f0000 {
472 compatible = "renesas,r8a774e1-cmt0",
473 "renesas,rcar-gen3-cmt0";
474 reg = <0 0xe60f0000 0 0x1004>;
475 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 303>;
478 clock-names = "fck";
479 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
480 resets = <&cpg 303>;
481 status = "disabled";
482 };
484 cmt1: timer@e6130000 {
485 compatible = "renesas,r8a774e1-cmt1",
486 "renesas,rcar-gen3-cmt1";
487 reg = <0 0xe6130000 0 0x1004>;
488 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&cpg CPG_MOD 302>;
497 clock-names = "fck";
498 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
499 resets = <&cpg 302>;
500 status = "disabled";
501 };
503 cmt2: timer@e6140000 {
504 compatible = "renesas,r8a774e1-cmt1",
505 "renesas,rcar-gen3-cmt1";
506 reg = <0 0xe6140000 0 0x1004>;
507 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&cpg CPG_MOD 301>;
516 clock-names = "fck";
517 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
518 resets = <&cpg 301>;
519 status = "disabled";
520 };
522 cmt3: timer@e6148000 {
523 compatible = "renesas,r8a774e1-cmt1",
524 "renesas,rcar-gen3-cmt1";
525 reg = <0 0xe6148000 0 0x1004>;
526 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&cpg CPG_MOD 300>;
535 clock-names = "fck";
536 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
537 resets = <&cpg 300>;
538 status = "disabled";
539 };
541 cpg: clock-controller@e6150000 {
542 compatible = "renesas,r8a774e1-cpg-mssr";
543 reg = <0 0xe6150000 0 0x1000>;
544 clocks = <&extal_clk>, <&extalr_clk>;
545 clock-names = "extal", "extalr";
546 #clock-cells = <2>;
547 #power-domain-cells = <0>;
548 #reset-cells = <1>;
549 };
551 rst: reset-controller@e6160000 {
552 compatible = "renesas,r8a774e1-rst";
553 reg = <0 0xe6160000 0 0x0200>;
554 };
556 sysc: system-controller@e6180000 {
557 compatible = "renesas,r8a774e1-sysc";
558 reg = <0 0xe6180000 0 0x0400>;
559 #power-domain-cells = <1>;
560 };
562 tsc: thermal@e6198000 {
563 compatible = "renesas,r8a774e1-thermal";
564 reg = <0 0xe6198000 0 0x100>,
565 <0 0xe61a0000 0 0x100>,
566 <0 0xe61a8000 0 0x100>;
567 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cpg CPG_MOD 522>;
571 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
572 resets = <&cpg 522>;
573 #thermal-sensor-cells = <1>;
574 };
576 intc_ex: interrupt-controller@e61c0000 {
577 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc";
578 #interrupt-cells = <2>;
579 interrupt-controller;
580 reg = <0 0xe61c0000 0 0x200>;
581 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&cpg CPG_MOD 407>;
588 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
589 resets = <&cpg 407>;
590 };
592 tmu0: timer@e61e0000 {
593 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
594 reg = <0 0xe61e0000 0 0x30>;
595 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&cpg CPG_MOD 125>;
599 clock-names = "fck";
600 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
601 resets = <&cpg 125>;
602 status = "disabled";
603 };
605 tmu1: timer@e6fc0000 {
606 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
607 reg = <0 0xe6fc0000 0 0x30>;
608 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&cpg CPG_MOD 124>;
612 clock-names = "fck";
613 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
614 resets = <&cpg 124>;
615 status = "disabled";
616 };
618 tmu2: timer@e6fd0000 {
619 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
620 reg = <0 0xe6fd0000 0 0x30>;
621 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&cpg CPG_MOD 123>;
625 clock-names = "fck";
626 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
627 resets = <&cpg 123>;
628 status = "disabled";
629 };
631 tmu3: timer@e6fe0000 {
632 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
633 reg = <0 0xe6fe0000 0 0x30>;
634 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cpg CPG_MOD 122>;
638 clock-names = "fck";
639 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
640 resets = <&cpg 122>;
641 status = "disabled";
642 };
644 tmu4: timer@ffc00000 {
645 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
646 reg = <0 0xffc00000 0 0x30>;
647 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&cpg CPG_MOD 121>;
651 clock-names = "fck";
652 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
653 resets = <&cpg 121>;
654 status = "disabled";
655 };
657 i2c0: i2c@e6500000 {
658 #address-cells = <1>;
659 #size-cells = <0>;
660 compatible = "renesas,i2c-r8a774e1",
661 "renesas,rcar-gen3-i2c";
662 reg = <0 0xe6500000 0 0x40>;
663 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&cpg CPG_MOD 931>;
665 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
666 resets = <&cpg 931>;
667 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
668 <&dmac2 0x91>, <&dmac2 0x90>;
669 dma-names = "tx", "rx", "tx", "rx";
670 i2c-scl-internal-delay-ns = <110>;
671 status = "disabled";
672 };
674 i2c1: i2c@e6508000 {
675 #address-cells = <1>;
676 #size-cells = <0>;
677 compatible = "renesas,i2c-r8a774e1",
678 "renesas,rcar-gen3-i2c";
679 reg = <0 0xe6508000 0 0x40>;
680 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&cpg CPG_MOD 930>;
682 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
683 resets = <&cpg 930>;
684 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
685 <&dmac2 0x93>, <&dmac2 0x92>;
686 dma-names = "tx", "rx", "tx", "rx";
687 i2c-scl-internal-delay-ns = <6>;
688 status = "disabled";
689 };
691 i2c2: i2c@e6510000 {
692 #address-cells = <1>;
693 #size-cells = <0>;
694 compatible = "renesas,i2c-r8a774e1",
695 "renesas,rcar-gen3-i2c";
696 reg = <0 0xe6510000 0 0x40>;
697 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&cpg CPG_MOD 929>;
699 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
700 resets = <&cpg 929>;
701 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
702 <&dmac2 0x95>, <&dmac2 0x94>;
703 dma-names = "tx", "rx", "tx", "rx";
704 i2c-scl-internal-delay-ns = <6>;
705 status = "disabled";
706 };
708 i2c3: i2c@e66d0000 {
709 #address-cells = <1>;
710 #size-cells = <0>;
711 compatible = "renesas,i2c-r8a774e1",
712 "renesas,rcar-gen3-i2c";
713 reg = <0 0xe66d0000 0 0x40>;
714 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&cpg CPG_MOD 928>;
716 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
717 resets = <&cpg 928>;
718 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
719 dma-names = "tx", "rx";
720 i2c-scl-internal-delay-ns = <110>;
721 status = "disabled";
722 };
724 i2c4: i2c@e66d8000 {
725 #address-cells = <1>;
726 #size-cells = <0>;
727 compatible = "renesas,i2c-r8a774e1",
728 "renesas,rcar-gen3-i2c";
729 reg = <0 0xe66d8000 0 0x40>;
730 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&cpg CPG_MOD 927>;
732 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
733 resets = <&cpg 927>;
734 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
735 dma-names = "tx", "rx";
736 i2c-scl-internal-delay-ns = <110>;
737 status = "disabled";
738 };
740 i2c5: i2c@e66e0000 {
741 #address-cells = <1>;
742 #size-cells = <0>;
743 compatible = "renesas,i2c-r8a774e1",
744 "renesas,rcar-gen3-i2c";
745 reg = <0 0xe66e0000 0 0x40>;
746 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&cpg CPG_MOD 919>;
748 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
749 resets = <&cpg 919>;
750 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
751 dma-names = "tx", "rx";
752 i2c-scl-internal-delay-ns = <110>;
753 status = "disabled";
754 };
756 i2c6: i2c@e66e8000 {
757 #address-cells = <1>;
758 #size-cells = <0>;
759 compatible = "renesas,i2c-r8a774e1",
760 "renesas,rcar-gen3-i2c";
761 reg = <0 0xe66e8000 0 0x40>;
762 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&cpg CPG_MOD 918>;
764 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
765 resets = <&cpg 918>;
766 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
767 dma-names = "tx", "rx";
768 i2c-scl-internal-delay-ns = <6>;
769 status = "disabled";
770 };
772 i2c_dvfs: i2c@e60b0000 {
773 #address-cells = <1>;
774 #size-cells = <0>;
775 compatible = "renesas,iic-r8a774e1",
776 "renesas,rcar-gen3-iic",
777 "renesas,rmobile-iic";
778 reg = <0 0xe60b0000 0 0x425>;
779 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&cpg CPG_MOD 926>;
781 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
782 resets = <&cpg 926>;
783 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
784 dma-names = "tx", "rx";
785 status = "disabled";
786 };
788 hscif0: serial@e6540000 {
789 compatible = "renesas,hscif-r8a774e1",
790 "renesas,rcar-gen3-hscif",
791 "renesas,hscif";
792 reg = <0 0xe6540000 0 0x60>;
793 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&cpg CPG_MOD 520>,
795 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
796 <&scif_clk>;
797 clock-names = "fck", "brg_int", "scif_clk";
798 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
799 <&dmac2 0x31>, <&dmac2 0x30>;
800 dma-names = "tx", "rx", "tx", "rx";
801 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
802 resets = <&cpg 520>;
803 status = "disabled";
804 };
806 hscif1: serial@e6550000 {
807 compatible = "renesas,hscif-r8a774e1",
808 "renesas,rcar-gen3-hscif",
809 "renesas,hscif";
810 reg = <0 0xe6550000 0 0x60>;
811 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&cpg CPG_MOD 519>,
813 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
814 <&scif_clk>;
815 clock-names = "fck", "brg_int", "scif_clk";
816 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
817 <&dmac2 0x33>, <&dmac2 0x32>;
818 dma-names = "tx", "rx", "tx", "rx";
819 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
820 resets = <&cpg 519>;
821 status = "disabled";
822 };
824 hscif2: serial@e6560000 {
825 compatible = "renesas,hscif-r8a774e1",
826 "renesas,rcar-gen3-hscif",
827 "renesas,hscif";
828 reg = <0 0xe6560000 0 0x60>;
829 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&cpg CPG_MOD 518>,
831 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
832 <&scif_clk>;
833 clock-names = "fck", "brg_int", "scif_clk";
834 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
835 <&dmac2 0x35>, <&dmac2 0x34>;
836 dma-names = "tx", "rx", "tx", "rx";
837 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
838 resets = <&cpg 518>;
839 status = "disabled";
840 };
842 hscif3: serial@e66a0000 {
843 compatible = "renesas,hscif-r8a774e1",
844 "renesas,rcar-gen3-hscif",
845 "renesas,hscif";
846 reg = <0 0xe66a0000 0 0x60>;
847 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&cpg CPG_MOD 517>,
849 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
850 <&scif_clk>;
851 clock-names = "fck", "brg_int", "scif_clk";
852 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
853 dma-names = "tx", "rx";
854 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
855 resets = <&cpg 517>;
856 status = "disabled";
857 };
859 hscif4: serial@e66b0000 {
860 compatible = "renesas,hscif-r8a774e1",
861 "renesas,rcar-gen3-hscif",
862 "renesas,hscif";
863 reg = <0 0xe66b0000 0 0x60>;
864 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&cpg CPG_MOD 516>,
866 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
867 <&scif_clk>;
868 clock-names = "fck", "brg_int", "scif_clk";
869 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
870 dma-names = "tx", "rx";
871 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
872 resets = <&cpg 516>;
873 status = "disabled";
874 };
876 hsusb: usb@e6590000 {
877 compatible = "renesas,usbhs-r8a774e1",
878 "renesas,rcar-gen3-usbhs";
879 reg = <0 0xe6590000 0 0x200>;
880 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
882 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
883 <&usb_dmac1 0>, <&usb_dmac1 1>;
884 dma-names = "ch0", "ch1", "ch2", "ch3";
885 renesas,buswait = <11>;
886 phys = <&usb2_phy0 3>;
887 phy-names = "usb";
888 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
889 resets = <&cpg 704>, <&cpg 703>;
890 status = "disabled";
891 };
893 usb_dmac0: dma-controller@e65a0000 {
894 compatible = "renesas,r8a774e1-usb-dmac",
895 "renesas,usb-dmac";
896 reg = <0 0xe65a0000 0 0x100>;
897 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
899 interrupt-names = "ch0", "ch1";
900 clocks = <&cpg CPG_MOD 330>;
901 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
902 resets = <&cpg 330>;
903 #dma-cells = <1>;
904 dma-channels = <2>;
905 };
907 usb_dmac1: dma-controller@e65b0000 {
908 compatible = "renesas,r8a774e1-usb-dmac",
909 "renesas,usb-dmac";
910 reg = <0 0xe65b0000 0 0x100>;
911 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
912 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
913 interrupt-names = "ch0", "ch1";
914 clocks = <&cpg CPG_MOD 331>;
915 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
916 resets = <&cpg 331>;
917 #dma-cells = <1>;
918 dma-channels = <2>;
919 };
921 usb3_phy0: usb-phy@e65ee000 {
922 compatible = "renesas,r8a774e1-usb3-phy",
923 "renesas,rcar-gen3-usb3-phy";
924 reg = <0 0xe65ee000 0 0x90>;
925 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
926 <&usb_extal_clk>;
927 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
928 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
929 resets = <&cpg 328>;
930 #phy-cells = <0>;
931 status = "disabled";
932 };
934 dmac0: dma-controller@e6700000 {
935 compatible = "renesas,dmac-r8a774e1",
936 "renesas,rcar-dmac";
937 reg = <0 0xe6700000 0 0x10000>;
938 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
955 interrupt-names = "error",
956 "ch0", "ch1", "ch2", "ch3",
957 "ch4", "ch5", "ch6", "ch7",
958 "ch8", "ch9", "ch10", "ch11",
959 "ch12", "ch13", "ch14", "ch15";
960 clocks = <&cpg CPG_MOD 219>;
961 clock-names = "fck";
962 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
963 resets = <&cpg 219>;
964 #dma-cells = <1>;
965 dma-channels = <16>;
966 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
967 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
968 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
969 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
970 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
971 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
972 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
973 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
974 };
976 dmac1: dma-controller@e7300000 {
977 compatible = "renesas,dmac-r8a774e1",
978 "renesas,rcar-dmac";
979 reg = <0 0xe7300000 0 0x10000>;
980 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
997 interrupt-names = "error",
998 "ch0", "ch1", "ch2", "ch3",
999 "ch4", "ch5", "ch6", "ch7",
1000 "ch8", "ch9", "ch10", "ch11",
1001 "ch12", "ch13", "ch14", "ch15";
1002 clocks = <&cpg CPG_MOD 218>;
1003 clock-names = "fck";
1004 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1005 resets = <&cpg 218>;
1006 #dma-cells = <1>;
1007 dma-channels = <16>;
1008 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1009 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1010 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1011 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1012 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1013 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1014 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1015 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1016 };
1018 dmac2: dma-controller@e7310000 {
1019 compatible = "renesas,dmac-r8a774e1",
1020 "renesas,rcar-dmac";
1021 reg = <0 0xe7310000 0 0x10000>;
1022 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1039 interrupt-names = "error",
1040 "ch0", "ch1", "ch2", "ch3",
1041 "ch4", "ch5", "ch6", "ch7",
1042 "ch8", "ch9", "ch10", "ch11",
1043 "ch12", "ch13", "ch14", "ch15";
1044 clocks = <&cpg CPG_MOD 217>;
1045 clock-names = "fck";
1046 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1047 resets = <&cpg 217>;
1048 #dma-cells = <1>;
1049 dma-channels = <16>;
1050 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1051 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1052 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1053 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1054 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1055 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1056 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1057 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1058 };
1060 ipmmu_ds0: iommu@e6740000 {
1061 compatible = "renesas,ipmmu-r8a774e1";
1062 reg = <0 0xe6740000 0 0x1000>;
1063 renesas,ipmmu-main = <&ipmmu_mm 0>;
1064 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1065 #iommu-cells = <1>;
1066 };
1068 ipmmu_ds1: iommu@e7740000 {
1069 compatible = "renesas,ipmmu-r8a774e1";
1070 reg = <0 0xe7740000 0 0x1000>;
1071 renesas,ipmmu-main = <&ipmmu_mm 1>;
1072 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1073 #iommu-cells = <1>;
1074 };
1076 ipmmu_hc: iommu@e6570000 {
1077 compatible = "renesas,ipmmu-r8a774e1";
1078 reg = <0 0xe6570000 0 0x1000>;
1079 renesas,ipmmu-main = <&ipmmu_mm 2>;
1080 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1081 #iommu-cells = <1>;
1082 };
1084 ipmmu_mm: iommu@e67b0000 {
1085 compatible = "renesas,ipmmu-r8a774e1";
1086 reg = <0 0xe67b0000 0 0x1000>;
1087 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1089 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1090 #iommu-cells = <1>;
1091 };
1093 ipmmu_mp0: iommu@ec670000 {
1094 compatible = "renesas,ipmmu-r8a774e1";
1095 reg = <0 0xec670000 0 0x1000>;
1096 renesas,ipmmu-main = <&ipmmu_mm 4>;
1097 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1098 #iommu-cells = <1>;
1099 };
1101 ipmmu_pv0: iommu@fd800000 {
1102 compatible = "renesas,ipmmu-r8a774e1";
1103 reg = <0 0xfd800000 0 0x1000>;
1104 renesas,ipmmu-main = <&ipmmu_mm 6>;
1105 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1106 #iommu-cells = <1>;
1107 };
1109 ipmmu_pv1: iommu@fd950000 {
1110 compatible = "renesas,ipmmu-r8a774e1";
1111 reg = <0 0xfd950000 0 0x1000>;
1112 renesas,ipmmu-main = <&ipmmu_mm 7>;
1113 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1114 #iommu-cells = <1>;
1115 };
1117 ipmmu_pv2: iommu@fd960000 {
1118 compatible = "renesas,ipmmu-r8a774e1";
1119 reg = <0 0xfd960000 0 0x1000>;
1120 renesas,ipmmu-main = <&ipmmu_mm 8>;
1121 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1122 #iommu-cells = <1>;
1123 };
1125 ipmmu_pv3: iommu@fd970000 {
1126 compatible = "renesas,ipmmu-r8a774e1";
1127 reg = <0 0xfd970000 0 0x1000>;
1128 renesas,ipmmu-main = <&ipmmu_mm 9>;
1129 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1130 #iommu-cells = <1>;
1131 };
1133 ipmmu_vc0: iommu@fe6b0000 {
1134 compatible = "renesas,ipmmu-r8a774e1";
1135 reg = <0 0xfe6b0000 0 0x1000>;
1136 renesas,ipmmu-main = <&ipmmu_mm 12>;
1137 power-domains = <&sysc R8A774E1_PD_A3VC>;
1138 #iommu-cells = <1>;
1139 };
1141 ipmmu_vc1: iommu@fe6f0000 {
1142 compatible = "renesas,ipmmu-r8a774e1";
1143 reg = <0 0xfe6f0000 0 0x1000>;
1144 renesas,ipmmu-main = <&ipmmu_mm 13>;
1145 power-domains = <&sysc R8A774E1_PD_A3VC>;
1146 #iommu-cells = <1>;
1147 };
1149 ipmmu_vi0: iommu@febd0000 {
1150 compatible = "renesas,ipmmu-r8a774e1";
1151 reg = <0 0xfebd0000 0 0x1000>;
1152 renesas,ipmmu-main = <&ipmmu_mm 14>;
1153 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1154 #iommu-cells = <1>;
1155 };
1157 ipmmu_vi1: iommu@febe0000 {
1158 compatible = "renesas,ipmmu-r8a774e1";
1159 reg = <0 0xfebe0000 0 0x1000>;
1160 renesas,ipmmu-main = <&ipmmu_mm 15>;
1161 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1162 #iommu-cells = <1>;
1163 };
1165 ipmmu_vp0: iommu@fe990000 {
1166 compatible = "renesas,ipmmu-r8a774e1";
1167 reg = <0 0xfe990000 0 0x1000>;
1168 renesas,ipmmu-main = <&ipmmu_mm 16>;
1169 power-domains = <&sysc R8A774E1_PD_A3VP>;
1170 #iommu-cells = <1>;
1171 };
1173 ipmmu_vp1: iommu@fe980000 {
1174 compatible = "renesas,ipmmu-r8a774e1";
1175 reg = <0 0xfe980000 0 0x1000>;
1176 renesas,ipmmu-main = <&ipmmu_mm 17>;
1177 power-domains = <&sysc R8A774E1_PD_A3VP>;
1178 #iommu-cells = <1>;
1179 };
1181 avb: ethernet@e6800000 {
1182 compatible = "renesas,etheravb-r8a774e1",
1183 "renesas,etheravb-rcar-gen3";
1184 reg = <0 0xe6800000 0 0x800>;
1185 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1192 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1194 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1195 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1196 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1198 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1199 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1200 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1201 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1202 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1203 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1204 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1205 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1210 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1211 "ch4", "ch5", "ch6", "ch7",
1212 "ch8", "ch9", "ch10", "ch11",
1213 "ch12", "ch13", "ch14", "ch15",
1214 "ch16", "ch17", "ch18", "ch19",
1215 "ch20", "ch21", "ch22", "ch23",
1216 "ch24";
1217 clocks = <&cpg CPG_MOD 812>;
1218 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1219 resets = <&cpg 812>;
1220 phy-mode = "rgmii";
1221 rx-internal-delay-ps = <0>;
1222 tx-internal-delay-ps = <0>;
1223 iommus = <&ipmmu_ds0 16>;
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1226 status = "disabled";
1227 };
1229 can0: can@e6c30000 {
1230 compatible = "renesas,can-r8a774e1",
1231 "renesas,rcar-gen3-can";
1232 reg = <0 0xe6c30000 0 0x1000>;
1233 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1234 clocks = <&cpg CPG_MOD 916>,
1235 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1236 <&can_clk>;
1237 clock-names = "clkp1", "clkp2", "can_clk";
1238 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1239 assigned-clock-rates = <40000000>;
1240 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1241 resets = <&cpg 916>;
1242 status = "disabled";
1243 };
1245 can1: can@e6c38000 {
1246 compatible = "renesas,can-r8a774e1",
1247 "renesas,rcar-gen3-can";
1248 reg = <0 0xe6c38000 0 0x1000>;
1249 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&cpg CPG_MOD 915>,
1251 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1252 <&can_clk>;
1253 clock-names = "clkp1", "clkp2", "can_clk";
1254 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1255 assigned-clock-rates = <40000000>;
1256 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1257 resets = <&cpg 915>;
1258 status = "disabled";
1259 };
1261 canfd: can@e66c0000 {
1262 compatible = "renesas,r8a774e1-canfd",
1263 "renesas,rcar-gen3-canfd";
1264 reg = <0 0xe66c0000 0 0x8000>;
1265 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1267 clocks = <&cpg CPG_MOD 914>,
1268 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1269 <&can_clk>;
1270 clock-names = "fck", "canfd", "can_clk";
1271 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1272 assigned-clock-rates = <40000000>;
1273 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1274 resets = <&cpg 914>;
1275 status = "disabled";
1277 channel0 {
1278 status = "disabled";
1279 };
1281 channel1 {
1282 status = "disabled";
1283 };
1284 };
1286 pwm0: pwm@e6e30000 {
1287 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1288 reg = <0 0xe6e30000 0 0x8>;
1289 clocks = <&cpg CPG_MOD 523>;
1290 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1291 resets = <&cpg 523>;
1292 #pwm-cells = <2>;
1293 status = "disabled";
1294 };
1296 pwm1: pwm@e6e31000 {
1297 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1298 reg = <0 0xe6e31000 0 0x8>;
1299 clocks = <&cpg CPG_MOD 523>;
1300 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1301 resets = <&cpg 523>;
1302 #pwm-cells = <2>;
1303 status = "disabled";
1304 };
1306 pwm2: pwm@e6e32000 {
1307 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1308 reg = <0 0xe6e32000 0 0x8>;
1309 clocks = <&cpg CPG_MOD 523>;
1310 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1311 resets = <&cpg 523>;
1312 #pwm-cells = <2>;
1313 status = "disabled";
1314 };
1316 pwm3: pwm@e6e33000 {
1317 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1318 reg = <0 0xe6e33000 0 0x8>;
1319 clocks = <&cpg CPG_MOD 523>;
1320 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1321 resets = <&cpg 523>;
1322 #pwm-cells = <2>;
1323 status = "disabled";
1324 };
1326 pwm4: pwm@e6e34000 {
1327 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1328 reg = <0 0xe6e34000 0 0x8>;
1329 clocks = <&cpg CPG_MOD 523>;
1330 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1331 resets = <&cpg 523>;
1332 #pwm-cells = <2>;
1333 status = "disabled";
1334 };
1336 pwm5: pwm@e6e35000 {
1337 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1338 reg = <0 0xe6e35000 0 0x8>;
1339 clocks = <&cpg CPG_MOD 523>;
1340 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1341 resets = <&cpg 523>;
1342 #pwm-cells = <2>;
1343 status = "disabled";
1344 };
1346 pwm6: pwm@e6e36000 {
1347 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1348 reg = <0 0xe6e36000 0 0x8>;
1349 clocks = <&cpg CPG_MOD 523>;
1350 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1351 resets = <&cpg 523>;
1352 #pwm-cells = <2>;
1353 status = "disabled";
1354 };
1356 scif0: serial@e6e60000 {
1357 compatible = "renesas,scif-r8a774e1",
1358 "renesas,rcar-gen3-scif", "renesas,scif";
1359 reg = <0 0xe6e60000 0 0x40>;
1360 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1361 clocks = <&cpg CPG_MOD 207>,
1362 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1363 <&scif_clk>;
1364 clock-names = "fck", "brg_int", "scif_clk";
1365 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1366 <&dmac2 0x51>, <&dmac2 0x50>;
1367 dma-names = "tx", "rx", "tx", "rx";
1368 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1369 resets = <&cpg 207>;
1370 status = "disabled";
1371 };
1373 scif1: serial@e6e68000 {
1374 compatible = "renesas,scif-r8a774e1",
1375 "renesas,rcar-gen3-scif", "renesas,scif";
1376 reg = <0 0xe6e68000 0 0x40>;
1377 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1378 clocks = <&cpg CPG_MOD 206>,
1379 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1380 <&scif_clk>;
1381 clock-names = "fck", "brg_int", "scif_clk";
1382 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1383 <&dmac2 0x53>, <&dmac2 0x52>;
1384 dma-names = "tx", "rx", "tx", "rx";
1385 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1386 resets = <&cpg 206>;
1387 status = "disabled";
1388 };
1390 scif2: serial@e6e88000 {
1391 compatible = "renesas,scif-r8a774e1",
1392 "renesas,rcar-gen3-scif", "renesas,scif";
1393 reg = <0 0xe6e88000 0 0x40>;
1394 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1395 clocks = <&cpg CPG_MOD 310>,
1396 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1397 <&scif_clk>;
1398 clock-names = "fck", "brg_int", "scif_clk";
1399 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1400 <&dmac2 0x13>, <&dmac2 0x12>;
1401 dma-names = "tx", "rx", "tx", "rx";
1402 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1403 resets = <&cpg 310>;
1404 status = "disabled";
1405 };
1407 scif3: serial@e6c50000 {
1408 compatible = "renesas,scif-r8a774e1",
1409 "renesas,rcar-gen3-scif", "renesas,scif";
1410 reg = <0 0xe6c50000 0 0x40>;
1411 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1412 clocks = <&cpg CPG_MOD 204>,
1413 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1414 <&scif_clk>;
1415 clock-names = "fck", "brg_int", "scif_clk";
1416 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1417 dma-names = "tx", "rx";
1418 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1419 resets = <&cpg 204>;
1420 status = "disabled";
1421 };
1423 scif4: serial@e6c40000 {
1424 compatible = "renesas,scif-r8a774e1",
1425 "renesas,rcar-gen3-scif", "renesas,scif";
1426 reg = <0 0xe6c40000 0 0x40>;
1427 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1428 clocks = <&cpg CPG_MOD 203>,
1429 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1430 <&scif_clk>;
1431 clock-names = "fck", "brg_int", "scif_clk";
1432 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1433 dma-names = "tx", "rx";
1434 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1435 resets = <&cpg 203>;
1436 status = "disabled";
1437 };
1439 scif5: serial@e6f30000 {
1440 compatible = "renesas,scif-r8a774e1",
1441 "renesas,rcar-gen3-scif", "renesas,scif";
1442 reg = <0 0xe6f30000 0 0x40>;
1443 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&cpg CPG_MOD 202>,
1445 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1446 <&scif_clk>;
1447 clock-names = "fck", "brg_int", "scif_clk";
1448 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1449 <&dmac2 0x5b>, <&dmac2 0x5a>;
1450 dma-names = "tx", "rx", "tx", "rx";
1451 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1452 resets = <&cpg 202>;
1453 status = "disabled";
1454 };
1456 msiof0: spi@e6e90000 {
1457 compatible = "renesas,msiof-r8a774e1",
1458 "renesas,rcar-gen3-msiof";
1459 reg = <0 0xe6e90000 0 0x0064>;
1460 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1461 clocks = <&cpg CPG_MOD 211>;
1462 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1463 <&dmac2 0x41>, <&dmac2 0x40>;
1464 dma-names = "tx", "rx", "tx", "rx";
1465 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1466 resets = <&cpg 211>;
1467 #address-cells = <1>;
1468 #size-cells = <0>;
1469 status = "disabled";
1470 };
1472 msiof1: spi@e6ea0000 {
1473 compatible = "renesas,msiof-r8a774e1",
1474 "renesas,rcar-gen3-msiof";
1475 reg = <0 0xe6ea0000 0 0x0064>;
1476 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1477 clocks = <&cpg CPG_MOD 210>;
1478 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1479 <&dmac2 0x43>, <&dmac2 0x42>;
1480 dma-names = "tx", "rx", "tx", "rx";
1481 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1482 resets = <&cpg 210>;
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1485 status = "disabled";
1486 };
1488 msiof2: spi@e6c00000 {
1489 compatible = "renesas,msiof-r8a774e1",
1490 "renesas,rcar-gen3-msiof";
1491 reg = <0 0xe6c00000 0 0x0064>;
1492 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1493 clocks = <&cpg CPG_MOD 209>;
1494 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1495 dma-names = "tx", "rx";
1496 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1497 resets = <&cpg 209>;
1498 #address-cells = <1>;
1499 #size-cells = <0>;
1500 status = "disabled";
1501 };
1503 msiof3: spi@e6c10000 {
1504 compatible = "renesas,msiof-r8a774e1",
1505 "renesas,rcar-gen3-msiof";
1506 reg = <0 0xe6c10000 0 0x0064>;
1507 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1508 clocks = <&cpg CPG_MOD 208>;
1509 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1510 dma-names = "tx", "rx";
1511 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1512 resets = <&cpg 208>;
1513 #address-cells = <1>;
1514 #size-cells = <0>;
1515 status = "disabled";
1516 };
1518 vin0: video@e6ef0000 {
1519 compatible = "renesas,vin-r8a774e1";
1520 reg = <0 0xe6ef0000 0 0x1000>;
1521 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1522 clocks = <&cpg CPG_MOD 811>;
1523 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1524 resets = <&cpg 811>;
1525 renesas,id = <0>;
1526 status = "disabled";
1528 ports {
1529 #address-cells = <1>;
1530 #size-cells = <0>;
1532 port@1 {
1533 #address-cells = <1>;
1534 #size-cells = <0>;
1536 reg = <1>;
1538 vin0csi20: endpoint@0 {
1539 reg = <0>;
1540 remote-endpoint = <&csi20vin0>;
1541 };
1542 vin0csi40: endpoint@2 {
1543 reg = <2>;
1544 remote-endpoint = <&csi40vin0>;
1545 };
1546 };
1547 };
1548 };
1550 vin1: video@e6ef1000 {
1551 compatible = "renesas,vin-r8a774e1";
1552 reg = <0 0xe6ef1000 0 0x1000>;
1553 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1554 clocks = <&cpg CPG_MOD 810>;
1555 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1556 resets = <&cpg 810>;
1557 renesas,id = <1>;
1558 status = "disabled";
1560 ports {
1561 #address-cells = <1>;
1562 #size-cells = <0>;
1564 port@1 {
1565 #address-cells = <1>;
1566 #size-cells = <0>;
1568 reg = <1>;
1570 vin1csi20: endpoint@0 {
1571 reg = <0>;
1572 remote-endpoint = <&csi20vin1>;
1573 };
1574 vin1csi40: endpoint@2 {
1575 reg = <2>;
1576 remote-endpoint = <&csi40vin1>;
1577 };
1578 };
1579 };
1580 };
1582 vin2: video@e6ef2000 {
1583 compatible = "renesas,vin-r8a774e1";
1584 reg = <0 0xe6ef2000 0 0x1000>;
1585 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1586 clocks = <&cpg CPG_MOD 809>;
1587 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1588 resets = <&cpg 809>;
1589 renesas,id = <2>;
1590 status = "disabled";
1592 ports {
1593 #address-cells = <1>;
1594 #size-cells = <0>;
1596 port@1 {
1597 #address-cells = <1>;
1598 #size-cells = <0>;
1600 reg = <1>;
1602 vin2csi20: endpoint@0 {
1603 reg = <0>;
1604 remote-endpoint = <&csi20vin2>;
1605 };
1606 vin2csi40: endpoint@2 {
1607 reg = <2>;
1608 remote-endpoint = <&csi40vin2>;
1609 };
1610 };
1611 };
1612 };
1614 vin3: video@e6ef3000 {
1615 compatible = "renesas,vin-r8a774e1";
1616 reg = <0 0xe6ef3000 0 0x1000>;
1617 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&cpg CPG_MOD 808>;
1619 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1620 resets = <&cpg 808>;
1621 renesas,id = <3>;
1622 status = "disabled";
1624 ports {
1625 #address-cells = <1>;
1626 #size-cells = <0>;
1628 port@1 {
1629 #address-cells = <1>;
1630 #size-cells = <0>;
1632 reg = <1>;
1634 vin3csi20: endpoint@0 {
1635 reg = <0>;
1636 remote-endpoint = <&csi20vin3>;
1637 };
1638 vin3csi40: endpoint@2 {
1639 reg = <2>;
1640 remote-endpoint = <&csi40vin3>;
1641 };
1642 };
1643 };
1644 };
1646 vin4: video@e6ef4000 {
1647 compatible = "renesas,vin-r8a774e1";
1648 reg = <0 0xe6ef4000 0 0x1000>;
1649 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1650 clocks = <&cpg CPG_MOD 807>;
1651 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1652 resets = <&cpg 807>;
1653 renesas,id = <4>;
1654 status = "disabled";
1656 ports {
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1660 port@1 {
1661 #address-cells = <1>;
1662 #size-cells = <0>;
1664 reg = <1>;
1666 vin4csi20: endpoint@0 {
1667 reg = <0>;
1668 remote-endpoint = <&csi20vin4>;
1669 };
1670 };
1671 };
1672 };
1674 vin5: video@e6ef5000 {
1675 compatible = "renesas,vin-r8a774e1";
1676 reg = <0 0xe6ef5000 0 0x1000>;
1677 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1678 clocks = <&cpg CPG_MOD 806>;
1679 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1680 resets = <&cpg 806>;
1681 renesas,id = <5>;
1682 status = "disabled";
1684 ports {
1685 #address-cells = <1>;
1686 #size-cells = <0>;
1688 port@1 {
1689 #address-cells = <1>;
1690 #size-cells = <0>;
1692 reg = <1>;
1694 vin5csi20: endpoint@0 {
1695 reg = <0>;
1696 remote-endpoint = <&csi20vin5>;
1697 };
1698 };
1699 };
1700 };
1702 vin6: video@e6ef6000 {
1703 compatible = "renesas,vin-r8a774e1";
1704 reg = <0 0xe6ef6000 0 0x1000>;
1705 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1706 clocks = <&cpg CPG_MOD 805>;
1707 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1708 resets = <&cpg 805>;
1709 renesas,id = <6>;
1710 status = "disabled";
1712 ports {
1713 #address-cells = <1>;
1714 #size-cells = <0>;
1716 port@1 {
1717 #address-cells = <1>;
1718 #size-cells = <0>;
1720 reg = <1>;
1722 vin6csi20: endpoint@0 {
1723 reg = <0>;
1724 remote-endpoint = <&csi20vin6>;
1725 };
1726 };
1727 };
1728 };
1730 vin7: video@e6ef7000 {
1731 compatible = "renesas,vin-r8a774e1";
1732 reg = <0 0xe6ef7000 0 0x1000>;
1733 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1734 clocks = <&cpg CPG_MOD 804>;
1735 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1736 resets = <&cpg 804>;
1737 renesas,id = <7>;
1738 status = "disabled";
1740 ports {
1741 #address-cells = <1>;
1742 #size-cells = <0>;
1744 port@1 {
1745 #address-cells = <1>;
1746 #size-cells = <0>;
1748 reg = <1>;
1750 vin7csi20: endpoint@0 {
1751 reg = <0>;
1752 remote-endpoint = <&csi20vin7>;
1753 };
1754 };
1755 };
1756 };
1758 rcar_sound: sound@ec500000 {
1759 /*
1760 * #sound-dai-cells is required
1761 *
1762 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1763 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1764 */
1765 /*
1766 * #clock-cells is required for audio_clkout0/1/2/3
1767 *
1768 * clkout : #clock-cells = <0>; <&rcar_sound>;
1769 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1770 */
1771 compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
1772 reg = <0 0xec500000 0 0x1000>, /* SCU */
1773 <0 0xec5a0000 0 0x100>, /* ADG */
1774 <0 0xec540000 0 0x1000>, /* SSIU */
1775 <0 0xec541000 0 0x280>, /* SSI */
1776 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1777 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1779 clocks = <&cpg CPG_MOD 1005>,
1780 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1781 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1782 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1783 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1784 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1785 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1786 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1787 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1788 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1789 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1790 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1791 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1792 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1793 <&audio_clk_a>, <&audio_clk_b>,
1794 <&audio_clk_c>,
1795 <&cpg CPG_CORE R8A774E1_CLK_S0D4>;
1796 clock-names = "ssi-all",
1797 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1798 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1799 "ssi.1", "ssi.0",
1800 "src.9", "src.8", "src.7", "src.6",
1801 "src.5", "src.4", "src.3", "src.2",
1802 "src.1", "src.0",
1803 "mix.1", "mix.0",
1804 "ctu.1", "ctu.0",
1805 "dvc.0", "dvc.1",
1806 "clk_a", "clk_b", "clk_c", "clk_i";
1807 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1808 resets = <&cpg 1005>,
1809 <&cpg 1006>, <&cpg 1007>,
1810 <&cpg 1008>, <&cpg 1009>,
1811 <&cpg 1010>, <&cpg 1011>,
1812 <&cpg 1012>, <&cpg 1013>,
1813 <&cpg 1014>, <&cpg 1015>;
1814 reset-names = "ssi-all",
1815 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1816 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1817 "ssi.1", "ssi.0";
1818 status = "disabled";
1820 rcar_sound,dvc {
1821 dvc0: dvc-0 {
1822 dmas = <&audma1 0xbc>;
1823 dma-names = "tx";
1824 };
1825 dvc1: dvc-1 {
1826 dmas = <&audma1 0xbe>;
1827 dma-names = "tx";
1828 };
1829 };
1831 rcar_sound,mix {
1832 mix0: mix-0 { };
1833 mix1: mix-1 { };
1834 };
1836 rcar_sound,ctu {
1837 ctu00: ctu-0 { };
1838 ctu01: ctu-1 { };
1839 ctu02: ctu-2 { };
1840 ctu03: ctu-3 { };
1841 ctu10: ctu-4 { };
1842 ctu11: ctu-5 { };
1843 ctu12: ctu-6 { };
1844 ctu13: ctu-7 { };
1845 };
1847 rcar_sound,src {
1848 src0: src-0 {
1849 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1850 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1851 dma-names = "rx", "tx";
1852 };
1853 src1: src-1 {
1854 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1855 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1856 dma-names = "rx", "tx";
1857 };
1858 src2: src-2 {
1859 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1860 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1861 dma-names = "rx", "tx";
1862 };
1863 src3: src-3 {
1864 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1865 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1866 dma-names = "rx", "tx";
1867 };
1868 src4: src-4 {
1869 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1870 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1871 dma-names = "rx", "tx";
1872 };
1873 src5: src-5 {
1874 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1875 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1876 dma-names = "rx", "tx";
1877 };
1878 src6: src-6 {
1879 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1880 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1881 dma-names = "rx", "tx";
1882 };
1883 src7: src-7 {
1884 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1885 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1886 dma-names = "rx", "tx";
1887 };
1888 src8: src-8 {
1889 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1890 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1891 dma-names = "rx", "tx";
1892 };
1893 src9: src-9 {
1894 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1895 dmas = <&audma0 0x97>, <&audma1 0xba>;
1896 dma-names = "rx", "tx";
1897 };
1898 };
1900 rcar_sound,ssiu {
1901 ssiu00: ssiu-0 {
1902 dmas = <&audma0 0x15>, <&audma1 0x16>;
1903 dma-names = "rx", "tx";
1904 };
1905 ssiu01: ssiu-1 {
1906 dmas = <&audma0 0x35>, <&audma1 0x36>;
1907 dma-names = "rx", "tx";
1908 };
1909 ssiu02: ssiu-2 {
1910 dmas = <&audma0 0x37>, <&audma1 0x38>;
1911 dma-names = "rx", "tx";
1912 };
1913 ssiu03: ssiu-3 {
1914 dmas = <&audma0 0x47>, <&audma1 0x48>;
1915 dma-names = "rx", "tx";
1916 };
1917 ssiu04: ssiu-4 {
1918 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1919 dma-names = "rx", "tx";
1920 };
1921 ssiu05: ssiu-5 {
1922 dmas = <&audma0 0x43>, <&audma1 0x44>;
1923 dma-names = "rx", "tx";
1924 };
1925 ssiu06: ssiu-6 {
1926 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1927 dma-names = "rx", "tx";
1928 };
1929 ssiu07: ssiu-7 {
1930 dmas = <&audma0 0x53>, <&audma1 0x54>;
1931 dma-names = "rx", "tx";
1932 };
1933 ssiu10: ssiu-8 {
1934 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1935 dma-names = "rx", "tx";
1936 };
1937 ssiu11: ssiu-9 {
1938 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1939 dma-names = "rx", "tx";
1940 };
1941 ssiu12: ssiu-10 {
1942 dmas = <&audma0 0x57>, <&audma1 0x58>;
1943 dma-names = "rx", "tx";
1944 };
1945 ssiu13: ssiu-11 {
1946 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1947 dma-names = "rx", "tx";
1948 };
1949 ssiu14: ssiu-12 {
1950 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1951 dma-names = "rx", "tx";
1952 };
1953 ssiu15: ssiu-13 {
1954 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1955 dma-names = "rx", "tx";
1956 };
1957 ssiu16: ssiu-14 {
1958 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1959 dma-names = "rx", "tx";
1960 };
1961 ssiu17: ssiu-15 {
1962 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1963 dma-names = "rx", "tx";
1964 };
1965 ssiu20: ssiu-16 {
1966 dmas = <&audma0 0x63>, <&audma1 0x64>;
1967 dma-names = "rx", "tx";
1968 };
1969 ssiu21: ssiu-17 {
1970 dmas = <&audma0 0x67>, <&audma1 0x68>;
1971 dma-names = "rx", "tx";
1972 };
1973 ssiu22: ssiu-18 {
1974 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1975 dma-names = "rx", "tx";
1976 };
1977 ssiu23: ssiu-19 {
1978 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1979 dma-names = "rx", "tx";
1980 };
1981 ssiu24: ssiu-20 {
1982 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1983 dma-names = "rx", "tx";
1984 };
1985 ssiu25: ssiu-21 {
1986 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1987 dma-names = "rx", "tx";
1988 };
1989 ssiu26: ssiu-22 {
1990 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1991 dma-names = "rx", "tx";
1992 };
1993 ssiu27: ssiu-23 {
1994 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1995 dma-names = "rx", "tx";
1996 };
1997 ssiu30: ssiu-24 {
1998 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1999 dma-names = "rx", "tx";
2000 };
2001 ssiu31: ssiu-25 {
2002 dmas = <&audma0 0x21>, <&audma1 0x22>;
2003 dma-names = "rx", "tx";
2004 };
2005 ssiu32: ssiu-26 {
2006 dmas = <&audma0 0x23>, <&audma1 0x24>;
2007 dma-names = "rx", "tx";
2008 };
2009 ssiu33: ssiu-27 {
2010 dmas = <&audma0 0x25>, <&audma1 0x26>;
2011 dma-names = "rx", "tx";
2012 };
2013 ssiu34: ssiu-28 {
2014 dmas = <&audma0 0x27>, <&audma1 0x28>;
2015 dma-names = "rx", "tx";
2016 };
2017 ssiu35: ssiu-29 {
2018 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2019 dma-names = "rx", "tx";
2020 };
2021 ssiu36: ssiu-30 {
2022 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2023 dma-names = "rx", "tx";
2024 };
2025 ssiu37: ssiu-31 {
2026 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2027 dma-names = "rx", "tx";
2028 };
2029 ssiu40: ssiu-32 {
2030 dmas = <&audma0 0x71>, <&audma1 0x72>;
2031 dma-names = "rx", "tx";
2032 };
2033 ssiu41: ssiu-33 {
2034 dmas = <&audma0 0x17>, <&audma1 0x18>;
2035 dma-names = "rx", "tx";
2036 };
2037 ssiu42: ssiu-34 {
2038 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2039 dma-names = "rx", "tx";
2040 };
2041 ssiu43: ssiu-35 {
2042 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2043 dma-names = "rx", "tx";
2044 };
2045 ssiu44: ssiu-36 {
2046 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2047 dma-names = "rx", "tx";
2048 };
2049 ssiu45: ssiu-37 {
2050 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2051 dma-names = "rx", "tx";
2052 };
2053 ssiu46: ssiu-38 {
2054 dmas = <&audma0 0x31>, <&audma1 0x32>;
2055 dma-names = "rx", "tx";
2056 };
2057 ssiu47: ssiu-39 {
2058 dmas = <&audma0 0x33>, <&audma1 0x34>;
2059 dma-names = "rx", "tx";
2060 };
2061 ssiu50: ssiu-40 {
2062 dmas = <&audma0 0x73>, <&audma1 0x74>;
2063 dma-names = "rx", "tx";
2064 };
2065 ssiu60: ssiu-41 {
2066 dmas = <&audma0 0x75>, <&audma1 0x76>;
2067 dma-names = "rx", "tx";
2068 };
2069 ssiu70: ssiu-42 {
2070 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2071 dma-names = "rx", "tx";
2072 };
2073 ssiu80: ssiu-43 {
2074 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2075 dma-names = "rx", "tx";
2076 };
2077 ssiu90: ssiu-44 {
2078 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2079 dma-names = "rx", "tx";
2080 };
2081 ssiu91: ssiu-45 {
2082 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2083 dma-names = "rx", "tx";
2084 };
2085 ssiu92: ssiu-46 {
2086 dmas = <&audma0 0x81>, <&audma1 0x82>;
2087 dma-names = "rx", "tx";
2088 };
2089 ssiu93: ssiu-47 {
2090 dmas = <&audma0 0x83>, <&audma1 0x84>;
2091 dma-names = "rx", "tx";
2092 };
2093 ssiu94: ssiu-48 {
2094 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2095 dma-names = "rx", "tx";
2096 };
2097 ssiu95: ssiu-49 {
2098 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2099 dma-names = "rx", "tx";
2100 };
2101 ssiu96: ssiu-50 {
2102 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2103 dma-names = "rx", "tx";
2104 };
2105 ssiu97: ssiu-51 {
2106 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2107 dma-names = "rx", "tx";
2108 };
2109 };
2111 rcar_sound,ssi {
2112 ssi0: ssi-0 {
2113 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2114 dmas = <&audma0 0x01>, <&audma1 0x02>;
2115 dma-names = "rx", "tx";
2116 };
2117 ssi1: ssi-1 {
2118 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2119 dmas = <&audma0 0x03>, <&audma1 0x04>;
2120 dma-names = "rx", "tx";
2121 };
2122 ssi2: ssi-2 {
2123 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2124 dmas = <&audma0 0x05>, <&audma1 0x06>;
2125 dma-names = "rx", "tx";
2126 };
2127 ssi3: ssi-3 {
2128 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2129 dmas = <&audma0 0x07>, <&audma1 0x08>;
2130 dma-names = "rx", "tx";
2131 };
2132 ssi4: ssi-4 {
2133 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2134 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2135 dma-names = "rx", "tx";
2136 };
2137 ssi5: ssi-5 {
2138 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2139 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2140 dma-names = "rx", "tx";
2141 };
2142 ssi6: ssi-6 {
2143 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2144 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2145 dma-names = "rx", "tx";
2146 };
2147 ssi7: ssi-7 {
2148 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2149 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2150 dma-names = "rx", "tx";
2151 };
2152 ssi8: ssi-8 {
2153 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2154 dmas = <&audma0 0x11>, <&audma1 0x12>;
2155 dma-names = "rx", "tx";
2156 };
2157 ssi9: ssi-9 {
2158 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2159 dmas = <&audma0 0x13>, <&audma1 0x14>;
2160 dma-names = "rx", "tx";
2161 };
2162 };
2163 };
2165 audma0: dma-controller@ec700000 {
2166 compatible = "renesas,dmac-r8a774e1",
2167 "renesas,rcar-dmac";
2168 reg = <0 0xec700000 0 0x10000>;
2169 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2170 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2171 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2172 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2173 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2174 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2175 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2176 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2177 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2178 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2179 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2180 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2181 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2182 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2183 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2184 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2185 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2186 interrupt-names = "error",
2187 "ch0", "ch1", "ch2", "ch3",
2188 "ch4", "ch5", "ch6", "ch7",
2189 "ch8", "ch9", "ch10", "ch11",
2190 "ch12", "ch13", "ch14", "ch15";
2191 clocks = <&cpg CPG_MOD 502>;
2192 clock-names = "fck";
2193 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2194 resets = <&cpg 502>;
2195 #dma-cells = <1>;
2196 dma-channels = <16>;
2197 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2198 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
2199 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
2200 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
2201 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
2202 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
2203 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
2204 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
2205 };
2207 audma1: dma-controller@ec720000 {
2208 compatible = "renesas,dmac-r8a774e1",
2209 "renesas,rcar-dmac";
2210 reg = <0 0xec720000 0 0x10000>;
2211 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2212 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2213 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2214 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2215 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2216 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2217 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2218 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2219 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2220 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2221 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2222 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2223 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2224 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2226 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2227 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2228 interrupt-names = "error",
2229 "ch0", "ch1", "ch2", "ch3",
2230 "ch4", "ch5", "ch6", "ch7",
2231 "ch8", "ch9", "ch10", "ch11",
2232 "ch12", "ch13", "ch14", "ch15";
2233 clocks = <&cpg CPG_MOD 501>;
2234 clock-names = "fck";
2235 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2236 resets = <&cpg 501>;
2237 #dma-cells = <1>;
2238 dma-channels = <16>;
2239 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
2240 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
2241 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
2242 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
2243 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
2244 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
2245 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
2246 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
2247 };
2249 xhci0: usb@ee000000 {
2250 compatible = "renesas,xhci-r8a774e1",
2251 "renesas,rcar-gen3-xhci";
2252 reg = <0 0xee000000 0 0xc00>;
2253 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2254 clocks = <&cpg CPG_MOD 328>;
2255 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2256 resets = <&cpg 328>;
2257 status = "disabled";
2258 };
2260 usb3_peri0: usb@ee020000 {
2261 compatible = "renesas,r8a774e1-usb3-peri",
2262 "renesas,rcar-gen3-usb3-peri";
2263 reg = <0 0xee020000 0 0x400>;
2264 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2265 clocks = <&cpg CPG_MOD 328>;
2266 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2267 resets = <&cpg 328>;
2268 status = "disabled";
2269 };
2271 ohci0: usb@ee080000 {
2272 compatible = "generic-ohci";
2273 reg = <0 0xee080000 0 0x100>;
2274 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2275 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2276 phys = <&usb2_phy0 1>;
2277 phy-names = "usb";
2278 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2279 resets = <&cpg 703>, <&cpg 704>;
2280 status = "disabled";
2281 };
2283 ohci1: usb@ee0a0000 {
2284 compatible = "generic-ohci";
2285 reg = <0 0xee0a0000 0 0x100>;
2286 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2287 clocks = <&cpg CPG_MOD 702>;
2288 phys = <&usb2_phy1 1>;
2289 phy-names = "usb";
2290 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2291 resets = <&cpg 702>;
2292 status = "disabled";
2293 };
2295 ehci0: usb@ee080100 {
2296 compatible = "generic-ehci";
2297 reg = <0 0xee080100 0 0x100>;
2298 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2299 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2300 phys = <&usb2_phy0 2>;
2301 phy-names = "usb";
2302 companion = <&ohci0>;
2303 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2304 resets = <&cpg 703>, <&cpg 704>;
2305 status = "disabled";
2306 };
2308 ehci1: usb@ee0a0100 {
2309 compatible = "generic-ehci";
2310 reg = <0 0xee0a0100 0 0x100>;
2311 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2312 clocks = <&cpg CPG_MOD 702>;
2313 phys = <&usb2_phy1 2>;
2314 phy-names = "usb";
2315 companion = <&ohci1>;
2316 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2317 resets = <&cpg 702>;
2318 status = "disabled";
2319 };
2321 usb2_phy0: usb-phy@ee080200 {
2322 compatible = "renesas,usb2-phy-r8a774e1",
2323 "renesas,rcar-gen3-usb2-phy";
2324 reg = <0 0xee080200 0 0x700>;
2325 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2326 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2327 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2328 resets = <&cpg 703>, <&cpg 704>;
2329 #phy-cells = <1>;
2330 status = "disabled";
2331 };
2333 usb2_phy1: usb-phy@ee0a0200 {
2334 compatible = "renesas,usb2-phy-r8a774e1",
2335 "renesas,rcar-gen3-usb2-phy";
2336 reg = <0 0xee0a0200 0 0x700>;
2337 clocks = <&cpg CPG_MOD 702>;
2338 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2339 resets = <&cpg 702>;
2340 #phy-cells = <1>;
2341 status = "disabled";
2342 };
2344 sdhi0: mmc@ee100000 {
2345 compatible = "renesas,sdhi-r8a774e1",
2346 "renesas,rcar-gen3-sdhi";
2347 reg = <0 0xee100000 0 0x2000>;
2348 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2349 clocks = <&cpg CPG_MOD 314>;
2350 max-frequency = <200000000>;
2351 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2352 resets = <&cpg 314>;
2353 iommus = <&ipmmu_ds1 32>;
2354 status = "disabled";
2355 };
2357 sdhi1: mmc@ee120000 {
2358 compatible = "renesas,sdhi-r8a774e1",
2359 "renesas,rcar-gen3-sdhi";
2360 reg = <0 0xee120000 0 0x2000>;
2361 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2362 clocks = <&cpg CPG_MOD 313>;
2363 max-frequency = <200000000>;
2364 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2365 resets = <&cpg 313>;
2366 iommus = <&ipmmu_ds1 33>;
2367 status = "disabled";
2368 };
2370 sdhi2: mmc@ee140000 {
2371 compatible = "renesas,sdhi-r8a774e1",
2372 "renesas,rcar-gen3-sdhi";
2373 reg = <0 0xee140000 0 0x2000>;
2374 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2375 clocks = <&cpg CPG_MOD 312>;
2376 max-frequency = <200000000>;
2377 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2378 resets = <&cpg 312>;
2379 iommus = <&ipmmu_ds1 34>;
2380 status = "disabled";
2381 };
2383 sdhi3: mmc@ee160000 {
2384 compatible = "renesas,sdhi-r8a774e1",
2385 "renesas,rcar-gen3-sdhi";
2386 reg = <0 0xee160000 0 0x2000>;
2387 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2388 clocks = <&cpg CPG_MOD 311>;
2389 max-frequency = <200000000>;
2390 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2391 resets = <&cpg 311>;
2392 iommus = <&ipmmu_ds1 35>;
2393 status = "disabled";
2394 };
2396 sata: sata@ee300000 {
2397 compatible = "renesas,sata-r8a774e1",
2398 "renesas,rcar-gen3-sata";
2399 reg = <0 0xee300000 0 0x200000>;
2400 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2401 clocks = <&cpg CPG_MOD 815>;
2402 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2403 resets = <&cpg 815>;
2404 iommus = <&ipmmu_hc 2>;
2405 status = "disabled";
2406 };
2408 gic: interrupt-controller@f1010000 {
2409 compatible = "arm,gic-400";
2410 #interrupt-cells = <3>;
2411 #address-cells = <0>;
2412 interrupt-controller;
2413 reg = <0x0 0xf1010000 0 0x1000>,
2414 <0x0 0xf1020000 0 0x20000>,
2415 <0x0 0xf1040000 0 0x20000>,
2416 <0x0 0xf1060000 0 0x20000>;
2417 interrupts = <GIC_PPI 9
2418 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2419 clocks = <&cpg CPG_MOD 408>;
2420 clock-names = "clk";
2421 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2422 resets = <&cpg 408>;
2423 };
2425 pciec0: pcie@fe000000 {
2426 compatible = "renesas,pcie-r8a774e1",
2427 "renesas,pcie-rcar-gen3";
2428 reg = <0 0xfe000000 0 0x80000>;
2429 #address-cells = <3>;
2430 #size-cells = <2>;
2431 bus-range = <0x00 0xff>;
2432 device_type = "pci";
2433 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2434 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2435 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2436 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2437 /* Map all possible DDR as inbound ranges */
2438 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2439 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2442 #interrupt-cells = <1>;
2443 interrupt-map-mask = <0 0 0 0>;
2444 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2445 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2446 clock-names = "pcie", "pcie_bus";
2447 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2448 resets = <&cpg 319>;
2449 status = "disabled";
2450 };
2452 pciec1: pcie@ee800000 {
2453 compatible = "renesas,pcie-r8a774e1",
2454 "renesas,pcie-rcar-gen3";
2455 reg = <0 0xee800000 0 0x80000>;
2456 #address-cells = <3>;
2457 #size-cells = <2>;
2458 bus-range = <0x00 0xff>;
2459 device_type = "pci";
2460 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2461 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2462 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2463 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2464 /* Map all possible DDR as inbound ranges */
2465 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2466 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2467 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2468 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2469 #interrupt-cells = <1>;
2470 interrupt-map-mask = <0 0 0 0>;
2471 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2472 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2473 clock-names = "pcie", "pcie_bus";
2474 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2475 resets = <&cpg 318>;
2476 status = "disabled";
2477 };
2479 pciec0_ep: pcie-ep@fe000000 {
2480 compatible = "renesas,r8a774e1-pcie-ep",
2481 "renesas,rcar-gen3-pcie-ep";
2482 reg = <0x0 0xfe000000 0 0x80000>,
2483 <0x0 0xfe100000 0 0x100000>,
2484 <0x0 0xfe200000 0 0x200000>,
2485 <0x0 0x30000000 0 0x8000000>,
2486 <0x0 0x38000000 0 0x8000000>;
2487 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2488 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2489 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2490 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2491 clocks = <&cpg CPG_MOD 319>;
2492 clock-names = "pcie";
2493 resets = <&cpg 319>;
2494 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2495 status = "disabled";
2496 };
2498 pciec1_ep: pcie-ep@ee800000 {
2499 compatible = "renesas,r8a774e1-pcie-ep",
2500 "renesas,rcar-gen3-pcie-ep";
2501 reg = <0x0 0xee800000 0 0x80000>,
2502 <0x0 0xee900000 0 0x100000>,
2503 <0x0 0xeea00000 0 0x200000>,
2504 <0x0 0xc0000000 0 0x8000000>,
2505 <0x0 0xc8000000 0 0x8000000>;
2506 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2507 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2508 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2509 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2510 clocks = <&cpg CPG_MOD 318>;
2511 clock-names = "pcie";
2512 resets = <&cpg 318>;
2513 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2514 status = "disabled";
2515 };
2517 vspbc: vsp@fe920000 {
2518 compatible = "renesas,vsp2";
2519 reg = <0 0xfe920000 0 0x8000>;
2520 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
2521 clocks = <&cpg CPG_MOD 624>;
2522 power-domains = <&sysc R8A774E1_PD_A3VP>;
2523 resets = <&cpg 624>;
2525 renesas,fcp = <&fcpvb1>;
2526 };
2528 vspbd: vsp@fe960000 {
2529 compatible = "renesas,vsp2";
2530 reg = <0 0xfe960000 0 0x8000>;
2531 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2532 clocks = <&cpg CPG_MOD 626>;
2533 power-domains = <&sysc R8A774E1_PD_A3VP>;
2534 resets = <&cpg 626>;
2536 renesas,fcp = <&fcpvb0>;
2537 };
2539 vspd0: vsp@fea20000 {
2540 compatible = "renesas,vsp2";
2541 reg = <0 0xfea20000 0 0x5000>;
2542 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2543 clocks = <&cpg CPG_MOD 623>;
2544 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2545 resets = <&cpg 623>;
2547 renesas,fcp = <&fcpvd0>;
2548 };
2550 vspd1: vsp@fea28000 {
2551 compatible = "renesas,vsp2";
2552 reg = <0 0xfea28000 0 0x5000>;
2553 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2554 clocks = <&cpg CPG_MOD 622>;
2555 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2556 resets = <&cpg 622>;
2558 renesas,fcp = <&fcpvd1>;
2559 };
2561 vspi0: vsp@fe9a0000 {
2562 compatible = "renesas,vsp2";
2563 reg = <0 0xfe9a0000 0 0x8000>;
2564 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2565 clocks = <&cpg CPG_MOD 631>;
2566 power-domains = <&sysc R8A774E1_PD_A3VP>;
2567 resets = <&cpg 631>;
2569 renesas,fcp = <&fcpvi0>;
2570 };
2572 vspi1: vsp@fe9b0000 {
2573 compatible = "renesas,vsp2";
2574 reg = <0 0xfe9b0000 0 0x8000>;
2575 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
2576 clocks = <&cpg CPG_MOD 630>;
2577 power-domains = <&sysc R8A774E1_PD_A3VP>;
2578 resets = <&cpg 630>;
2580 renesas,fcp = <&fcpvi1>;
2581 };
2583 fdp1@fe940000 {
2584 compatible = "renesas,fdp1";
2585 reg = <0 0xfe940000 0 0x2400>;
2586 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2587 clocks = <&cpg CPG_MOD 119>;
2588 power-domains = <&sysc R8A774E1_PD_A3VP>;
2589 resets = <&cpg 119>;
2590 renesas,fcp = <&fcpf0>;
2591 };
2593 fdp1@fe944000 {
2594 compatible = "renesas,fdp1";
2595 reg = <0 0xfe944000 0 0x2400>;
2596 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2597 clocks = <&cpg CPG_MOD 118>;
2598 power-domains = <&sysc R8A774E1_PD_A3VP>;
2599 resets = <&cpg 118>;
2600 renesas,fcp = <&fcpf1>;
2601 };
2603 fcpf0: fcp@fe950000 {
2604 compatible = "renesas,fcpf";
2605 reg = <0 0xfe950000 0 0x200>;
2606 clocks = <&cpg CPG_MOD 615>;
2607 power-domains = <&sysc R8A774E1_PD_A3VP>;
2608 resets = <&cpg 615>;
2609 };
2611 fcpf1: fcp@fe951000 {
2612 compatible = "renesas,fcpf";
2613 reg = <0 0xfe951000 0 0x200>;
2614 clocks = <&cpg CPG_MOD 614>;
2615 power-domains = <&sysc R8A774E1_PD_A3VP>;
2616 resets = <&cpg 614>;
2617 };
2619 fcpvb0: fcp@fe96f000 {
2620 compatible = "renesas,fcpv";
2621 reg = <0 0xfe96f000 0 0x200>;
2622 clocks = <&cpg CPG_MOD 607>;
2623 power-domains = <&sysc R8A774E1_PD_A3VP>;
2624 resets = <&cpg 607>;
2625 };
2627 fcpvb1: fcp@fe92f000 {
2628 compatible = "renesas,fcpv";
2629 reg = <0 0xfe92f000 0 0x200>;
2630 clocks = <&cpg CPG_MOD 606>;
2631 power-domains = <&sysc R8A774E1_PD_A3VP>;
2632 resets = <&cpg 606>;
2633 };
2635 fcpvi0: fcp@fe9af000 {
2636 compatible = "renesas,fcpv";
2637 reg = <0 0xfe9af000 0 0x200>;
2638 clocks = <&cpg CPG_MOD 611>;
2639 power-domains = <&sysc R8A774E1_PD_A3VP>;
2640 resets = <&cpg 611>;
2641 };
2643 fcpvi1: fcp@fe9bf000 {
2644 compatible = "renesas,fcpv";
2645 reg = <0 0xfe9bf000 0 0x200>;
2646 clocks = <&cpg CPG_MOD 610>;
2647 power-domains = <&sysc R8A774E1_PD_A3VP>;
2648 resets = <&cpg 610>;
2649 };
2651 fcpvd0: fcp@fea27000 {
2652 compatible = "renesas,fcpv";
2653 reg = <0 0xfea27000 0 0x200>;
2654 clocks = <&cpg CPG_MOD 603>;
2655 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2656 resets = <&cpg 603>;
2657 };
2659 fcpvd1: fcp@fea2f000 {
2660 compatible = "renesas,fcpv";
2661 reg = <0 0xfea2f000 0 0x200>;
2662 clocks = <&cpg CPG_MOD 602>;
2663 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2664 resets = <&cpg 602>;
2665 };
2667 csi20: csi2@fea80000 {
2668 compatible = "renesas,r8a774e1-csi2";
2669 reg = <0 0xfea80000 0 0x10000>;
2670 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2671 clocks = <&cpg CPG_MOD 714>;
2672 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2673 resets = <&cpg 714>;
2674 status = "disabled";
2676 ports {
2677 #address-cells = <1>;
2678 #size-cells = <0>;
2680 port@1 {
2681 #address-cells = <1>;
2682 #size-cells = <0>;
2684 reg = <1>;
2686 csi20vin0: endpoint@0 {
2687 reg = <0>;
2688 remote-endpoint = <&vin0csi20>;
2689 };
2690 csi20vin1: endpoint@1 {
2691 reg = <1>;
2692 remote-endpoint = <&vin1csi20>;
2693 };
2694 csi20vin2: endpoint@2 {
2695 reg = <2>;
2696 remote-endpoint = <&vin2csi20>;
2697 };
2698 csi20vin3: endpoint@3 {
2699 reg = <3>;
2700 remote-endpoint = <&vin3csi20>;
2701 };
2702 csi20vin4: endpoint@4 {
2703 reg = <4>;
2704 remote-endpoint = <&vin4csi20>;
2705 };
2706 csi20vin5: endpoint@5 {
2707 reg = <5>;
2708 remote-endpoint = <&vin5csi20>;
2709 };
2710 csi20vin6: endpoint@6 {
2711 reg = <6>;
2712 remote-endpoint = <&vin6csi20>;
2713 };
2714 csi20vin7: endpoint@7 {
2715 reg = <7>;
2716 remote-endpoint = <&vin7csi20>;
2717 };
2718 };
2719 };
2720 };
2722 csi40: csi2@feaa0000 {
2723 compatible = "renesas,r8a774e1-csi2";
2724 reg = <0 0xfeaa0000 0 0x10000>;
2725 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2726 clocks = <&cpg CPG_MOD 716>;
2727 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2728 resets = <&cpg 716>;
2729 status = "disabled";
2731 ports {
2732 #address-cells = <1>;
2733 #size-cells = <0>;
2735 port@1 {
2736 #address-cells = <1>;
2737 #size-cells = <0>;
2739 reg = <1>;
2741 csi40vin0: endpoint@0 {
2742 reg = <0>;
2743 remote-endpoint = <&vin0csi40>;
2744 };
2745 csi40vin1: endpoint@1 {
2746 reg = <1>;
2747 remote-endpoint = <&vin1csi40>;
2748 };
2749 csi40vin2: endpoint@2 {
2750 reg = <2>;
2751 remote-endpoint = <&vin2csi40>;
2752 };
2753 csi40vin3: endpoint@3 {
2754 reg = <3>;
2755 remote-endpoint = <&vin3csi40>;
2756 };
2757 };
2758 };
2759 };
2761 hdmi0: hdmi@fead0000 {
2762 compatible = "renesas,r8a774e1-hdmi",
2763 "renesas,rcar-gen3-hdmi";
2764 reg = <0 0xfead0000 0 0x10000>;
2765 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2766 clocks = <&cpg CPG_MOD 729>,
2767 <&cpg CPG_CORE R8A774E1_CLK_HDMI>;
2768 clock-names = "iahb", "isfr";
2769 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2770 resets = <&cpg 729>;
2771 status = "disabled";
2773 ports {
2774 #address-cells = <1>;
2775 #size-cells = <0>;
2777 port@0 {
2778 reg = <0>;
2779 dw_hdmi0_in: endpoint {
2780 remote-endpoint = <&du_out_hdmi0>;
2781 };
2782 };
2783 port@1 {
2784 reg = <1>;
2785 };
2786 port@2 {
2787 /* HDMI sound */
2788 reg = <2>;
2789 };
2790 };
2791 };
2793 du: display@feb00000 {
2794 compatible = "renesas,du-r8a774e1";
2795 reg = <0 0xfeb00000 0 0x80000>;
2796 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2797 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2798 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
2799 clocks = <&cpg CPG_MOD 724>,
2800 <&cpg CPG_MOD 723>,
2801 <&cpg CPG_MOD 721>;
2802 clock-names = "du.0", "du.1", "du.3";
2803 resets = <&cpg 724>, <&cpg 722>;
2804 reset-names = "du.0", "du.3";
2805 status = "disabled";
2807 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2809 ports {
2810 #address-cells = <1>;
2811 #size-cells = <0>;
2813 port@0 {
2814 reg = <0>;
2815 du_out_rgb: endpoint {
2816 };
2817 };
2818 port@1 {
2819 reg = <1>;
2820 du_out_hdmi0: endpoint {
2821 remote-endpoint = <&dw_hdmi0_in>;
2822 };
2823 };
2824 port@2 {
2825 reg = <2>;
2826 du_out_lvds0: endpoint {
2827 remote-endpoint = <&lvds0_in>;
2828 };
2829 };
2830 };
2831 };
2833 lvds0: lvds@feb90000 {
2834 compatible = "renesas,r8a774e1-lvds";
2835 reg = <0 0xfeb90000 0 0x14>;
2836 clocks = <&cpg CPG_MOD 727>;
2837 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2838 resets = <&cpg 727>;
2839 status = "disabled";
2841 ports {
2842 #address-cells = <1>;
2843 #size-cells = <0>;
2845 port@0 {
2846 reg = <0>;
2847 lvds0_in: endpoint {
2848 remote-endpoint = <&du_out_lvds0>;
2849 };
2850 };
2851 port@1 {
2852 reg = <1>;
2853 lvds0_out: endpoint {
2854 };
2855 };
2856 };
2857 };
2859 prr: chipid@fff00044 {
2860 compatible = "renesas,prr";
2861 reg = <0 0xfff00044 0 4>;
2862 };
2863 };
2865 thermal-zones {
2866 sensor_thermal1: sensor-thermal1 {
2867 polling-delay-passive = <250>;
2868 polling-delay = <1000>;
2869 thermal-sensors = <&tsc 0>;
2870 sustainable-power = <6313>;
2872 trips {
2873 sensor1_crit: sensor1-crit {
2874 temperature = <120000>;
2875 hysteresis = <1000>;
2876 type = "critical";
2877 };
2878 };
2879 };
2881 sensor_thermal2: sensor-thermal2 {
2882 polling-delay-passive = <250>;
2883 polling-delay = <1000>;
2884 thermal-sensors = <&tsc 1>;
2885 sustainable-power = <6313>;
2887 trips {
2888 sensor2_crit: sensor2-crit {
2889 temperature = <120000>;
2890 hysteresis = <1000>;
2891 type = "critical";
2892 };
2893 };
2894 };
2896 sensor_thermal3: sensor-thermal3 {
2897 polling-delay-passive = <250>;
2898 polling-delay = <1000>;
2899 thermal-sensors = <&tsc 2>;
2900 sustainable-power = <6313>;
2902 trips {
2903 target: trip-point1 {
2904 temperature = <100000>;
2905 hysteresis = <1000>;
2906 type = "passive";
2907 };
2909 sensor3_crit: sensor3-crit {
2910 temperature = <120000>;
2911 hysteresis = <1000>;
2912 type = "critical";
2913 };
2914 };
2916 cooling-maps {
2917 map0 {
2918 trip = <&target>;
2919 cooling-device = <&a57_0 0 2>;
2920 contribution = <1024>;
2921 };
2923 map1 {
2924 trip = <&target>;
2925 cooling-device = <&a53_0 0 2>;
2926 contribution = <1024>;
2927 };
2928 };
2929 };
2930 };
2932 timer {
2933 compatible = "arm,armv8-timer";
2934 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2935 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2936 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2937 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2938 };
2940 /* External USB clocks - can be overridden by the board */
2941 usb3s0_clk: usb3s0 {
2942 compatible = "fixed-clock";
2943 #clock-cells = <0>;
2944 clock-frequency = <0>;
2945 };
2947 usb_extal_clk: usb_extal {
2948 compatible = "fixed-clock";
2949 #clock-cells = <0>;
2950 clock-frequency = <0>;
2951 };
2952 };