| blob | e1af7c4782f4d7684d6e4e0e8aab5bb1eceb2dde |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba
7 */
9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a77995-sysc.h>
13 / {
14 compatible = "renesas,r8a77995";
15 #address-cells = <2>;
16 #size-cells = <2>;
18 /* External CAN clock - to be overridden by boards that provide it */
19 can_clk: can {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <0>;
23 };
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
29 a53_0: cpu@0 {
30 compatible = "arm,cortex-a53";
31 reg = <0x0>;
32 device_type = "cpu";
33 power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
34 next-level-cache = <&L2_CA53>;
35 enable-method = "psci";
36 };
38 L2_CA53: cache-controller-1 {
39 compatible = "cache";
40 power-domains = <&sysc R8A77995_PD_CA53_SCU>;
41 cache-unified;
42 cache-level = <2>;
43 };
44 };
46 extal_clk: extal {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 /* This value must be overridden by the board */
50 clock-frequency = <0>;
51 };
53 pmu_a53 {
54 compatible = "arm,cortex-a53-pmu";
55 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
56 };
58 psci {
59 compatible = "arm,psci-1.0", "arm,psci-0.2";
60 method = "smc";
61 };
63 scif_clk: scif {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
67 };
69 soc {
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
72 #address-cells = <2>;
73 #size-cells = <2>;
74 ranges;
76 rwdt: watchdog@e6020000 {
77 compatible = "renesas,r8a77995-wdt",
78 "renesas,rcar-gen3-wdt";
79 reg = <0 0xe6020000 0 0x0c>;
80 clocks = <&cpg CPG_MOD 402>;
81 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
82 resets = <&cpg 402>;
83 status = "disabled";
84 };
86 gpio0: gpio@e6050000 {
87 compatible = "renesas,gpio-r8a77995",
88 "renesas,rcar-gen3-gpio";
89 reg = <0 0xe6050000 0 0x50>;
90 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
91 #gpio-cells = <2>;
92 gpio-controller;
93 gpio-ranges = <&pfc 0 0 9>;
94 #interrupt-cells = <2>;
95 interrupt-controller;
96 clocks = <&cpg CPG_MOD 912>;
97 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
98 resets = <&cpg 912>;
99 };
101 gpio1: gpio@e6051000 {
102 compatible = "renesas,gpio-r8a77995",
103 "renesas,rcar-gen3-gpio";
104 reg = <0 0xe6051000 0 0x50>;
105 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
106 #gpio-cells = <2>;
107 gpio-controller;
108 gpio-ranges = <&pfc 0 32 32>;
109 #interrupt-cells = <2>;
110 interrupt-controller;
111 clocks = <&cpg CPG_MOD 911>;
112 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
113 resets = <&cpg 911>;
114 };
116 gpio2: gpio@e6052000 {
117 compatible = "renesas,gpio-r8a77995",
118 "renesas,rcar-gen3-gpio";
119 reg = <0 0xe6052000 0 0x50>;
120 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
121 #gpio-cells = <2>;
122 gpio-controller;
123 gpio-ranges = <&pfc 0 64 32>;
124 #interrupt-cells = <2>;
125 interrupt-controller;
126 clocks = <&cpg CPG_MOD 910>;
127 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
128 resets = <&cpg 910>;
129 };
131 gpio3: gpio@e6053000 {
132 compatible = "renesas,gpio-r8a77995",
133 "renesas,rcar-gen3-gpio";
134 reg = <0 0xe6053000 0 0x50>;
135 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
136 #gpio-cells = <2>;
137 gpio-controller;
138 gpio-ranges = <&pfc 0 96 10>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
141 clocks = <&cpg CPG_MOD 909>;
142 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
143 resets = <&cpg 909>;
144 };
146 gpio4: gpio@e6054000 {
147 compatible = "renesas,gpio-r8a77995",
148 "renesas,rcar-gen3-gpio";
149 reg = <0 0xe6054000 0 0x50>;
150 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
151 #gpio-cells = <2>;
152 gpio-controller;
153 gpio-ranges = <&pfc 0 128 32>;
154 #interrupt-cells = <2>;
155 interrupt-controller;
156 clocks = <&cpg CPG_MOD 908>;
157 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
158 resets = <&cpg 908>;
159 };
161 gpio5: gpio@e6055000 {
162 compatible = "renesas,gpio-r8a77995",
163 "renesas,rcar-gen3-gpio";
164 reg = <0 0xe6055000 0 0x50>;
165 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
166 #gpio-cells = <2>;
167 gpio-controller;
168 gpio-ranges = <&pfc 0 160 21>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
171 clocks = <&cpg CPG_MOD 907>;
172 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
173 resets = <&cpg 907>;
174 };
176 gpio6: gpio@e6055400 {
177 compatible = "renesas,gpio-r8a77995",
178 "renesas,rcar-gen3-gpio";
179 reg = <0 0xe6055400 0 0x50>;
180 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
181 #gpio-cells = <2>;
182 gpio-controller;
183 gpio-ranges = <&pfc 0 192 14>;
184 #interrupt-cells = <2>;
185 interrupt-controller;
186 clocks = <&cpg CPG_MOD 906>;
187 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
188 resets = <&cpg 906>;
189 };
191 pfc: pinctrl@e6060000 {
192 compatible = "renesas,pfc-r8a77995";
193 reg = <0 0xe6060000 0 0x508>;
194 };
196 cpg: clock-controller@e6150000 {
197 compatible = "renesas,r8a77995-cpg-mssr";
198 reg = <0 0xe6150000 0 0x1000>;
199 clocks = <&extal_clk>;
200 clock-names = "extal";
201 #clock-cells = <2>;
202 #power-domain-cells = <0>;
203 #reset-cells = <1>;
204 };
206 rst: reset-controller@e6160000 {
207 compatible = "renesas,r8a77995-rst";
208 reg = <0 0xe6160000 0 0x0200>;
209 };
211 sysc: system-controller@e6180000 {
212 compatible = "renesas,r8a77995-sysc";
213 reg = <0 0xe6180000 0 0x0400>;
214 #power-domain-cells = <1>;
215 };
217 thermal: thermal@e6190000 {
218 compatible = "renesas,thermal-r8a77995";
219 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
220 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cpg CPG_MOD 522>;
224 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
225 resets = <&cpg 522>;
226 #thermal-sensor-cells = <0>;
227 };
229 intc_ex: interrupt-controller@e61c0000 {
230 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
231 #interrupt-cells = <2>;
232 interrupt-controller;
233 reg = <0 0xe61c0000 0 0x200>;
234 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cpg CPG_MOD 407>;
241 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
242 resets = <&cpg 407>;
243 };
245 i2c0: i2c@e6500000 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "renesas,i2c-r8a77995",
249 "renesas,rcar-gen3-i2c";
250 reg = <0 0xe6500000 0 0x40>;
251 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&cpg CPG_MOD 931>;
253 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
254 resets = <&cpg 931>;
255 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
256 <&dmac2 0x91>, <&dmac2 0x90>;
257 dma-names = "tx", "rx", "tx", "rx";
258 i2c-scl-internal-delay-ns = <6>;
259 status = "disabled";
260 };
262 i2c1: i2c@e6508000 {
263 #address-cells = <1>;
264 #size-cells = <0>;
265 compatible = "renesas,i2c-r8a77995",
266 "renesas,rcar-gen3-i2c";
267 reg = <0 0xe6508000 0 0x40>;
268 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cpg CPG_MOD 930>;
270 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
271 resets = <&cpg 930>;
272 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
273 <&dmac2 0x93>, <&dmac2 0x92>;
274 dma-names = "tx", "rx", "tx", "rx";
275 i2c-scl-internal-delay-ns = <6>;
276 status = "disabled";
277 };
279 i2c2: i2c@e6510000 {
280 #address-cells = <1>;
281 #size-cells = <0>;
282 compatible = "renesas,i2c-r8a77995",
283 "renesas,rcar-gen3-i2c";
284 reg = <0 0xe6510000 0 0x40>;
285 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&cpg CPG_MOD 929>;
287 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
288 resets = <&cpg 929>;
289 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
290 <&dmac2 0x95>, <&dmac2 0x94>;
291 dma-names = "tx", "rx", "tx", "rx";
292 i2c-scl-internal-delay-ns = <6>;
293 status = "disabled";
294 };
296 i2c3: i2c@e66d0000 {
297 #address-cells = <1>;
298 #size-cells = <0>;
299 compatible = "renesas,i2c-r8a77995",
300 "renesas,rcar-gen3-i2c";
301 reg = <0 0xe66d0000 0 0x40>;
302 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&cpg CPG_MOD 928>;
304 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
305 resets = <&cpg 928>;
306 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
307 dma-names = "tx", "rx";
308 i2c-scl-internal-delay-ns = <6>;
309 status = "disabled";
310 };
312 hscif0: serial@e6540000 {
313 compatible = "renesas,hscif-r8a77995",
314 "renesas,rcar-gen3-hscif",
315 "renesas,hscif";
316 reg = <0 0xe6540000 0 0x60>;
317 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cpg CPG_MOD 520>,
319 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
320 <&scif_clk>;
321 clock-names = "fck", "brg_int", "scif_clk";
322 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
323 <&dmac2 0x31>, <&dmac2 0x30>;
324 dma-names = "tx", "rx", "tx", "rx";
325 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
326 resets = <&cpg 520>;
327 status = "disabled";
328 };
330 hscif3: serial@e66a0000 {
331 compatible = "renesas,hscif-r8a77995",
332 "renesas,rcar-gen3-hscif",
333 "renesas,hscif";
334 reg = <0 0xe66a0000 0 0x60>;
335 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&cpg CPG_MOD 517>,
337 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
338 <&scif_clk>;
339 clock-names = "fck", "brg_int", "scif_clk";
340 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
341 dma-names = "tx", "rx";
342 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
343 resets = <&cpg 517>;
344 status = "disabled";
345 };
347 hsusb: usb@e6590000 {
348 compatible = "renesas,usbhs-r8a77995",
349 "renesas,rcar-gen3-usbhs";
350 reg = <0 0xe6590000 0 0x200>;
351 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
353 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
354 <&usb_dmac1 0>, <&usb_dmac1 1>;
355 dma-names = "ch0", "ch1", "ch2", "ch3";
356 renesas,buswait = <11>;
357 phys = <&usb2_phy0 3>;
358 phy-names = "usb";
359 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
360 resets = <&cpg 704>, <&cpg 703>;
361 status = "disabled";
362 };
364 usb_dmac0: dma-controller@e65a0000 {
365 compatible = "renesas,r8a77995-usb-dmac",
366 "renesas,usb-dmac";
367 reg = <0 0xe65a0000 0 0x100>;
368 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
370 interrupt-names = "ch0", "ch1";
371 clocks = <&cpg CPG_MOD 330>;
372 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
373 resets = <&cpg 330>;
374 #dma-cells = <1>;
375 dma-channels = <2>;
376 };
378 usb_dmac1: dma-controller@e65b0000 {
379 compatible = "renesas,r8a77995-usb-dmac",
380 "renesas,usb-dmac";
381 reg = <0 0xe65b0000 0 0x100>;
382 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
384 interrupt-names = "ch0", "ch1";
385 clocks = <&cpg CPG_MOD 331>;
386 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
387 resets = <&cpg 331>;
388 #dma-cells = <1>;
389 dma-channels = <2>;
390 };
392 arm_cc630p: crypto@e6601000 {
393 compatible = "arm,cryptocell-630p-ree";
394 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
395 reg = <0x0 0xe6601000 0 0x1000>;
396 clocks = <&cpg CPG_MOD 229>;
397 resets = <&cpg 229>;
398 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
399 };
401 canfd: can@e66c0000 {
402 compatible = "renesas,r8a77995-canfd",
403 "renesas,rcar-gen3-canfd";
404 reg = <0 0xe66c0000 0 0x8000>;
405 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&cpg CPG_MOD 914>,
408 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
409 <&can_clk>;
410 clock-names = "fck", "canfd", "can_clk";
411 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
412 assigned-clock-rates = <40000000>;
413 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
414 resets = <&cpg 914>;
415 status = "disabled";
417 channel0 {
418 status = "disabled";
419 };
421 channel1 {
422 status = "disabled";
423 };
424 };
426 dmac0: dma-controller@e6700000 {
427 compatible = "renesas,dmac-r8a77995",
428 "renesas,rcar-dmac";
429 reg = <0 0xe6700000 0 0x10000>;
430 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
439 interrupt-names = "error",
440 "ch0", "ch1", "ch2", "ch3",
441 "ch4", "ch5", "ch6", "ch7";
442 clocks = <&cpg CPG_MOD 219>;
443 clock-names = "fck";
444 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
445 resets = <&cpg 219>;
446 #dma-cells = <1>;
447 dma-channels = <8>;
448 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
449 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
450 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
451 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
452 };
454 dmac1: dma-controller@e7300000 {
455 compatible = "renesas,dmac-r8a77995",
456 "renesas,rcar-dmac";
457 reg = <0 0xe7300000 0 0x10000>;
458 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
467 interrupt-names = "error",
468 "ch0", "ch1", "ch2", "ch3",
469 "ch4", "ch5", "ch6", "ch7";
470 clocks = <&cpg CPG_MOD 218>;
471 clock-names = "fck";
472 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
473 resets = <&cpg 218>;
474 #dma-cells = <1>;
475 dma-channels = <8>;
476 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
477 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
478 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
479 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
480 };
482 dmac2: dma-controller@e7310000 {
483 compatible = "renesas,dmac-r8a77995",
484 "renesas,rcar-dmac";
485 reg = <0 0xe7310000 0 0x10000>;
486 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
495 interrupt-names = "error",
496 "ch0", "ch1", "ch2", "ch3",
497 "ch4", "ch5", "ch6", "ch7";
498 clocks = <&cpg CPG_MOD 217>;
499 clock-names = "fck";
500 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
501 resets = <&cpg 217>;
502 #dma-cells = <1>;
503 dma-channels = <8>;
504 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
505 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
506 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
507 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
508 };
510 ipmmu_ds0: iommu@e6740000 {
511 compatible = "renesas,ipmmu-r8a77995";
512 reg = <0 0xe6740000 0 0x1000>;
513 renesas,ipmmu-main = <&ipmmu_mm 0>;
514 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
515 #iommu-cells = <1>;
516 };
518 ipmmu_ds1: iommu@e7740000 {
519 compatible = "renesas,ipmmu-r8a77995";
520 reg = <0 0xe7740000 0 0x1000>;
521 renesas,ipmmu-main = <&ipmmu_mm 1>;
522 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
523 #iommu-cells = <1>;
524 };
526 ipmmu_hc: iommu@e6570000 {
527 compatible = "renesas,ipmmu-r8a77995";
528 reg = <0 0xe6570000 0 0x1000>;
529 renesas,ipmmu-main = <&ipmmu_mm 2>;
530 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
531 #iommu-cells = <1>;
532 };
534 ipmmu_mm: iommu@e67b0000 {
535 compatible = "renesas,ipmmu-r8a77995";
536 reg = <0 0xe67b0000 0 0x1000>;
537 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
539 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
540 #iommu-cells = <1>;
541 };
543 ipmmu_mp: iommu@ec670000 {
544 compatible = "renesas,ipmmu-r8a77995";
545 reg = <0 0xec670000 0 0x1000>;
546 renesas,ipmmu-main = <&ipmmu_mm 4>;
547 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
548 #iommu-cells = <1>;
549 };
551 ipmmu_pv0: iommu@fd800000 {
552 compatible = "renesas,ipmmu-r8a77995";
553 reg = <0 0xfd800000 0 0x1000>;
554 renesas,ipmmu-main = <&ipmmu_mm 6>;
555 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
556 #iommu-cells = <1>;
557 };
559 ipmmu_rt: iommu@ffc80000 {
560 compatible = "renesas,ipmmu-r8a77995";
561 reg = <0 0xffc80000 0 0x1000>;
562 renesas,ipmmu-main = <&ipmmu_mm 10>;
563 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
564 #iommu-cells = <1>;
565 };
567 ipmmu_vc0: iommu@fe6b0000 {
568 compatible = "renesas,ipmmu-r8a77995";
569 reg = <0 0xfe6b0000 0 0x1000>;
570 renesas,ipmmu-main = <&ipmmu_mm 12>;
571 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
572 #iommu-cells = <1>;
573 };
575 ipmmu_vi0: iommu@febd0000 {
576 compatible = "renesas,ipmmu-r8a77995";
577 reg = <0 0xfebd0000 0 0x1000>;
578 renesas,ipmmu-main = <&ipmmu_mm 14>;
579 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
580 #iommu-cells = <1>;
581 };
583 ipmmu_vp0: iommu@fe990000 {
584 compatible = "renesas,ipmmu-r8a77995";
585 reg = <0 0xfe990000 0 0x1000>;
586 renesas,ipmmu-main = <&ipmmu_mm 16>;
587 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
588 #iommu-cells = <1>;
589 };
591 avb: ethernet@e6800000 {
592 compatible = "renesas,etheravb-r8a77995",
593 "renesas,etheravb-rcar-gen3";
594 reg = <0 0xe6800000 0 0x800>;
595 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
620 interrupt-names = "ch0", "ch1", "ch2", "ch3",
621 "ch4", "ch5", "ch6", "ch7",
622 "ch8", "ch9", "ch10", "ch11",
623 "ch12", "ch13", "ch14", "ch15",
624 "ch16", "ch17", "ch18", "ch19",
625 "ch20", "ch21", "ch22", "ch23",
626 "ch24";
627 clocks = <&cpg CPG_MOD 812>;
628 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
629 resets = <&cpg 812>;
630 phy-mode = "rgmii";
631 rx-internal-delay-ps = <1800>;
632 iommus = <&ipmmu_ds0 16>;
633 #address-cells = <1>;
634 #size-cells = <0>;
635 status = "disabled";
636 };
638 can0: can@e6c30000 {
639 compatible = "renesas,can-r8a77995",
640 "renesas,rcar-gen3-can";
641 reg = <0 0xe6c30000 0 0x1000>;
642 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&cpg CPG_MOD 916>,
644 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
645 <&can_clk>;
646 clock-names = "clkp1", "clkp2", "can_clk";
647 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
648 assigned-clock-rates = <40000000>;
649 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
650 resets = <&cpg 916>;
651 status = "disabled";
652 };
654 can1: can@e6c38000 {
655 compatible = "renesas,can-r8a77995",
656 "renesas,rcar-gen3-can";
657 reg = <0 0xe6c38000 0 0x1000>;
658 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&cpg CPG_MOD 915>,
660 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
661 <&can_clk>;
662 clock-names = "clkp1", "clkp2", "can_clk";
663 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
664 assigned-clock-rates = <40000000>;
665 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
666 resets = <&cpg 915>;
667 status = "disabled";
668 };
670 pwm0: pwm@e6e30000 {
671 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
672 reg = <0 0xe6e30000 0 0x8>;
673 #pwm-cells = <2>;
674 clocks = <&cpg CPG_MOD 523>;
675 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
676 resets = <&cpg 523>;
677 status = "disabled";
678 };
680 pwm1: pwm@e6e31000 {
681 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
682 reg = <0 0xe6e31000 0 0x8>;
683 #pwm-cells = <2>;
684 clocks = <&cpg CPG_MOD 523>;
685 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
686 resets = <&cpg 523>;
687 status = "disabled";
688 };
690 pwm2: pwm@e6e32000 {
691 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
692 reg = <0 0xe6e32000 0 0x8>;
693 #pwm-cells = <2>;
694 clocks = <&cpg CPG_MOD 523>;
695 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
696 resets = <&cpg 523>;
697 status = "disabled";
698 };
700 pwm3: pwm@e6e33000 {
701 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
702 reg = <0 0xe6e33000 0 0x8>;
703 #pwm-cells = <2>;
704 clocks = <&cpg CPG_MOD 523>;
705 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
706 resets = <&cpg 523>;
707 status = "disabled";
708 };
710 scif0: serial@e6e60000 {
711 compatible = "renesas,scif-r8a77995",
712 "renesas,rcar-gen3-scif", "renesas,scif";
713 reg = <0 0xe6e60000 0 64>;
714 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&cpg CPG_MOD 207>,
716 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
717 <&scif_clk>;
718 clock-names = "fck", "brg_int", "scif_clk";
719 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
720 <&dmac2 0x51>, <&dmac2 0x50>;
721 dma-names = "tx", "rx", "tx", "rx";
722 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
723 resets = <&cpg 207>;
724 status = "disabled";
725 };
727 scif1: serial@e6e68000 {
728 compatible = "renesas,scif-r8a77995",
729 "renesas,rcar-gen3-scif", "renesas,scif";
730 reg = <0 0xe6e68000 0 64>;
731 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&cpg CPG_MOD 206>,
733 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
734 <&scif_clk>;
735 clock-names = "fck", "brg_int", "scif_clk";
736 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
737 <&dmac2 0x53>, <&dmac2 0x52>;
738 dma-names = "tx", "rx", "tx", "rx";
739 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
740 resets = <&cpg 206>;
741 status = "disabled";
742 };
744 scif2: serial@e6e88000 {
745 compatible = "renesas,scif-r8a77995",
746 "renesas,rcar-gen3-scif", "renesas,scif";
747 reg = <0 0xe6e88000 0 64>;
748 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&cpg CPG_MOD 310>,
750 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
751 <&scif_clk>;
752 clock-names = "fck", "brg_int", "scif_clk";
753 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
754 <&dmac2 0x13>, <&dmac2 0x12>;
755 dma-names = "tx", "rx", "tx", "rx";
756 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
757 resets = <&cpg 310>;
758 status = "disabled";
759 };
761 scif3: serial@e6c50000 {
762 compatible = "renesas,scif-r8a77995",
763 "renesas,rcar-gen3-scif", "renesas,scif";
764 reg = <0 0xe6c50000 0 64>;
765 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&cpg CPG_MOD 204>,
767 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
768 <&scif_clk>;
769 clock-names = "fck", "brg_int", "scif_clk";
770 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
771 dma-names = "tx", "rx";
772 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
773 resets = <&cpg 204>;
774 status = "disabled";
775 };
777 scif4: serial@e6c40000 {
778 compatible = "renesas,scif-r8a77995",
779 "renesas,rcar-gen3-scif", "renesas,scif";
780 reg = <0 0xe6c40000 0 64>;
781 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&cpg CPG_MOD 203>,
783 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
784 <&scif_clk>;
785 clock-names = "fck", "brg_int", "scif_clk";
786 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
787 dma-names = "tx", "rx";
788 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
789 resets = <&cpg 203>;
790 status = "disabled";
791 };
793 scif5: serial@e6f30000 {
794 compatible = "renesas,scif-r8a77995",
795 "renesas,rcar-gen3-scif", "renesas,scif";
796 reg = <0 0xe6f30000 0 64>;
797 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&cpg CPG_MOD 202>,
799 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
800 <&scif_clk>;
801 clock-names = "fck", "brg_int", "scif_clk";
802 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
803 <&dmac2 0x5b>, <&dmac2 0x5a>;
804 dma-names = "tx", "rx", "tx", "rx";
805 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
806 resets = <&cpg 202>;
807 status = "disabled";
808 };
810 msiof0: spi@e6e90000 {
811 compatible = "renesas,msiof-r8a77995",
812 "renesas,rcar-gen3-msiof";
813 reg = <0 0xe6e90000 0 0x64>;
814 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&cpg CPG_MOD 211>;
816 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
817 <&dmac2 0x41>, <&dmac2 0x40>;
818 dma-names = "tx", "rx", "tx", "rx";
819 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
820 resets = <&cpg 211>;
821 #address-cells = <1>;
822 #size-cells = <0>;
823 status = "disabled";
824 };
826 msiof1: spi@e6ea0000 {
827 compatible = "renesas,msiof-r8a77995",
828 "renesas,rcar-gen3-msiof";
829 reg = <0 0xe6ea0000 0 0x64>;
830 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&cpg CPG_MOD 210>;
832 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
833 <&dmac2 0x43>, <&dmac2 0x42>;
834 dma-names = "tx", "rx", "tx", "rx";
835 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
836 resets = <&cpg 210>;
837 #address-cells = <1>;
838 #size-cells = <0>;
839 status = "disabled";
840 };
842 msiof2: spi@e6c00000 {
843 compatible = "renesas,msiof-r8a77995",
844 "renesas,rcar-gen3-msiof";
845 reg = <0 0xe6c00000 0 0x64>;
846 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&cpg CPG_MOD 209>;
848 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
849 dma-names = "tx", "rx";
850 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
851 resets = <&cpg 209>;
852 #address-cells = <1>;
853 #size-cells = <0>;
854 status = "disabled";
855 };
857 msiof3: spi@e6c10000 {
858 compatible = "renesas,msiof-r8a77995",
859 "renesas,rcar-gen3-msiof";
860 reg = <0 0xe6c10000 0 0x64>;
861 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&cpg CPG_MOD 208>;
863 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
864 dma-names = "tx", "rx";
865 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
866 resets = <&cpg 208>;
867 #address-cells = <1>;
868 #size-cells = <0>;
869 status = "disabled";
870 };
872 vin4: video@e6ef4000 {
873 compatible = "renesas,vin-r8a77995";
874 reg = <0 0xe6ef4000 0 0x1000>;
875 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&cpg CPG_MOD 807>;
877 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
878 resets = <&cpg 807>;
879 renesas,id = <4>;
880 status = "disabled";
881 };
883 ohci0: usb@ee080000 {
884 compatible = "generic-ohci";
885 reg = <0 0xee080000 0 0x100>;
886 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
888 phys = <&usb2_phy0 1>;
889 phy-names = "usb";
890 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
891 resets = <&cpg 703>, <&cpg 704>;
892 status = "disabled";
893 };
895 ehci0: usb@ee080100 {
896 compatible = "generic-ehci";
897 reg = <0 0xee080100 0 0x100>;
898 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
900 phys = <&usb2_phy0 2>;
901 phy-names = "usb";
902 companion = <&ohci0>;
903 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
904 resets = <&cpg 703>, <&cpg 704>;
905 status = "disabled";
906 };
908 usb2_phy0: usb-phy@ee080200 {
909 compatible = "renesas,usb2-phy-r8a77995",
910 "renesas,rcar-gen3-usb2-phy";
911 reg = <0 0xee080200 0 0x700>;
912 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
914 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
915 resets = <&cpg 703>, <&cpg 704>;
916 #phy-cells = <1>;
917 status = "disabled";
918 };
920 sdhi2: mmc@ee140000 {
921 compatible = "renesas,sdhi-r8a77995",
922 "renesas,rcar-gen3-sdhi";
923 reg = <0 0xee140000 0 0x2000>;
924 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&cpg CPG_MOD 312>;
926 max-frequency = <200000000>;
927 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
928 resets = <&cpg 312>;
929 iommus = <&ipmmu_ds1 34>;
930 status = "disabled";
931 };
933 gic: interrupt-controller@f1010000 {
934 compatible = "arm,gic-400";
935 #interrupt-cells = <3>;
936 #address-cells = <0>;
937 interrupt-controller;
938 reg = <0x0 0xf1010000 0 0x1000>,
939 <0x0 0xf1020000 0 0x20000>,
940 <0x0 0xf1040000 0 0x20000>,
941 <0x0 0xf1060000 0 0x20000>;
942 interrupts = <GIC_PPI 9
943 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
944 clocks = <&cpg CPG_MOD 408>;
945 clock-names = "clk";
946 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
947 resets = <&cpg 408>;
948 };
950 vspbs: vsp@fe960000 {
951 compatible = "renesas,vsp2";
952 reg = <0 0xfe960000 0 0x8000>;
953 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
954 clocks = <&cpg CPG_MOD 627>;
955 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
956 resets = <&cpg 627>;
957 renesas,fcp = <&fcpvb0>;
958 };
960 vspd0: vsp@fea20000 {
961 compatible = "renesas,vsp2";
962 reg = <0 0xfea20000 0 0x5000>;
963 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
964 clocks = <&cpg CPG_MOD 623>;
965 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
966 resets = <&cpg 623>;
967 renesas,fcp = <&fcpvd0>;
968 };
970 vspd1: vsp@fea28000 {
971 compatible = "renesas,vsp2";
972 reg = <0 0xfea28000 0 0x5000>;
973 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&cpg CPG_MOD 622>;
975 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
976 resets = <&cpg 622>;
977 renesas,fcp = <&fcpvd1>;
978 };
980 fcpvb0: fcp@fe96f000 {
981 compatible = "renesas,fcpv";
982 reg = <0 0xfe96f000 0 0x200>;
983 clocks = <&cpg CPG_MOD 607>;
984 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
985 resets = <&cpg 607>;
986 iommus = <&ipmmu_vp0 5>;
987 };
989 fcpvd0: fcp@fea27000 {
990 compatible = "renesas,fcpv";
991 reg = <0 0xfea27000 0 0x200>;
992 clocks = <&cpg CPG_MOD 603>;
993 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
994 resets = <&cpg 603>;
995 iommus = <&ipmmu_vi0 8>;
996 };
998 fcpvd1: fcp@fea2f000 {
999 compatible = "renesas,fcpv";
1000 reg = <0 0xfea2f000 0 0x200>;
1001 clocks = <&cpg CPG_MOD 602>;
1002 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1003 resets = <&cpg 602>;
1004 iommus = <&ipmmu_vi0 9>;
1005 };
1007 cmm0: cmm@fea40000 {
1008 compatible = "renesas,r8a77995-cmm",
1009 "renesas,rcar-gen3-cmm";
1010 reg = <0 0xfea40000 0 0x1000>;
1011 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1012 clocks = <&cpg CPG_MOD 711>;
1013 resets = <&cpg 711>;
1014 };
1016 cmm1: cmm@fea50000 {
1017 compatible = "renesas,r8a77995-cmm",
1018 "renesas,rcar-gen3-cmm";
1019 reg = <0 0xfea50000 0 0x1000>;
1020 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1021 clocks = <&cpg CPG_MOD 710>;
1022 resets = <&cpg 710>;
1023 };
1025 du: display@feb00000 {
1026 compatible = "renesas,du-r8a77995";
1027 reg = <0 0xfeb00000 0 0x40000>;
1028 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1031 clock-names = "du.0", "du.1";
1032 resets = <&cpg 724>;
1033 reset-names = "du.0";
1035 renesas,cmms = <&cmm0>, <&cmm1>;
1036 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1038 status = "disabled";
1040 ports {
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1044 port@0 {
1045 reg = <0>;
1046 du_out_rgb: endpoint {
1047 };
1048 };
1050 port@1 {
1051 reg = <1>;
1052 du_out_lvds0: endpoint {
1053 remote-endpoint = <&lvds0_in>;
1054 };
1055 };
1057 port@2 {
1058 reg = <2>;
1059 du_out_lvds1: endpoint {
1060 remote-endpoint = <&lvds1_in>;
1061 };
1062 };
1063 };
1064 };
1066 lvds0: lvds-encoder@feb90000 {
1067 compatible = "renesas,r8a77995-lvds";
1068 reg = <0 0xfeb90000 0 0x20>;
1069 clocks = <&cpg CPG_MOD 727>;
1070 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1071 resets = <&cpg 727>;
1072 status = "disabled";
1074 renesas,companion = <&lvds1>;
1076 ports {
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1080 port@0 {
1081 reg = <0>;
1082 lvds0_in: endpoint {
1083 remote-endpoint = <&du_out_lvds0>;
1084 };
1085 };
1087 port@1 {
1088 reg = <1>;
1089 lvds0_out: endpoint {
1090 };
1091 };
1092 };
1093 };
1095 lvds1: lvds-encoder@feb90100 {
1096 compatible = "renesas,r8a77995-lvds";
1097 reg = <0 0xfeb90100 0 0x20>;
1098 clocks = <&cpg CPG_MOD 727>;
1099 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1100 resets = <&cpg 726>;
1101 status = "disabled";
1103 ports {
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1107 port@0 {
1108 reg = <0>;
1109 lvds1_in: endpoint {
1110 remote-endpoint = <&du_out_lvds1>;
1111 };
1112 };
1114 port@1 {
1115 reg = <1>;
1116 lvds1_out: endpoint {
1117 };
1118 };
1119 };
1120 };
1122 prr: chipid@fff00044 {
1123 compatible = "renesas,prr";
1124 reg = <0 0xfff00044 0 4>;
1125 };
1126 };
1128 thermal-zones {
1129 cpu_thermal: cpu-thermal {
1130 polling-delay-passive = <250>;
1131 polling-delay = <1000>;
1132 thermal-sensors = <&thermal>;
1134 cooling-maps {
1135 };
1137 trips {
1138 cpu-crit {
1139 temperature = <120000>;
1140 hysteresis = <2000>;
1141 type = "critical";
1142 };
1143 };
1144 };
1145 };
1147 timer {
1148 compatible = "arm,armv8-timer";
1149 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1150 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1151 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1152 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
1153 };
1154 };