| blob | 2560b98771ca8ff6ed0ab65d5c4323f695bfeb26 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
4 *
5 */
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
15 / {
16 compatible = "rockchip,rk3308";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 serial2 = &uart2;
30 serial3 = &uart3;
31 serial4 = &uart4;
32 spi0 = &spi0;
33 spi1 = &spi1;
34 spi2 = &spi2;
35 };
37 cpus {
38 #address-cells = <2>;
39 #size-cells = <0>;
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a35";
44 reg = <0x0 0x0>;
45 enable-method = "psci";
46 clocks = <&cru ARMCLK>;
47 #cooling-cells = <2>;
48 dynamic-power-coefficient = <90>;
49 operating-points-v2 = <&cpu0_opp_table>;
50 cpu-idle-states = <&CPU_SLEEP>;
51 next-level-cache = <&l2>;
52 };
54 cpu1: cpu@1 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a35";
57 reg = <0x0 0x1>;
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
60 cpu-idle-states = <&CPU_SLEEP>;
61 next-level-cache = <&l2>;
62 };
64 cpu2: cpu@2 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a35";
67 reg = <0x0 0x2>;
68 enable-method = "psci";
69 operating-points-v2 = <&cpu0_opp_table>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 next-level-cache = <&l2>;
72 };
74 cpu3: cpu@3 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a35";
77 reg = <0x0 0x3>;
78 enable-method = "psci";
79 operating-points-v2 = <&cpu0_opp_table>;
80 cpu-idle-states = <&CPU_SLEEP>;
81 next-level-cache = <&l2>;
82 };
84 idle-states {
85 entry-method = "psci";
87 CPU_SLEEP: cpu-sleep {
88 compatible = "arm,idle-state";
89 local-timer-stop;
90 arm,psci-suspend-param = <0x0010000>;
91 entry-latency-us = <120>;
92 exit-latency-us = <250>;
93 min-residency-us = <900>;
94 };
95 };
97 l2: l2-cache {
98 compatible = "cache";
99 };
100 };
102 cpu0_opp_table: cpu0-opp-table {
103 compatible = "operating-points-v2";
104 opp-shared;
106 opp-408000000 {
107 opp-hz = /bits/ 64 <408000000>;
108 opp-microvolt = <950000 950000 1340000>;
109 clock-latency-ns = <40000>;
110 opp-suspend;
111 };
112 opp-600000000 {
113 opp-hz = /bits/ 64 <600000000>;
114 opp-microvolt = <950000 950000 1340000>;
115 clock-latency-ns = <40000>;
116 };
117 opp-816000000 {
118 opp-hz = /bits/ 64 <816000000>;
119 opp-microvolt = <1025000 1025000 1340000>;
120 clock-latency-ns = <40000>;
121 };
122 opp-1008000000 {
123 opp-hz = /bits/ 64 <1008000000>;
124 opp-microvolt = <1125000 1125000 1340000>;
125 clock-latency-ns = <40000>;
126 };
127 };
129 arm-pmu {
130 compatible = "arm,cortex-a35-pmu";
131 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
136 };
138 mac_clkin: external-mac-clock {
139 compatible = "fixed-clock";
140 clock-frequency = <50000000>;
141 clock-output-names = "mac_clkin";
142 #clock-cells = <0>;
143 };
145 psci {
146 compatible = "arm,psci-1.0";
147 method = "smc";
148 };
150 timer {
151 compatible = "arm,armv8-timer";
152 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
153 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
154 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
155 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
156 };
158 xin24m: xin24m {
159 compatible = "fixed-clock";
160 #clock-cells = <0>;
161 clock-frequency = <24000000>;
162 clock-output-names = "xin24m";
163 };
165 grf: grf@ff000000 {
166 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
167 reg = <0x0 0xff000000 0x0 0x10000>;
169 reboot-mode {
170 compatible = "syscon-reboot-mode";
171 offset = <0x500>;
172 mode-bootloader = <BOOT_BL_DOWNLOAD>;
173 mode-loader = <BOOT_BL_DOWNLOAD>;
174 mode-normal = <BOOT_NORMAL>;
175 mode-recovery = <BOOT_RECOVERY>;
176 mode-fastboot = <BOOT_FASTBOOT>;
177 };
178 };
180 detect_grf: syscon@ff00b000 {
181 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
182 reg = <0x0 0xff00b000 0x0 0x1000>;
183 #address-cells = <1>;
184 #size-cells = <1>;
185 };
187 core_grf: syscon@ff00c000 {
188 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
189 reg = <0x0 0xff00c000 0x0 0x1000>;
190 #address-cells = <1>;
191 #size-cells = <1>;
192 };
194 i2c0: i2c@ff040000 {
195 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
196 reg = <0x0 0xff040000 0x0 0x1000>;
197 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
198 clock-names = "i2c", "pclk";
199 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&i2c0_xfer>;
202 #address-cells = <1>;
203 #size-cells = <0>;
204 status = "disabled";
205 };
207 i2c1: i2c@ff050000 {
208 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
209 reg = <0x0 0xff050000 0x0 0x1000>;
210 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
211 clock-names = "i2c", "pclk";
212 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&i2c1_xfer>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 status = "disabled";
218 };
220 i2c2: i2c@ff060000 {
221 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
222 reg = <0x0 0xff060000 0x0 0x1000>;
223 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
224 clock-names = "i2c", "pclk";
225 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&i2c2_xfer>;
228 #address-cells = <1>;
229 #size-cells = <0>;
230 status = "disabled";
231 };
233 i2c3: i2c@ff070000 {
234 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
235 reg = <0x0 0xff070000 0x0 0x1000>;
236 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
237 clock-names = "i2c", "pclk";
238 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&i2c3m0_xfer>;
241 #address-cells = <1>;
242 #size-cells = <0>;
243 status = "disabled";
244 };
246 wdt: watchdog@ff080000 {
247 compatible = "snps,dw-wdt";
248 reg = <0x0 0xff080000 0x0 0x100>;
249 clocks = <&cru PCLK_WDT>;
250 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
251 status = "disabled";
252 };
254 uart0: serial@ff0a0000 {
255 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
256 reg = <0x0 0xff0a0000 0x0 0x100>;
257 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
259 clock-names = "baudclk", "apb_pclk";
260 reg-shift = <2>;
261 reg-io-width = <4>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
264 status = "disabled";
265 };
267 uart1: serial@ff0b0000 {
268 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
269 reg = <0x0 0xff0b0000 0x0 0x100>;
270 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
272 clock-names = "baudclk", "apb_pclk";
273 reg-shift = <2>;
274 reg-io-width = <4>;
275 pinctrl-names = "default";
276 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
277 status = "disabled";
278 };
280 uart2: serial@ff0c0000 {
281 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
282 reg = <0x0 0xff0c0000 0x0 0x100>;
283 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
285 clock-names = "baudclk", "apb_pclk";
286 reg-shift = <2>;
287 reg-io-width = <4>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&uart2m0_xfer>;
290 status = "disabled";
291 };
293 uart3: serial@ff0d0000 {
294 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
295 reg = <0x0 0xff0d0000 0x0 0x100>;
296 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
298 clock-names = "baudclk", "apb_pclk";
299 reg-shift = <2>;
300 reg-io-width = <4>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&uart3_xfer>;
303 status = "disabled";
304 };
306 uart4: serial@ff0e0000 {
307 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
308 reg = <0x0 0xff0e0000 0x0 0x100>;
309 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
311 clock-names = "baudclk", "apb_pclk";
312 reg-shift = <2>;
313 reg-io-width = <4>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
316 status = "disabled";
317 };
319 spi0: spi@ff120000 {
320 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
321 reg = <0x0 0xff120000 0x0 0x1000>;
322 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
323 #address-cells = <1>;
324 #size-cells = <0>;
325 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
326 clock-names = "spiclk", "apb_pclk";
327 dmas = <&dmac0 0>, <&dmac0 1>;
328 dma-names = "tx", "rx";
329 pinctrl-names = "default";
330 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
331 status = "disabled";
332 };
334 spi1: spi@ff130000 {
335 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
336 reg = <0x0 0xff130000 0x0 0x1000>;
337 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
339 #size-cells = <0>;
340 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
341 clock-names = "spiclk", "apb_pclk";
342 dmas = <&dmac0 2>, <&dmac0 3>;
343 dma-names = "tx", "rx";
344 pinctrl-names = "default";
345 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
346 status = "disabled";
347 };
349 spi2: spi@ff140000 {
350 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
351 reg = <0x0 0xff140000 0x0 0x1000>;
352 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
354 #size-cells = <0>;
355 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
356 clock-names = "spiclk", "apb_pclk";
357 dmas = <&dmac1 16>, <&dmac1 17>;
358 dma-names = "tx", "rx";
359 pinctrl-names = "default";
360 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
361 status = "disabled";
362 };
364 pwm8: pwm@ff160000 {
365 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
366 reg = <0x0 0xff160000 0x0 0x10>;
367 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
368 clock-names = "pwm", "pclk";
369 pinctrl-names = "default";
370 pinctrl-0 = <&pwm8_pin>;
371 #pwm-cells = <3>;
372 status = "disabled";
373 };
375 pwm9: pwm@ff160010 {
376 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
377 reg = <0x0 0xff160010 0x0 0x10>;
378 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
379 clock-names = "pwm", "pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&pwm9_pin>;
382 #pwm-cells = <3>;
383 status = "disabled";
384 };
386 pwm10: pwm@ff160020 {
387 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
388 reg = <0x0 0xff160020 0x0 0x10>;
389 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
390 clock-names = "pwm", "pclk";
391 pinctrl-names = "default";
392 pinctrl-0 = <&pwm10_pin>;
393 #pwm-cells = <3>;
394 status = "disabled";
395 };
397 pwm11: pwm@ff160030 {
398 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
399 reg = <0x0 0xff160030 0x0 0x10>;
400 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
401 clock-names = "pwm", "pclk";
402 pinctrl-names = "default";
403 pinctrl-0 = <&pwm11_pin>;
404 #pwm-cells = <3>;
405 status = "disabled";
406 };
408 pwm4: pwm@ff170000 {
409 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
410 reg = <0x0 0xff170000 0x0 0x10>;
411 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
412 clock-names = "pwm", "pclk";
413 pinctrl-names = "default";
414 pinctrl-0 = <&pwm4_pin>;
415 #pwm-cells = <3>;
416 status = "disabled";
417 };
419 pwm5: pwm@ff170010 {
420 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
421 reg = <0x0 0xff170010 0x0 0x10>;
422 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
423 clock-names = "pwm", "pclk";
424 pinctrl-names = "default";
425 pinctrl-0 = <&pwm5_pin>;
426 #pwm-cells = <3>;
427 status = "disabled";
428 };
430 pwm6: pwm@ff170020 {
431 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
432 reg = <0x0 0xff170020 0x0 0x10>;
433 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
434 clock-names = "pwm", "pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&pwm6_pin>;
437 #pwm-cells = <3>;
438 status = "disabled";
439 };
441 pwm7: pwm@ff170030 {
442 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
443 reg = <0x0 0xff170030 0x0 0x10>;
444 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
445 clock-names = "pwm", "pclk";
446 pinctrl-names = "default";
447 pinctrl-0 = <&pwm7_pin>;
448 #pwm-cells = <3>;
449 status = "disabled";
450 };
452 pwm0: pwm@ff180000 {
453 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
454 reg = <0x0 0xff180000 0x0 0x10>;
455 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
456 clock-names = "pwm", "pclk";
457 pinctrl-names = "default";
458 pinctrl-0 = <&pwm0_pin>;
459 #pwm-cells = <3>;
460 status = "disabled";
461 };
463 pwm1: pwm@ff180010 {
464 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
465 reg = <0x0 0xff180010 0x0 0x10>;
466 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
467 clock-names = "pwm", "pclk";
468 pinctrl-names = "default";
469 pinctrl-0 = <&pwm1_pin>;
470 #pwm-cells = <3>;
471 status = "disabled";
472 };
474 pwm2: pwm@ff180020 {
475 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
476 reg = <0x0 0xff180020 0x0 0x10>;
477 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
478 clock-names = "pwm", "pclk";
479 pinctrl-names = "default";
480 pinctrl-0 = <&pwm2_pin>;
481 #pwm-cells = <3>;
482 status = "disabled";
483 };
485 pwm3: pwm@ff180030 {
486 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
487 reg = <0x0 0xff180030 0x0 0x10>;
488 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
489 clock-names = "pwm", "pclk";
490 pinctrl-names = "default";
491 pinctrl-0 = <&pwm3_pin>;
492 #pwm-cells = <3>;
493 status = "disabled";
494 };
496 rktimer: rktimer@ff1a0000 {
497 compatible = "rockchip,rk3288-timer";
498 reg = <0x0 0xff1a0000 0x0 0x20>;
499 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
501 clock-names = "pclk", "timer";
502 };
504 saradc: saradc@ff1e0000 {
505 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
506 reg = <0x0 0xff1e0000 0x0 0x100>;
507 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
509 clock-names = "saradc", "apb_pclk";
510 #io-channel-cells = <1>;
511 resets = <&cru SRST_SARADC_P>;
512 reset-names = "saradc-apb";
513 status = "disabled";
514 };
516 amba: bus {
517 compatible = "simple-bus";
518 #address-cells = <2>;
519 #size-cells = <2>;
520 ranges;
522 dmac0: dma-controller@ff2c0000 {
523 compatible = "arm,pl330", "arm,primecell";
524 reg = <0x0 0xff2c0000 0x0 0x4000>;
525 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
527 arm,pl330-periph-burst;
528 clocks = <&cru ACLK_DMAC0>;
529 clock-names = "apb_pclk";
530 #dma-cells = <1>;
531 };
533 dmac1: dma-controller@ff2d0000 {
534 compatible = "arm,pl330", "arm,primecell";
535 reg = <0x0 0xff2d0000 0x0 0x4000>;
536 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
538 arm,pl330-periph-burst;
539 clocks = <&cru ACLK_DMAC1>;
540 clock-names = "apb_pclk";
541 #dma-cells = <1>;
542 };
543 };
545 i2s_2ch_0: i2s@ff350000 {
546 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
547 reg = <0x0 0xff350000 0x0 0x1000>;
548 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
550 clock-names = "i2s_clk", "i2s_hclk";
551 dmas = <&dmac1 8>, <&dmac1 9>;
552 dma-names = "tx", "rx";
553 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
554 reset-names = "reset-m", "reset-h";
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2s_2ch_0_sclk
557 &i2s_2ch_0_lrck
558 &i2s_2ch_0_sdi
559 &i2s_2ch_0_sdo>;
560 status = "disabled";
561 };
563 i2s_2ch_1: i2s@ff360000 {
564 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
565 reg = <0x0 0xff360000 0x0 0x1000>;
566 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
568 clock-names = "i2s_clk", "i2s_hclk";
569 dmas = <&dmac1 11>;
570 dma-names = "rx";
571 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
572 reset-names = "reset-m", "reset-h";
573 status = "disabled";
574 };
576 spdif_tx: spdif-tx@ff3a0000 {
577 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
578 reg = <0x0 0xff3a0000 0x0 0x1000>;
579 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
581 clock-names = "mclk", "hclk";
582 dmas = <&dmac1 13>;
583 dma-names = "tx";
584 pinctrl-names = "default";
585 pinctrl-0 = <&spdif_out>;
586 status = "disabled";
587 };
589 sdmmc: mmc@ff480000 {
590 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
591 reg = <0x0 0xff480000 0x0 0x4000>;
592 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
593 bus-width = <4>;
594 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
595 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
596 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
597 fifo-depth = <0x100>;
598 max-frequency = <150000000>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
601 status = "disabled";
602 };
604 emmc: mmc@ff490000 {
605 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
606 reg = <0x0 0xff490000 0x0 0x4000>;
607 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
608 bus-width = <8>;
609 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
610 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
611 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
612 fifo-depth = <0x100>;
613 max-frequency = <150000000>;
614 status = "disabled";
615 };
617 sdio: mmc@ff4a0000 {
618 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
619 reg = <0x0 0xff4a0000 0x0 0x4000>;
620 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
621 bus-width = <4>;
622 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
623 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
624 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
625 fifo-depth = <0x100>;
626 max-frequency = <150000000>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
629 status = "disabled";
630 };
632 cru: clock-controller@ff500000 {
633 compatible = "rockchip,rk3308-cru";
634 reg = <0x0 0xff500000 0x0 0x1000>;
635 #clock-cells = <1>;
636 #reset-cells = <1>;
637 rockchip,grf = <&grf>;
639 assigned-clocks = <&cru SCLK_RTC32K>;
640 assigned-clock-rates = <32768>;
641 };
643 gic: interrupt-controller@ff580000 {
644 compatible = "arm,gic-400";
645 reg = <0x0 0xff581000 0x0 0x1000>,
646 <0x0 0xff582000 0x0 0x2000>,
647 <0x0 0xff584000 0x0 0x2000>,
648 <0x0 0xff586000 0x0 0x2000>;
649 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
650 #interrupt-cells = <3>;
651 interrupt-controller;
652 #address-cells = <0>;
653 };
655 sram: sram@fff80000 {
656 compatible = "mmio-sram";
657 reg = <0x0 0xfff80000 0x0 0x40000>;
658 ranges = <0 0x0 0xfff80000 0x40000>;
659 #address-cells = <1>;
660 #size-cells = <1>;
662 /* reserved for ddr dvfs and system suspend/resume */
663 ddr-sram@0 {
664 reg = <0x0 0x8000>;
665 };
667 /* reserved for vad audio buffer */
668 vad_sram: vad-sram@8000 {
669 reg = <0x8000 0x38000>;
670 };
671 };
673 pinctrl: pinctrl {
674 compatible = "rockchip,rk3308-pinctrl";
675 rockchip,grf = <&grf>;
676 #address-cells = <2>;
677 #size-cells = <2>;
678 ranges;
680 gpio0: gpio0@ff220000 {
681 compatible = "rockchip,gpio-bank";
682 reg = <0x0 0xff220000 0x0 0x100>;
683 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&cru PCLK_GPIO0>;
685 gpio-controller;
686 #gpio-cells = <2>;
687 interrupt-controller;
688 #interrupt-cells = <2>;
689 };
691 gpio1: gpio1@ff230000 {
692 compatible = "rockchip,gpio-bank";
693 reg = <0x0 0xff230000 0x0 0x100>;
694 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&cru PCLK_GPIO1>;
696 gpio-controller;
697 #gpio-cells = <2>;
698 interrupt-controller;
699 #interrupt-cells = <2>;
700 };
702 gpio2: gpio2@ff240000 {
703 compatible = "rockchip,gpio-bank";
704 reg = <0x0 0xff240000 0x0 0x100>;
705 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cru PCLK_GPIO2>;
707 gpio-controller;
708 #gpio-cells = <2>;
709 interrupt-controller;
710 #interrupt-cells = <2>;
711 };
713 gpio3: gpio3@ff250000 {
714 compatible = "rockchip,gpio-bank";
715 reg = <0x0 0xff250000 0x0 0x100>;
716 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&cru PCLK_GPIO3>;
718 gpio-controller;
719 #gpio-cells = <2>;
720 interrupt-controller;
721 #interrupt-cells = <2>;
722 };
724 gpio4: gpio4@ff260000 {
725 compatible = "rockchip,gpio-bank";
726 reg = <0x0 0xff260000 0x0 0x100>;
727 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&cru PCLK_GPIO4>;
729 gpio-controller;
730 #gpio-cells = <2>;
731 interrupt-controller;
732 #interrupt-cells = <2>;
733 };
735 pcfg_pull_up: pcfg-pull-up {
736 bias-pull-up;
737 };
739 pcfg_pull_down: pcfg-pull-down {
740 bias-pull-down;
741 };
743 pcfg_pull_none: pcfg-pull-none {
744 bias-disable;
745 };
747 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
748 bias-disable;
749 drive-strength = <2>;
750 };
752 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
753 bias-pull-up;
754 drive-strength = <2>;
755 };
757 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
758 bias-pull-up;
759 drive-strength = <4>;
760 };
762 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
763 bias-disable;
764 drive-strength = <4>;
765 };
767 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
768 bias-pull-down;
769 drive-strength = <4>;
770 };
772 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
773 bias-disable;
774 drive-strength = <8>;
775 };
777 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
778 bias-pull-up;
779 drive-strength = <8>;
780 };
782 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
783 bias-disable;
784 drive-strength = <12>;
785 };
787 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
788 bias-pull-up;
789 drive-strength = <12>;
790 };
792 pcfg_pull_none_smt: pcfg-pull-none-smt {
793 bias-disable;
794 input-schmitt-enable;
795 };
797 pcfg_output_high: pcfg-output-high {
798 output-high;
799 };
801 pcfg_output_low: pcfg-output-low {
802 output-low;
803 };
805 pcfg_input_high: pcfg-input-high {
806 bias-pull-up;
807 input-enable;
808 };
810 pcfg_input: pcfg-input {
811 input-enable;
812 };
814 emmc {
815 emmc_clk: emmc-clk {
816 rockchip,pins =
817 <3 RK_PB1 2 &pcfg_pull_none_8ma>;
818 };
820 emmc_cmd: emmc-cmd {
821 rockchip,pins =
822 <3 RK_PB0 2 &pcfg_pull_up_8ma>;
823 };
825 emmc_pwren: emmc-pwren {
826 rockchip,pins =
827 <3 RK_PB3 2 &pcfg_pull_none>;
828 };
830 emmc_rstn: emmc-rstn {
831 rockchip,pins =
832 <3 RK_PB2 2 &pcfg_pull_none>;
833 };
835 emmc_bus1: emmc-bus1 {
836 rockchip,pins =
837 <3 RK_PA0 2 &pcfg_pull_up_8ma>;
838 };
840 emmc_bus4: emmc-bus4 {
841 rockchip,pins =
842 <3 RK_PA0 2 &pcfg_pull_up_8ma>,
843 <3 RK_PA1 2 &pcfg_pull_up_8ma>,
844 <3 RK_PA2 2 &pcfg_pull_up_8ma>,
845 <3 RK_PA3 2 &pcfg_pull_up_8ma>;
846 };
848 emmc_bus8: emmc-bus8 {
849 rockchip,pins =
850 <3 RK_PA0 2 &pcfg_pull_up_8ma>,
851 <3 RK_PA1 2 &pcfg_pull_up_8ma>,
852 <3 RK_PA2 2 &pcfg_pull_up_8ma>,
853 <3 RK_PA3 2 &pcfg_pull_up_8ma>,
854 <3 RK_PA4 2 &pcfg_pull_up_8ma>,
855 <3 RK_PA5 2 &pcfg_pull_up_8ma>,
856 <3 RK_PA6 2 &pcfg_pull_up_8ma>,
857 <3 RK_PA7 2 &pcfg_pull_up_8ma>;
858 };
859 };
861 flash {
862 flash_csn0: flash-csn0 {
863 rockchip,pins =
864 <3 RK_PB5 1 &pcfg_pull_none>;
865 };
867 flash_rdy: flash-rdy {
868 rockchip,pins =
869 <3 RK_PB4 1 &pcfg_pull_none>;
870 };
872 flash_ale: flash-ale {
873 rockchip,pins =
874 <3 RK_PB3 1 &pcfg_pull_none>;
875 };
877 flash_cle: flash-cle {
878 rockchip,pins =
879 <3 RK_PB1 1 &pcfg_pull_none>;
880 };
882 flash_wrn: flash-wrn {
883 rockchip,pins =
884 <3 RK_PB0 1 &pcfg_pull_none>;
885 };
887 flash_rdn: flash-rdn {
888 rockchip,pins =
889 <3 RK_PB2 1 &pcfg_pull_none>;
890 };
892 flash_bus8: flash-bus8 {
893 rockchip,pins =
894 <3 RK_PA0 1 &pcfg_pull_up_12ma>,
895 <3 RK_PA1 1 &pcfg_pull_up_12ma>,
896 <3 RK_PA2 1 &pcfg_pull_up_12ma>,
897 <3 RK_PA3 1 &pcfg_pull_up_12ma>,
898 <3 RK_PA4 1 &pcfg_pull_up_12ma>,
899 <3 RK_PA5 1 &pcfg_pull_up_12ma>,
900 <3 RK_PA6 1 &pcfg_pull_up_12ma>,
901 <3 RK_PA7 1 &pcfg_pull_up_12ma>;
902 };
903 };
905 gmac {
906 rmii_pins: rmii-pins {
907 rockchip,pins =
908 /* mac_txen */
909 <1 RK_PC1 3 &pcfg_pull_none_12ma>,
910 /* mac_txd1 */
911 <1 RK_PC3 3 &pcfg_pull_none_12ma>,
912 /* mac_txd0 */
913 <1 RK_PC2 3 &pcfg_pull_none_12ma>,
914 /* mac_rxd0 */
915 <1 RK_PC4 3 &pcfg_pull_none>,
916 /* mac_rxd1 */
917 <1 RK_PC5 3 &pcfg_pull_none>,
918 /* mac_rxer */
919 <1 RK_PB7 3 &pcfg_pull_none>,
920 /* mac_rxdv */
921 <1 RK_PC0 3 &pcfg_pull_none>,
922 /* mac_mdio */
923 <1 RK_PB6 3 &pcfg_pull_none>,
924 /* mac_mdc */
925 <1 RK_PB5 3 &pcfg_pull_none>;
926 };
928 mac_refclk_12ma: mac-refclk-12ma {
929 rockchip,pins =
930 <1 RK_PB4 3 &pcfg_pull_none_12ma>;
931 };
933 mac_refclk: mac-refclk {
934 rockchip,pins =
935 <1 RK_PB4 3 &pcfg_pull_none>;
936 };
937 };
939 gmac-m1 {
940 rmiim1_pins: rmiim1-pins {
941 rockchip,pins =
942 /* mac_txen */
943 <4 RK_PB7 2 &pcfg_pull_none_12ma>,
944 /* mac_txd1 */
945 <4 RK_PA5 2 &pcfg_pull_none_12ma>,
946 /* mac_txd0 */
947 <4 RK_PA4 2 &pcfg_pull_none_12ma>,
948 /* mac_rxd0 */
949 <4 RK_PA2 2 &pcfg_pull_none>,
950 /* mac_rxd1 */
951 <4 RK_PA3 2 &pcfg_pull_none>,
952 /* mac_rxer */
953 <4 RK_PA0 2 &pcfg_pull_none>,
954 /* mac_rxdv */
955 <4 RK_PA1 2 &pcfg_pull_none>,
956 /* mac_mdio */
957 <4 RK_PB6 2 &pcfg_pull_none>,
958 /* mac_mdc */
959 <4 RK_PB5 2 &pcfg_pull_none>;
960 };
962 macm1_refclk_12ma: macm1-refclk-12ma {
963 rockchip,pins =
964 <4 RK_PB4 2 &pcfg_pull_none_12ma>;
965 };
967 macm1_refclk: macm1-refclk {
968 rockchip,pins =
969 <4 RK_PB4 2 &pcfg_pull_none>;
970 };
971 };
973 i2c0 {
974 i2c0_xfer: i2c0-xfer {
975 rockchip,pins =
976 <1 RK_PD0 2 &pcfg_pull_none_smt>,
977 <1 RK_PD1 2 &pcfg_pull_none_smt>;
978 };
979 };
981 i2c1 {
982 i2c1_xfer: i2c1-xfer {
983 rockchip,pins =
984 <0 RK_PB3 1 &pcfg_pull_none_smt>,
985 <0 RK_PB4 1 &pcfg_pull_none_smt>;
986 };
987 };
989 i2c2 {
990 i2c2_xfer: i2c2-xfer {
991 rockchip,pins =
992 <2 RK_PA2 3 &pcfg_pull_none_smt>,
993 <2 RK_PA3 3 &pcfg_pull_none_smt>;
994 };
995 };
997 i2c3-m0 {
998 i2c3m0_xfer: i2c3m0-xfer {
999 rockchip,pins =
1000 <0 RK_PB7 2 &pcfg_pull_none_smt>,
1001 <0 RK_PC0 2 &pcfg_pull_none_smt>;
1002 };
1003 };
1005 i2c3-m1 {
1006 i2c3m1_xfer: i2c3m1-xfer {
1007 rockchip,pins =
1008 <3 RK_PB4 2 &pcfg_pull_none_smt>,
1009 <3 RK_PB5 2 &pcfg_pull_none_smt>;
1010 };
1011 };
1013 i2c3-m2 {
1014 i2c3m2_xfer: i2c3m2-xfer {
1015 rockchip,pins =
1016 <2 RK_PA1 3 &pcfg_pull_none_smt>,
1017 <2 RK_PA0 3 &pcfg_pull_none_smt>;
1018 };
1019 };
1021 i2s_2ch_0 {
1022 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1023 rockchip,pins =
1024 <4 RK_PB4 1 &pcfg_pull_none>;
1025 };
1027 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1028 rockchip,pins =
1029 <4 RK_PB5 1 &pcfg_pull_none>;
1030 };
1032 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1033 rockchip,pins =
1034 <4 RK_PB6 1 &pcfg_pull_none>;
1035 };
1037 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1038 rockchip,pins =
1039 <4 RK_PB7 1 &pcfg_pull_none>;
1040 };
1042 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1043 rockchip,pins =
1044 <4 RK_PC0 1 &pcfg_pull_none>;
1045 };
1046 };
1048 i2s_8ch_0 {
1049 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1050 rockchip,pins =
1051 <2 RK_PA4 1 &pcfg_pull_none>;
1052 };
1054 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1055 rockchip,pins =
1056 <2 RK_PA5 1 &pcfg_pull_none>;
1057 };
1059 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1060 rockchip,pins =
1061 <2 RK_PA6 1 &pcfg_pull_none>;
1062 };
1064 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1065 rockchip,pins =
1066 <2 RK_PA7 1 &pcfg_pull_none>;
1067 };
1069 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1070 rockchip,pins =
1071 <2 RK_PB0 1 &pcfg_pull_none>;
1072 };
1074 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1075 rockchip,pins =
1076 <2 RK_PB1 1 &pcfg_pull_none>;
1077 };
1079 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1080 rockchip,pins =
1081 <2 RK_PB2 1 &pcfg_pull_none>;
1082 };
1084 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1085 rockchip,pins =
1086 <2 RK_PB3 1 &pcfg_pull_none>;
1087 };
1089 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1090 rockchip,pins =
1091 <2 RK_PB4 1 &pcfg_pull_none>;
1092 };
1094 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1095 rockchip,pins =
1096 <2 RK_PB5 1 &pcfg_pull_none>;
1097 };
1099 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1100 rockchip,pins =
1101 <2 RK_PB6 1 &pcfg_pull_none>;
1102 };
1104 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1105 rockchip,pins =
1106 <2 RK_PB7 1 &pcfg_pull_none>;
1107 };
1109 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1110 rockchip,pins =
1111 <2 RK_PC0 1 &pcfg_pull_none>;
1112 };
1113 };
1115 i2s_8ch_1_m0 {
1116 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1117 rockchip,pins =
1118 <1 RK_PA2 2 &pcfg_pull_none>;
1119 };
1121 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1122 rockchip,pins =
1123 <1 RK_PA3 2 &pcfg_pull_none>;
1124 };
1126 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1127 rockchip,pins =
1128 <1 RK_PA4 2 &pcfg_pull_none>;
1129 };
1131 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1132 rockchip,pins =
1133 <1 RK_PA5 2 &pcfg_pull_none>;
1134 };
1136 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1137 rockchip,pins =
1138 <1 RK_PA6 2 &pcfg_pull_none>;
1139 };
1141 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1142 rockchip,pins =
1143 <1 RK_PA7 2 &pcfg_pull_none>;
1144 };
1146 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1147 rockchip,pins =
1148 <1 RK_PB0 2 &pcfg_pull_none>;
1149 };
1151 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1152 rockchip,pins =
1153 <1 RK_PB1 2 &pcfg_pull_none>;
1154 };
1156 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1157 rockchip,pins =
1158 <1 RK_PB2 2 &pcfg_pull_none>;
1159 };
1161 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1162 rockchip,pins =
1163 <1 RK_PB3 2 &pcfg_pull_none>;
1164 };
1165 };
1167 i2s_8ch_1_m1 {
1168 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1169 rockchip,pins =
1170 <1 RK_PB4 2 &pcfg_pull_none>;
1171 };
1173 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1174 rockchip,pins =
1175 <1 RK_PB5 2 &pcfg_pull_none>;
1176 };
1178 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1179 rockchip,pins =
1180 <1 RK_PB6 2 &pcfg_pull_none>;
1181 };
1183 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1184 rockchip,pins =
1185 <1 RK_PB7 2 &pcfg_pull_none>;
1186 };
1188 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1189 rockchip,pins =
1190 <1 RK_PC0 2 &pcfg_pull_none>;
1191 };
1193 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1194 rockchip,pins =
1195 <1 RK_PC1 2 &pcfg_pull_none>;
1196 };
1198 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1199 rockchip,pins =
1200 <1 RK_PC2 2 &pcfg_pull_none>;
1201 };
1203 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1204 rockchip,pins =
1205 <1 RK_PC3 2 &pcfg_pull_none>;
1206 };
1208 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1209 rockchip,pins =
1210 <1 RK_PC4 2 &pcfg_pull_none>;
1211 };
1213 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1214 rockchip,pins =
1215 <1 RK_PC5 2 &pcfg_pull_none>;
1216 };
1217 };
1219 pdm_m0 {
1220 pdm_m0_clk: pdm-m0-clk {
1221 rockchip,pins =
1222 <1 RK_PA4 3 &pcfg_pull_none>;
1223 };
1225 pdm_m0_sdi0: pdm-m0-sdi0 {
1226 rockchip,pins =
1227 <1 RK_PB3 3 &pcfg_pull_none>;
1228 };
1230 pdm_m0_sdi1: pdm-m0-sdi1 {
1231 rockchip,pins =
1232 <1 RK_PB2 3 &pcfg_pull_none>;
1233 };
1235 pdm_m0_sdi2: pdm-m0-sdi2 {
1236 rockchip,pins =
1237 <1 RK_PB1 3 &pcfg_pull_none>;
1238 };
1240 pdm_m0_sdi3: pdm-m0-sdi3 {
1241 rockchip,pins =
1242 <1 RK_PB0 3 &pcfg_pull_none>;
1243 };
1244 };
1246 pdm_m1 {
1247 pdm_m1_clk: pdm-m1-clk {
1248 rockchip,pins =
1249 <1 RK_PB6 4 &pcfg_pull_none>;
1250 };
1252 pdm_m1_sdi0: pdm-m1-sdi0 {
1253 rockchip,pins =
1254 <1 RK_PC5 4 &pcfg_pull_none>;
1255 };
1257 pdm_m1_sdi1: pdm-m1-sdi1 {
1258 rockchip,pins =
1259 <1 RK_PC4 4 &pcfg_pull_none>;
1260 };
1262 pdm_m1_sdi2: pdm-m1-sdi2 {
1263 rockchip,pins =
1264 <1 RK_PC3 4 &pcfg_pull_none>;
1265 };
1267 pdm_m1_sdi3: pdm-m1-sdi3 {
1268 rockchip,pins =
1269 <1 RK_PC2 4 &pcfg_pull_none>;
1270 };
1271 };
1273 pdm_m2 {
1274 pdm_m2_clkm: pdm-m2-clkm {
1275 rockchip,pins =
1276 <2 RK_PA4 3 &pcfg_pull_none>;
1277 };
1279 pdm_m2_clk: pdm-m2-clk {
1280 rockchip,pins =
1281 <2 RK_PA6 2 &pcfg_pull_none>;
1282 };
1284 pdm_m2_sdi0: pdm-m2-sdi0 {
1285 rockchip,pins =
1286 <2 RK_PB5 2 &pcfg_pull_none>;
1287 };
1289 pdm_m2_sdi1: pdm-m2-sdi1 {
1290 rockchip,pins =
1291 <2 RK_PB6 2 &pcfg_pull_none>;
1292 };
1294 pdm_m2_sdi2: pdm-m2-sdi2 {
1295 rockchip,pins =
1296 <2 RK_PB7 2 &pcfg_pull_none>;
1297 };
1299 pdm_m2_sdi3: pdm-m2-sdi3 {
1300 rockchip,pins =
1301 <2 RK_PC0 2 &pcfg_pull_none>;
1302 };
1303 };
1305 pwm0 {
1306 pwm0_pin: pwm0-pin {
1307 rockchip,pins =
1308 <0 RK_PB5 1 &pcfg_pull_none>;
1309 };
1311 pwm0_pin_pull_down: pwm0-pin-pull-down {
1312 rockchip,pins =
1313 <0 RK_PB5 1 &pcfg_pull_down>;
1314 };
1315 };
1317 pwm1 {
1318 pwm1_pin: pwm1-pin {
1319 rockchip,pins =
1320 <0 RK_PB6 1 &pcfg_pull_none>;
1321 };
1323 pwm1_pin_pull_down: pwm1-pin-pull-down {
1324 rockchip,pins =
1325 <0 RK_PB6 1 &pcfg_pull_down>;
1326 };
1327 };
1329 pwm2 {
1330 pwm2_pin: pwm2-pin {
1331 rockchip,pins =
1332 <0 RK_PB7 1 &pcfg_pull_none>;
1333 };
1335 pwm2_pin_pull_down: pwm2-pin-pull-down {
1336 rockchip,pins =
1337 <0 RK_PB7 1 &pcfg_pull_down>;
1338 };
1339 };
1341 pwm3 {
1342 pwm3_pin: pwm3-pin {
1343 rockchip,pins =
1344 <0 RK_PC0 1 &pcfg_pull_none>;
1345 };
1347 pwm3_pin_pull_down: pwm3-pin-pull-down {
1348 rockchip,pins =
1349 <0 RK_PC0 1 &pcfg_pull_down>;
1350 };
1351 };
1353 pwm4 {
1354 pwm4_pin: pwm4-pin {
1355 rockchip,pins =
1356 <0 RK_PA1 2 &pcfg_pull_none>;
1357 };
1359 pwm4_pin_pull_down: pwm4-pin-pull-down {
1360 rockchip,pins =
1361 <0 RK_PA1 2 &pcfg_pull_down>;
1362 };
1363 };
1365 pwm5 {
1366 pwm5_pin: pwm5-pin {
1367 rockchip,pins =
1368 <0 RK_PC1 2 &pcfg_pull_none>;
1369 };
1371 pwm5_pin_pull_down: pwm5-pin-pull-down {
1372 rockchip,pins =
1373 <0 RK_PC1 2 &pcfg_pull_down>;
1374 };
1375 };
1377 pwm6 {
1378 pwm6_pin: pwm6-pin {
1379 rockchip,pins =
1380 <0 RK_PC2 2 &pcfg_pull_none>;
1381 };
1383 pwm6_pin_pull_down: pwm6-pin-pull-down {
1384 rockchip,pins =
1385 <0 RK_PC2 2 &pcfg_pull_down>;
1386 };
1387 };
1389 pwm7 {
1390 pwm7_pin: pwm7-pin {
1391 rockchip,pins =
1392 <2 RK_PB0 2 &pcfg_pull_none>;
1393 };
1395 pwm7_pin_pull_down: pwm7-pin-pull-down {
1396 rockchip,pins =
1397 <2 RK_PB0 2 &pcfg_pull_down>;
1398 };
1399 };
1401 pwm8 {
1402 pwm8_pin: pwm8-pin {
1403 rockchip,pins =
1404 <2 RK_PB2 2 &pcfg_pull_none>;
1405 };
1407 pwm8_pin_pull_down: pwm8-pin-pull-down {
1408 rockchip,pins =
1409 <2 RK_PB2 2 &pcfg_pull_down>;
1410 };
1411 };
1413 pwm9 {
1414 pwm9_pin: pwm9-pin {
1415 rockchip,pins =
1416 <2 RK_PB3 2 &pcfg_pull_none>;
1417 };
1419 pwm9_pin_pull_down: pwm9-pin-pull-down {
1420 rockchip,pins =
1421 <2 RK_PB3 2 &pcfg_pull_down>;
1422 };
1423 };
1425 pwm10 {
1426 pwm10_pin: pwm10-pin {
1427 rockchip,pins =
1428 <2 RK_PB4 2 &pcfg_pull_none>;
1429 };
1431 pwm10_pin_pull_down: pwm10-pin-pull-down {
1432 rockchip,pins =
1433 <2 RK_PB4 2 &pcfg_pull_down>;
1434 };
1435 };
1437 pwm11 {
1438 pwm11_pin: pwm11-pin {
1439 rockchip,pins =
1440 <2 RK_PC0 4 &pcfg_pull_none>;
1441 };
1443 pwm11_pin_pull_down: pwm11-pin-pull-down {
1444 rockchip,pins =
1445 <2 RK_PC0 4 &pcfg_pull_down>;
1446 };
1447 };
1449 rtc {
1450 rtc_32k: rtc-32k {
1451 rockchip,pins =
1452 <0 RK_PC3 1 &pcfg_pull_none>;
1453 };
1454 };
1456 sdmmc {
1457 sdmmc_clk: sdmmc-clk {
1458 rockchip,pins =
1459 <4 RK_PD5 1 &pcfg_pull_none_4ma>;
1460 };
1462 sdmmc_cmd: sdmmc-cmd {
1463 rockchip,pins =
1464 <4 RK_PD4 1 &pcfg_pull_up_4ma>;
1465 };
1467 sdmmc_det: sdmmc-det {
1468 rockchip,pins =
1469 <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1470 };
1472 sdmmc_pwren: sdmmc-pwren {
1473 rockchip,pins =
1474 <4 RK_PD6 1 &pcfg_pull_none_4ma>;
1475 };
1477 sdmmc_bus1: sdmmc-bus1 {
1478 rockchip,pins =
1479 <4 RK_PD0 1 &pcfg_pull_up_4ma>;
1480 };
1482 sdmmc_bus4: sdmmc-bus4 {
1483 rockchip,pins =
1484 <4 RK_PD0 1 &pcfg_pull_up_4ma>,
1485 <4 RK_PD1 1 &pcfg_pull_up_4ma>,
1486 <4 RK_PD2 1 &pcfg_pull_up_4ma>,
1487 <4 RK_PD3 1 &pcfg_pull_up_4ma>;
1488 };
1489 };
1491 sdio {
1492 sdio_clk: sdio-clk {
1493 rockchip,pins =
1494 <4 RK_PA5 1 &pcfg_pull_none_8ma>;
1495 };
1497 sdio_cmd: sdio-cmd {
1498 rockchip,pins =
1499 <4 RK_PA4 1 &pcfg_pull_up_8ma>;
1500 };
1502 sdio_pwren: sdio-pwren {
1503 rockchip,pins =
1504 <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1505 };
1507 sdio_wrpt: sdio-wrpt {
1508 rockchip,pins =
1509 <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1510 };
1512 sdio_intn: sdio-intn {
1513 rockchip,pins =
1514 <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1515 };
1517 sdio_bus1: sdio-bus1 {
1518 rockchip,pins =
1519 <4 RK_PA0 1 &pcfg_pull_up_8ma>;
1520 };
1522 sdio_bus4: sdio-bus4 {
1523 rockchip,pins =
1524 <4 RK_PA0 1 &pcfg_pull_up_8ma>,
1525 <4 RK_PA1 1 &pcfg_pull_up_8ma>,
1526 <4 RK_PA2 1 &pcfg_pull_up_8ma>,
1527 <4 RK_PA3 1 &pcfg_pull_up_8ma>;
1528 };
1529 };
1531 spdif_in {
1532 spdif_in: spdif-in {
1533 rockchip,pins =
1534 <0 RK_PC2 1 &pcfg_pull_none>;
1535 };
1536 };
1538 spdif_out {
1539 spdif_out: spdif-out {
1540 rockchip,pins =
1541 <0 RK_PC1 1 &pcfg_pull_none>;
1542 };
1543 };
1545 spi0 {
1546 spi0_clk: spi0-clk {
1547 rockchip,pins =
1548 <2 RK_PA2 2 &pcfg_pull_up_4ma>;
1549 };
1551 spi0_csn0: spi0-csn0 {
1552 rockchip,pins =
1553 <2 RK_PA3 2 &pcfg_pull_up_4ma>;
1554 };
1556 spi0_miso: spi0-miso {
1557 rockchip,pins =
1558 <2 RK_PA0 2 &pcfg_pull_up_4ma>;
1559 };
1561 spi0_mosi: spi0-mosi {
1562 rockchip,pins =
1563 <2 RK_PA1 2 &pcfg_pull_up_4ma>;
1564 };
1565 };
1567 spi1 {
1568 spi1_clk: spi1-clk {
1569 rockchip,pins =
1570 <3 RK_PB3 3 &pcfg_pull_up_4ma>;
1571 };
1573 spi1_csn0: spi1-csn0 {
1574 rockchip,pins =
1575 <3 RK_PB5 3 &pcfg_pull_up_4ma>;
1576 };
1578 spi1_miso: spi1-miso {
1579 rockchip,pins =
1580 <3 RK_PB2 3 &pcfg_pull_up_4ma>;
1581 };
1583 spi1_mosi: spi1-mosi {
1584 rockchip,pins =
1585 <3 RK_PB4 3 &pcfg_pull_up_4ma>;
1586 };
1587 };
1589 spi1-m1 {
1590 spi1m1_miso: spi1m1-miso {
1591 rockchip,pins =
1592 <2 RK_PA4 2 &pcfg_pull_up_4ma>;
1593 };
1595 spi1m1_mosi: spi1m1-mosi {
1596 rockchip,pins =
1597 <2 RK_PA5 2 &pcfg_pull_up_4ma>;
1598 };
1600 spi1m1_clk: spi1m1-clk {
1601 rockchip,pins =
1602 <2 RK_PA7 2 &pcfg_pull_up_4ma>;
1603 };
1605 spi1m1_csn0: spi1m1-csn0 {
1606 rockchip,pins =
1607 <2 RK_PB1 2 &pcfg_pull_up_4ma>;
1608 };
1609 };
1611 spi2 {
1612 spi2_clk: spi2-clk {
1613 rockchip,pins =
1614 <1 RK_PD0 3 &pcfg_pull_up_4ma>;
1615 };
1617 spi2_csn0: spi2-csn0 {
1618 rockchip,pins =
1619 <1 RK_PD1 3 &pcfg_pull_up_4ma>;
1620 };
1622 spi2_miso: spi2-miso {
1623 rockchip,pins =
1624 <1 RK_PC6 3 &pcfg_pull_up_4ma>;
1625 };
1627 spi2_mosi: spi2-mosi {
1628 rockchip,pins =
1629 <1 RK_PC7 3 &pcfg_pull_up_4ma>;
1630 };
1631 };
1633 tsadc {
1634 tsadc_otp_pin: tsadc-otp-pin {
1635 rockchip,pins =
1636 <0 RK_PB2 0 &pcfg_pull_none>;
1637 };
1639 tsadc_otp_out: tsadc-otp-out {
1640 rockchip,pins =
1641 <0 RK_PB2 1 &pcfg_pull_none>;
1642 };
1643 };
1645 uart0 {
1646 uart0_xfer: uart0-xfer {
1647 rockchip,pins =
1648 <2 RK_PA1 1 &pcfg_pull_up>,
1649 <2 RK_PA0 1 &pcfg_pull_up>;
1650 };
1652 uart0_cts: uart0-cts {
1653 rockchip,pins =
1654 <2 RK_PA2 1 &pcfg_pull_none>;
1655 };
1657 uart0_rts: uart0-rts {
1658 rockchip,pins =
1659 <2 RK_PA3 1 &pcfg_pull_none>;
1660 };
1662 uart0_rts_pin: uart0-rts-pin {
1663 rockchip,pins =
1664 <2 RK_PA3 0 &pcfg_pull_none>;
1665 };
1666 };
1668 uart1 {
1669 uart1_xfer: uart1-xfer {
1670 rockchip,pins =
1671 <1 RK_PD1 1 &pcfg_pull_up>,
1672 <1 RK_PD0 1 &pcfg_pull_up>;
1673 };
1675 uart1_cts: uart1-cts {
1676 rockchip,pins =
1677 <1 RK_PC6 1 &pcfg_pull_none>;
1678 };
1680 uart1_rts: uart1-rts {
1681 rockchip,pins =
1682 <1 RK_PC7 1 &pcfg_pull_none>;
1683 };
1684 };
1686 uart2-m0 {
1687 uart2m0_xfer: uart2m0-xfer {
1688 rockchip,pins =
1689 <1 RK_PC7 2 &pcfg_pull_up>,
1690 <1 RK_PC6 2 &pcfg_pull_up>;
1691 };
1692 };
1694 uart2-m1 {
1695 uart2m1_xfer: uart2m1-xfer {
1696 rockchip,pins =
1697 <4 RK_PD3 2 &pcfg_pull_up>,
1698 <4 RK_PD2 2 &pcfg_pull_up>;
1699 };
1700 };
1702 uart3 {
1703 uart3_xfer: uart3-xfer {
1704 rockchip,pins =
1705 <3 RK_PB5 4 &pcfg_pull_up>,
1706 <3 RK_PB4 4 &pcfg_pull_up>;
1707 };
1708 };
1710 uart3-m1 {
1711 uart3m1_xfer: uart3m1-xfer {
1712 rockchip,pins =
1713 <0 RK_PC2 3 &pcfg_pull_up>,
1714 <0 RK_PC1 3 &pcfg_pull_up>;
1715 };
1716 };
1718 uart4 {
1719 uart4_xfer: uart4-xfer {
1720 rockchip,pins =
1721 <4 RK_PB1 1 &pcfg_pull_up>,
1722 <4 RK_PB0 1 &pcfg_pull_up>;
1723 };
1725 uart4_cts: uart4-cts {
1726 rockchip,pins =
1727 <4 RK_PA6 1 &pcfg_pull_none>;
1728 };
1730 uart4_rts: uart4-rts {
1731 rockchip,pins =
1732 <4 RK_PA7 1 &pcfg_pull_none>;
1733 };
1735 uart4_rts_pin: uart4-rts-pin {
1736 rockchip,pins =
1737 <4 RK_PA7 0 &pcfg_pull_none>;
1738 };
1739 };
1740 };
1741 };