arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3328-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3328-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3328";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 serial0 = &uart0;
  24                 serial1 = &uart1;
  25                 serial2 = &uart2;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 ethernet0 = &gmac2io;
  31                 ethernet1 = &gmac2phy;
  32         };
  33
  34         cpus {
  35                 #address-cells = <2>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53";
  41                         reg = <0x0 0x0>;
  42                         clocks = <&cru ARMCLK>;
  43                         #cooling-cells = <2>;
  44                         cpu-idle-states = <&CPU_SLEEP>;
  45                         dynamic-power-coefficient = <120>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&l2>;
  48                         operating-points-v2 = <&cpu0_opp_table>;
  49                 };
  50
  51                 cpu1: cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0x0 0x1>;
  55                         clocks = <&cru ARMCLK>;
  56                         #cooling-cells = <2>;
  57                         cpu-idle-states = <&CPU_SLEEP>;
  58                         dynamic-power-coefficient = <120>;
  59                         enable-method = "psci";
  60                         next-level-cache = <&l2>;
  61                         operating-points-v2 = <&cpu0_opp_table>;
  62                 };
  63
  64                 cpu2: cpu@2 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53";
  67                         reg = <0x0 0x2>;
  68                         clocks = <&cru ARMCLK>;
  69                         #cooling-cells = <2>;
  70                         cpu-idle-states = <&CPU_SLEEP>;
  71                         dynamic-power-coefficient = <120>;
  72                         enable-method = "psci";
  73                         next-level-cache = <&l2>;
  74                         operating-points-v2 = <&cpu0_opp_table>;
  75                 };
  76
  77                 cpu3: cpu@3 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a53";
  80                         reg = <0x0 0x3>;
  81                         clocks = <&cru ARMCLK>;
  82                         #cooling-cells = <2>;
  83                         cpu-idle-states = <&CPU_SLEEP>;
  84                         dynamic-power-coefficient = <120>;
  85                         enable-method = "psci";
  86                         next-level-cache = <&l2>;
  87                         operating-points-v2 = <&cpu0_opp_table>;
  88                 };
  89
  90                 idle-states {
  91                         entry-method = "psci";
  92
  93                         CPU_SLEEP: cpu-sleep {
  94                                 compatible = "arm,idle-state";
  95                                 local-timer-stop;
  96                                 arm,psci-suspend-param = <0x0010000>;
  97                                 entry-latency-us = <120>;
  98                                 exit-latency-us = <250>;
  99                                 min-residency-us = <900>;
 100                         };
 101                 };
 102
 103                 l2: l2-cache0 {
 104                         compatible = "cache";
 105                 };
 106         };
 107
 108         cpu0_opp_table: opp_table0 {
 109                 compatible = "operating-points-v2";
 110                 opp-shared;
 111
 112                 opp-408000000 {
 113                         opp-hz = /bits/ 64 <408000000>;
 114                         opp-microvolt = <950000>;
 115                         clock-latency-ns = <40000>;
 116                         opp-suspend;
 117                 };
 118                 opp-600000000 {
 119                         opp-hz = /bits/ 64 <600000000>;
 120                         opp-microvolt = <950000>;
 121                         clock-latency-ns = <40000>;
 122                 };
 123                 opp-816000000 {
 124                         opp-hz = /bits/ 64 <816000000>;
 125                         opp-microvolt = <1000000>;
 126                         clock-latency-ns = <40000>;
 127                 };
 128                 opp-1008000000 {
 129                         opp-hz = /bits/ 64 <1008000000>;
 130                         opp-microvolt = <1100000>;
 131                         clock-latency-ns = <40000>;
 132                 };
 133                 opp-1200000000 {
 134                         opp-hz = /bits/ 64 <1200000000>;
 135                         opp-microvolt = <1225000>;
 136                         clock-latency-ns = <40000>;
 137                 };
 138                 opp-1296000000 {
 139                         opp-hz = /bits/ 64 <1296000000>;
 140                         opp-microvolt = <1300000>;
 141                         clock-latency-ns = <40000>;
 142                 };
 143         };
 144
 145         amba: bus {
 146                 compatible = "simple-bus";
 147                 #address-cells = <2>;
 148                 #size-cells = <2>;
 149                 ranges;
 150
 151                 dmac: dmac@ff1f0000 {
 152                         compatible = "arm,pl330", "arm,primecell";
 153                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 154                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 155                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 156                         arm,pl330-periph-burst;
 157                         clocks = <&cru ACLK_DMAC>;
 158                         clock-names = "apb_pclk";
 159                         #dma-cells = <1>;
 160                 };
 161         };
 162
 163         analog_sound: analog-sound {
 164                 compatible = "simple-audio-card";
 165                 simple-audio-card,format = "i2s";
 166                 simple-audio-card,mclk-fs = <256>;
 167                 simple-audio-card,name = "Analog";
 168                 status = "disabled";
 169
 170                 simple-audio-card,cpu {
 171                         sound-dai = <&i2s1>;
 172                 };
 173
 174                 simple-audio-card,codec {
 175                         sound-dai = <&codec>;
 176                 };
 177         };
 178
 179         arm-pmu {
 180                 compatible = "arm,cortex-a53-pmu";
 181                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 185                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 186         };
 187
 188         display_subsystem: display-subsystem {
 189                 compatible = "rockchip,display-subsystem";
 190                 ports = <&vop_out>;
 191         };
 192
 193         hdmi_sound: hdmi-sound {
 194                 compatible = "simple-audio-card";
 195                 simple-audio-card,format = "i2s";
 196                 simple-audio-card,mclk-fs = <128>;
 197                 simple-audio-card,name = "HDMI";
 198                 status = "disabled";
 199
 200                 simple-audio-card,cpu {
 201                         sound-dai = <&i2s0>;
 202                 };
 203
 204                 simple-audio-card,codec {
 205                         sound-dai = <&hdmi>;
 206                 };
 207         };
 208
 209         psci {
 210                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 211                 method = "smc";
 212         };
 213
 214         timer {
 215                 compatible = "arm,armv8-timer";
 216                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 217                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 218                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 219                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 220         };
 221
 222         xin24m: xin24m {
 223                 compatible = "fixed-clock";
 224                 #clock-cells = <0>;
 225                 clock-frequency = <24000000>;
 226                 clock-output-names = "xin24m";
 227         };
 228
 229         i2s0: i2s@ff000000 {
 230                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 231                 reg = <0x0 0xff000000 0x0 0x1000>;
 232                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 234                 clock-names = "i2s_clk", "i2s_hclk";
 235                 dmas = <&dmac 11>, <&dmac 12>;
 236                 dma-names = "tx", "rx";
 237                 #sound-dai-cells = <0>;
 238                 status = "disabled";
 239         };
 240
 241         i2s1: i2s@ff010000 {
 242                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 243                 reg = <0x0 0xff010000 0x0 0x1000>;
 244                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 245                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 246                 clock-names = "i2s_clk", "i2s_hclk";
 247                 dmas = <&dmac 14>, <&dmac 15>;
 248                 dma-names = "tx", "rx";
 249                 #sound-dai-cells = <0>;
 250                 status = "disabled";
 251         };
 252
 253         i2s2: i2s@ff020000 {
 254                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 255                 reg = <0x0 0xff020000 0x0 0x1000>;
 256                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 257                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 258                 clock-names = "i2s_clk", "i2s_hclk";
 259                 dmas = <&dmac 0>, <&dmac 1>;
 260                 dma-names = "tx", "rx";
 261                 #sound-dai-cells = <0>;
 262                 status = "disabled";
 263         };
 264
 265         spdif: spdif@ff030000 {
 266                 compatible = "rockchip,rk3328-spdif";
 267                 reg = <0x0 0xff030000 0x0 0x1000>;
 268                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 270                 clock-names = "mclk", "hclk";
 271                 dmas = <&dmac 10>;
 272                 dma-names = "tx";
 273                 pinctrl-names = "default";
 274                 pinctrl-0 = <&spdifm2_tx>;
 275                 #sound-dai-cells = <0>;
 276                 status = "disabled";
 277         };
 278
 279         pdm: pdm@ff040000 {
 280                 compatible = "rockchip,pdm";
 281                 reg = <0x0 0xff040000 0x0 0x1000>;
 282                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 283                 clock-names = "pdm_clk", "pdm_hclk";
 284                 dmas = <&dmac 16>;
 285                 dma-names = "rx";
 286                 pinctrl-names = "default", "sleep";
 287                 pinctrl-0 = <&pdmm0_clk
 288                              &pdmm0_sdi0
 289                              &pdmm0_sdi1
 290                              &pdmm0_sdi2
 291                              &pdmm0_sdi3>;
 292                 pinctrl-1 = <&pdmm0_clk_sleep
 293                              &pdmm0_sdi0_sleep
 294                              &pdmm0_sdi1_sleep
 295                              &pdmm0_sdi2_sleep
 296                              &pdmm0_sdi3_sleep>;
 297                 status = "disabled";
 298         };
 299
 300         grf: syscon@ff100000 {
 301                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 302                 reg = <0x0 0xff100000 0x0 0x1000>;
 303
 304                 io_domains: io-domains {
 305                         compatible = "rockchip,rk3328-io-voltage-domain";
 306                         status = "disabled";
 307                 };
 308
 309                 grf_gpio: grf-gpio {
 310                         compatible = "rockchip,rk3328-grf-gpio";
 311                         gpio-controller;
 312                         #gpio-cells = <2>;
 313                 };
 314
 315                 power: power-controller {
 316                         compatible = "rockchip,rk3328-power-controller";
 317                         #power-domain-cells = <1>;
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320
 321                         pd_hevc@RK3328_PD_HEVC {
 322                                 reg = <RK3328_PD_HEVC>;
 323                         };
 324                         pd_video@RK3328_PD_VIDEO {
 325                                 reg = <RK3328_PD_VIDEO>;
 326                         };
 327                         pd_vpu@RK3328_PD_VPU {
 328                                 reg = <RK3328_PD_VPU>;
 329                                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 330                         };
 331                 };
 332
 333                 reboot-mode {
 334                         compatible = "syscon-reboot-mode";
 335                         offset = <0x5c8>;
 336                         mode-normal = <BOOT_NORMAL>;
 337                         mode-recovery = <BOOT_RECOVERY>;
 338                         mode-bootloader = <BOOT_FASTBOOT>;
 339                         mode-loader = <BOOT_BL_DOWNLOAD>;
 340                 };
 341         };
 342
 343         uart0: serial@ff110000 {
 344                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 345                 reg = <0x0 0xff110000 0x0 0x100>;
 346                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 347                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 348                 clock-names = "baudclk", "apb_pclk";
 349                 dmas = <&dmac 2>, <&dmac 3>;
 350                 dma-names = "tx", "rx";
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 353                 reg-io-width = <4>;
 354                 reg-shift = <2>;
 355                 status = "disabled";
 356         };
 357
 358         uart1: serial@ff120000 {
 359                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 360                 reg = <0x0 0xff120000 0x0 0x100>;
 361                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 363                 clock-names = "baudclk", "apb_pclk";
 364                 dmas = <&dmac 4>, <&dmac 5>;
 365                 dma-names = "tx", "rx";
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 368                 reg-io-width = <4>;
 369                 reg-shift = <2>;
 370                 status = "disabled";
 371         };
 372
 373         uart2: serial@ff130000 {
 374                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 375                 reg = <0x0 0xff130000 0x0 0x100>;
 376                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 378                 clock-names = "baudclk", "apb_pclk";
 379                 dmas = <&dmac 6>, <&dmac 7>;
 380                 dma-names = "tx", "rx";
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&uart2m1_xfer>;
 383                 reg-io-width = <4>;
 384                 reg-shift = <2>;
 385                 status = "disabled";
 386         };
 387
 388         i2c0: i2c@ff150000 {
 389                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 390                 reg = <0x0 0xff150000 0x0 0x1000>;
 391                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 395                 clock-names = "i2c", "pclk";
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&i2c0_xfer>;
 398                 status = "disabled";
 399         };
 400
 401         i2c1: i2c@ff160000 {
 402                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 403                 reg = <0x0 0xff160000 0x0 0x1000>;
 404                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 408                 clock-names = "i2c", "pclk";
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&i2c1_xfer>;
 411                 status = "disabled";
 412         };
 413
 414         i2c2: i2c@ff170000 {
 415                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 416                 reg = <0x0 0xff170000 0x0 0x1000>;
 417                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 421                 clock-names = "i2c", "pclk";
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&i2c2_xfer>;
 424                 status = "disabled";
 425         };
 426
 427         i2c3: i2c@ff180000 {
 428                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 429                 reg = <0x0 0xff180000 0x0 0x1000>;
 430                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 431                 #address-cells = <1>;
 432                 #size-cells = <0>;
 433                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 434                 clock-names = "i2c", "pclk";
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&i2c3_xfer>;
 437                 status = "disabled";
 438         };
 439
 440         spi0: spi@ff190000 {
 441                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 442                 reg = <0x0 0xff190000 0x0 0x1000>;
 443                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 447                 clock-names = "spiclk", "apb_pclk";
 448                 dmas = <&dmac 8>, <&dmac 9>;
 449                 dma-names = "tx", "rx";
 450                 pinctrl-names = "default";
 451                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 452                 status = "disabled";
 453         };
 454
 455         wdt: watchdog@ff1a0000 {
 456                 compatible = "snps,dw-wdt";
 457                 reg = <0x0 0xff1a0000 0x0 0x100>;
 458                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 459                 clocks = <&cru PCLK_WDT>;
 460         };
 461
 462         pwm0: pwm@ff1b0000 {
 463                 compatible = "rockchip,rk3328-pwm";
 464                 reg = <0x0 0xff1b0000 0x0 0x10>;
 465                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 466                 clock-names = "pwm", "pclk";
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&pwm0_pin>;
 469                 #pwm-cells = <3>;
 470                 status = "disabled";
 471         };
 472
 473         pwm1: pwm@ff1b0010 {
 474                 compatible = "rockchip,rk3328-pwm";
 475                 reg = <0x0 0xff1b0010 0x0 0x10>;
 476                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 477                 clock-names = "pwm", "pclk";
 478                 pinctrl-names = "default";
 479                 pinctrl-0 = <&pwm1_pin>;
 480                 #pwm-cells = <3>;
 481                 status = "disabled";
 482         };
 483
 484         pwm2: pwm@ff1b0020 {
 485                 compatible = "rockchip,rk3328-pwm";
 486                 reg = <0x0 0xff1b0020 0x0 0x10>;
 487                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 488                 clock-names = "pwm", "pclk";
 489                 pinctrl-names = "default";
 490                 pinctrl-0 = <&pwm2_pin>;
 491                 #pwm-cells = <3>;
 492                 status = "disabled";
 493         };
 494
 495         pwm3: pwm@ff1b0030 {
 496                 compatible = "rockchip,rk3328-pwm";
 497                 reg = <0x0 0xff1b0030 0x0 0x10>;
 498                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 499                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 500                 clock-names = "pwm", "pclk";
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&pwmir_pin>;
 503                 #pwm-cells = <3>;
 504                 status = "disabled";
 505         };
 506
 507         thermal-zones {
 508                 soc_thermal: soc-thermal {
 509                         polling-delay-passive = <20>;
 510                         polling-delay = <1000>;
 511                         sustainable-power = <1000>;
 512
 513                         thermal-sensors = <&tsadc 0>;
 514
 515                         trips {
 516                                 threshold: trip-point0 {
 517                                         temperature = <70000>;
 518                                         hysteresis = <2000>;
 519                                         type = "passive";
 520                                 };
 521                                 target: trip-point1 {
 522                                         temperature = <85000>;
 523                                         hysteresis = <2000>;
 524                                         type = "passive";
 525                                 };
 526                                 soc_crit: soc-crit {
 527                                         temperature = <95000>;
 528                                         hysteresis = <2000>;
 529                                         type = "critical";
 530                                 };
 531                         };
 532
 533                         cooling-maps {
 534                                 map0 {
 535                                         trip = <&target>;
 536                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 537                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 538                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 539                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 540                                         contribution = <4096>;
 541                                 };
 542                         };
 543                 };
 544
 545         };
 546
 547         tsadc: tsadc@ff250000 {
 548                 compatible = "rockchip,rk3328-tsadc";
 549                 reg = <0x0 0xff250000 0x0 0x100>;
 550                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 551                 assigned-clocks = <&cru SCLK_TSADC>;
 552                 assigned-clock-rates = <50000>;
 553                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 554                 clock-names = "tsadc", "apb_pclk";
 555                 pinctrl-names = "init", "default", "sleep";
 556                 pinctrl-0 = <&otp_pin>;
 557                 pinctrl-1 = <&otp_out>;
 558                 pinctrl-2 = <&otp_pin>;
 559                 resets = <&cru SRST_TSADC>;
 560                 reset-names = "tsadc-apb";
 561                 rockchip,grf = <&grf>;
 562                 rockchip,hw-tshut-temp = <100000>;
 563                 #thermal-sensor-cells = <1>;
 564                 status = "disabled";
 565         };
 566
 567         efuse: efuse@ff260000 {
 568                 compatible = "rockchip,rk3328-efuse";
 569                 reg = <0x0 0xff260000 0x0 0x50>;
 570                 #address-cells = <1>;
 571                 #size-cells = <1>;
 572                 clocks = <&cru SCLK_EFUSE>;
 573                 clock-names = "pclk_efuse";
 574                 rockchip,efuse-size = <0x20>;
 575
 576                 /* Data cells */
 577                 efuse_id: id@7 {
 578                         reg = <0x07 0x10>;
 579                 };
 580                 cpu_leakage: cpu-leakage@17 {
 581                         reg = <0x17 0x1>;
 582                 };
 583                 logic_leakage: logic-leakage@19 {
 584                         reg = <0x19 0x1>;
 585                 };
 586                 efuse_cpu_version: cpu-version@1a {
 587                         reg = <0x1a 0x1>;
 588                         bits = <3 3>;
 589                 };
 590         };
 591
 592         saradc: adc@ff280000 {
 593                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 594                 reg = <0x0 0xff280000 0x0 0x100>;
 595                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 596                 #io-channel-cells = <1>;
 597                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 598                 clock-names = "saradc", "apb_pclk";
 599                 resets = <&cru SRST_SARADC_P>;
 600                 reset-names = "saradc-apb";
 601                 status = "disabled";
 602         };
 603
 604         gpu: gpu@ff300000 {
 605                 compatible = "rockchip,rk3328-mali", "arm,mali-450";
 606                 reg = <0x0 0xff300000 0x0 0x40000>;
 607                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 608                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 609                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 610                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 611                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 612                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 613                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 614                 interrupt-names = "gp",
 615                                   "gpmmu",
 616                                   "pp",
 617                                   "pp0",
 618                                   "ppmmu0",
 619                                   "pp1",
 620                                   "ppmmu1";
 621                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 622                 clock-names = "bus", "core";
 623                 resets = <&cru SRST_GPU_A>;
 624         };
 625
 626         h265e_mmu: iommu@ff330200 {
 627                 compatible = "rockchip,iommu";
 628                 reg = <0x0 0xff330200 0 0x100>;
 629                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 630                 interrupt-names = "h265e_mmu";
 631                 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
 632                 clock-names = "aclk", "iface";
 633                 #iommu-cells = <0>;
 634                 status = "disabled";
 635         };
 636
 637         vepu_mmu: iommu@ff340800 {
 638                 compatible = "rockchip,iommu";
 639                 reg = <0x0 0xff340800 0x0 0x40>;
 640                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 641                 interrupt-names = "vepu_mmu";
 642                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 643                 clock-names = "aclk", "iface";
 644                 #iommu-cells = <0>;
 645                 status = "disabled";
 646         };
 647
 648         vpu: video-codec@ff350000 {
 649                 compatible = "rockchip,rk3328-vpu";
 650                 reg = <0x0 0xff350000 0x0 0x800>;
 651                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 652                 interrupt-names = "vdpu";
 653                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 654                 clock-names = "aclk", "hclk";
 655                 iommus = <&vpu_mmu>;
 656                 power-domains = <&power RK3328_PD_VPU>;
 657         };
 658
 659         vpu_mmu: iommu@ff350800 {
 660                 compatible = "rockchip,iommu";
 661                 reg = <0x0 0xff350800 0x0 0x40>;
 662                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 663                 interrupt-names = "vpu_mmu";
 664                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 665                 clock-names = "aclk", "iface";
 666                 #iommu-cells = <0>;
 667                 power-domains = <&power RK3328_PD_VPU>;
 668         };
 669
 670         rkvdec_mmu: iommu@ff360480 {
 671                 compatible = "rockchip,iommu";
 672                 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
 673                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 674                 interrupt-names = "rkvdec_mmu";
 675                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
 676                 clock-names = "aclk", "iface";
 677                 #iommu-cells = <0>;
 678                 status = "disabled";
 679         };
 680
 681         vop: vop@ff370000 {
 682                 compatible = "rockchip,rk3328-vop";
 683                 reg = <0x0 0xff370000 0x0 0x3efc>;
 684                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 685                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 686                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 687                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 688                 reset-names = "axi", "ahb", "dclk";
 689                 iommus = <&vop_mmu>;
 690                 status = "disabled";
 691
 692                 vop_out: port {
 693                         #address-cells = <1>;
 694                         #size-cells = <0>;
 695
 696                         vop_out_hdmi: endpoint@0 {
 697                                 reg = <0>;
 698                                 remote-endpoint = <&hdmi_in_vop>;
 699                         };
 700                 };
 701         };
 702
 703         vop_mmu: iommu@ff373f00 {
 704                 compatible = "rockchip,iommu";
 705                 reg = <0x0 0xff373f00 0x0 0x100>;
 706                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 707                 interrupt-names = "vop_mmu";
 708                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 709                 clock-names = "aclk", "iface";
 710                 #iommu-cells = <0>;
 711                 status = "disabled";
 712         };
 713
 714         hdmi: hdmi@ff3c0000 {
 715                 compatible = "rockchip,rk3328-dw-hdmi";
 716                 reg = <0x0 0xff3c0000 0x0 0x20000>;
 717                 reg-io-width = <4>;
 718                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 719                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 720                 clocks = <&cru PCLK_HDMI>,
 721                          <&cru SCLK_HDMI_SFC>,
 722                          <&cru SCLK_RTC32K>;
 723                 clock-names = "iahb",
 724                               "isfr",
 725                               "cec";
 726                 phys = <&hdmiphy>;
 727                 phy-names = "hdmi";
 728                 pinctrl-names = "default";
 729                 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
 730                 rockchip,grf = <&grf>;
 731                 #sound-dai-cells = <0>;
 732                 status = "disabled";
 733
 734                 ports {
 735                         hdmi_in: port {
 736                                 hdmi_in_vop: endpoint {
 737                                         remote-endpoint = <&vop_out_hdmi>;
 738                                 };
 739                         };
 740                 };
 741         };
 742
 743         codec: codec@ff410000 {
 744                 compatible = "rockchip,rk3328-codec";
 745                 reg = <0x0 0xff410000 0x0 0x1000>;
 746                 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
 747                 clock-names = "pclk", "mclk";
 748                 rockchip,grf = <&grf>;
 749                 #sound-dai-cells = <0>;
 750                 status = "disabled";
 751         };
 752
 753         hdmiphy: phy@ff430000 {
 754                 compatible = "rockchip,rk3328-hdmi-phy";
 755                 reg = <0x0 0xff430000 0x0 0x10000>;
 756                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 757                 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
 758                 clock-names = "sysclk", "refoclk", "refpclk";
 759                 clock-output-names = "hdmi_phy";
 760                 #clock-cells = <0>;
 761                 nvmem-cells = <&efuse_cpu_version>;
 762                 nvmem-cell-names = "cpu-version";
 763                 #phy-cells = <0>;
 764                 status = "disabled";
 765         };
 766
 767         cru: clock-controller@ff440000 {
 768                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 769                 reg = <0x0 0xff440000 0x0 0x1000>;
 770                 rockchip,grf = <&grf>;
 771                 #clock-cells = <1>;
 772                 #reset-cells = <1>;
 773                 assigned-clocks =
 774                         /*
 775                          * CPLL should run at 1200, but that is to high for
 776                          * the initial dividers of most of its children.
 777                          * We need set cpll child clk div first,
 778                          * and then set the cpll frequency.
 779                          */
 780                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 781                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 782                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 783                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 784                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 785                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 786                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 787                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 788                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 789                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 790                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 791                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 792                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 793                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 794                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 795                         <&cru SCLK_RTC32K>;
 796                 assigned-clock-parents =
 797                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 798                         <&cru PLL_GPLL>, <&xin24m>,
 799                         <&xin24m>, <&xin24m>;
 800                 assigned-clock-rates =
 801                         <0>, <61440000>,
 802                         <0>, <24000000>,
 803                         <24000000>, <24000000>,
 804                         <15000000>, <15000000>,
 805                         <100000000>, <100000000>,
 806                         <100000000>, <100000000>,
 807                         <50000000>, <100000000>,
 808                         <100000000>, <100000000>,
 809                         <50000000>, <50000000>,
 810                         <50000000>, <50000000>,
 811                         <24000000>, <600000000>,
 812                         <491520000>, <1200000000>,
 813                         <150000000>, <75000000>,
 814                         <75000000>, <150000000>,
 815                         <75000000>, <75000000>,
 816                         <32768>;
 817         };
 818
 819         usb2phy_grf: syscon@ff450000 {
 820                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 821                              "simple-mfd";
 822                 reg = <0x0 0xff450000 0x0 0x10000>;
 823                 #address-cells = <1>;
 824                 #size-cells = <1>;
 825
 826                 u2phy: usb2-phy@100 {
 827                         compatible = "rockchip,rk3328-usb2phy";
 828                         reg = <0x100 0x10>;
 829                         clocks = <&xin24m>;
 830                         clock-names = "phyclk";
 831                         clock-output-names = "usb480m_phy";
 832                         #clock-cells = <0>;
 833                         assigned-clocks = <&cru USB480M>;
 834                         assigned-clock-parents = <&u2phy>;
 835                         status = "disabled";
 836
 837                         u2phy_otg: otg-port {
 838                                 #phy-cells = <0>;
 839                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 840                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 841                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 842                                 interrupt-names = "otg-bvalid", "otg-id",
 843                                                   "linestate";
 844                                 status = "disabled";
 845                         };
 846
 847                         u2phy_host: host-port {
 848                                 #phy-cells = <0>;
 849                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 850                                 interrupt-names = "linestate";
 851                                 status = "disabled";
 852                         };
 853                 };
 854         };
 855
 856         sdmmc: mmc@ff500000 {
 857                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 858                 reg = <0x0 0xff500000 0x0 0x4000>;
 859                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 860                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 861                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 862                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 863                 fifo-depth = <0x100>;
 864                 max-frequency = <150000000>;
 865                 status = "disabled";
 866         };
 867
 868         sdio: mmc@ff510000 {
 869                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 870                 reg = <0x0 0xff510000 0x0 0x4000>;
 871                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 872                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 873                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 874                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 875                 fifo-depth = <0x100>;
 876                 max-frequency = <150000000>;
 877                 status = "disabled";
 878         };
 879
 880         emmc: mmc@ff520000 {
 881                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 882                 reg = <0x0 0xff520000 0x0 0x4000>;
 883                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 884                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 885                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 886                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 887                 fifo-depth = <0x100>;
 888                 max-frequency = <150000000>;
 889                 status = "disabled";
 890         };
 891
 892         gmac2io: ethernet@ff540000 {
 893                 compatible = "rockchip,rk3328-gmac";
 894                 reg = <0x0 0xff540000 0x0 0x10000>;
 895                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 896                 interrupt-names = "macirq";
 897                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 898                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 899                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 900                          <&cru PCLK_MAC2IO>;
 901                 clock-names = "stmmaceth", "mac_clk_rx",
 902                               "mac_clk_tx", "clk_mac_ref",
 903                               "clk_mac_refout", "aclk_mac",
 904                               "pclk_mac";
 905                 resets = <&cru SRST_GMAC2IO_A>;
 906                 reset-names = "stmmaceth";
 907                 rockchip,grf = <&grf>;
 908                 snps,txpbl = <0x4>;
 909                 status = "disabled";
 910         };
 911
 912         gmac2phy: ethernet@ff550000 {
 913                 compatible = "rockchip,rk3328-gmac";
 914                 reg = <0x0 0xff550000 0x0 0x10000>;
 915                 rockchip,grf = <&grf>;
 916                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 917                 interrupt-names = "macirq";
 918                 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
 919                          <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
 920                          <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
 921                          <&cru SCLK_MAC2PHY_OUT>;
 922                 clock-names = "stmmaceth", "mac_clk_rx",
 923                               "mac_clk_tx", "clk_mac_ref",
 924                               "aclk_mac", "pclk_mac",
 925                               "clk_macphy";
 926                 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
 927                 reset-names = "stmmaceth", "mac-phy";
 928                 phy-mode = "rmii";
 929                 phy-handle = <&phy>;
 930                 snps,txpbl = <0x4>;
 931                 status = "disabled";
 932
 933                 mdio {
 934                         compatible = "snps,dwmac-mdio";
 935                         #address-cells = <1>;
 936                         #size-cells = <0>;
 937
 938                         phy: ethernet-phy@0 {
 939                                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
 940                                 reg = <0>;
 941                                 clocks = <&cru SCLK_MAC2PHY_OUT>;
 942                                 resets = <&cru SRST_MACPHY>;
 943                                 pinctrl-names = "default";
 944                                 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
 945                                 phy-is-integrated;
 946                         };
 947                 };
 948         };
 949
 950         usb20_otg: usb@ff580000 {
 951                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 952                              "snps,dwc2";
 953                 reg = <0x0 0xff580000 0x0 0x40000>;
 954                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 955                 clocks = <&cru HCLK_OTG>;
 956                 clock-names = "otg";
 957                 dr_mode = "otg";
 958                 g-np-tx-fifo-size = <16>;
 959                 g-rx-fifo-size = <280>;
 960                 g-tx-fifo-size = <256 128 128 64 32 16>;
 961                 phys = <&u2phy_otg>;
 962                 phy-names = "usb2-phy";
 963                 status = "disabled";
 964         };
 965
 966         usb_host0_ehci: usb@ff5c0000 {
 967                 compatible = "generic-ehci";
 968                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 969                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 970                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 971                 phys = <&u2phy_host>;
 972                 phy-names = "usb";
 973                 status = "disabled";
 974         };
 975
 976         usb_host0_ohci: usb@ff5d0000 {
 977                 compatible = "generic-ohci";
 978                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 979                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 980                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 981                 phys = <&u2phy_host>;
 982                 phy-names = "usb";
 983                 status = "disabled";
 984         };
 985
 986         gic: interrupt-controller@ff811000 {
 987                 compatible = "arm,gic-400";
 988                 #interrupt-cells = <3>;
 989                 #address-cells = <0>;
 990                 interrupt-controller;
 991                 reg = <0x0 0xff811000 0 0x1000>,
 992                       <0x0 0xff812000 0 0x2000>,
 993                       <0x0 0xff814000 0 0x2000>,
 994                       <0x0 0xff816000 0 0x2000>;
 995                 interrupts = <GIC_PPI 9
 996                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 997         };
 998
 999         pinctrl: pinctrl {
1000                 compatible = "rockchip,rk3328-pinctrl";
1001                 rockchip,grf = <&grf>;
1002                 #address-cells = <2>;
1003                 #size-cells = <2>;
1004                 ranges;
1005
1006                 gpio0: gpio0@ff210000 {
1007                         compatible = "rockchip,gpio-bank";
1008                         reg = <0x0 0xff210000 0x0 0x100>;
1009                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1010                         clocks = <&cru PCLK_GPIO0>;
1011
1012                         gpio-controller;
1013                         #gpio-cells = <2>;
1014
1015                         interrupt-controller;
1016                         #interrupt-cells = <2>;
1017                 };
1018
1019                 gpio1: gpio1@ff220000 {
1020                         compatible = "rockchip,gpio-bank";
1021                         reg = <0x0 0xff220000 0x0 0x100>;
1022                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1023                         clocks = <&cru PCLK_GPIO1>;
1024
1025                         gpio-controller;
1026                         #gpio-cells = <2>;
1027
1028                         interrupt-controller;
1029                         #interrupt-cells = <2>;
1030                 };
1031
1032                 gpio2: gpio2@ff230000 {
1033                         compatible = "rockchip,gpio-bank";
1034                         reg = <0x0 0xff230000 0x0 0x100>;
1035                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1036                         clocks = <&cru PCLK_GPIO2>;
1037
1038                         gpio-controller;
1039                         #gpio-cells = <2>;
1040
1041                         interrupt-controller;
1042                         #interrupt-cells = <2>;
1043                 };
1044
1045                 gpio3: gpio3@ff240000 {
1046                         compatible = "rockchip,gpio-bank";
1047                         reg = <0x0 0xff240000 0x0 0x100>;
1048                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1049                         clocks = <&cru PCLK_GPIO3>;
1050
1051                         gpio-controller;
1052                         #gpio-cells = <2>;
1053
1054                         interrupt-controller;
1055                         #interrupt-cells = <2>;
1056                 };
1057
1058                 pcfg_pull_up: pcfg-pull-up {
1059                         bias-pull-up;
1060                 };
1061
1062                 pcfg_pull_down: pcfg-pull-down {
1063                         bias-pull-down;
1064                 };
1065
1066                 pcfg_pull_none: pcfg-pull-none {
1067                         bias-disable;
1068                 };
1069
1070                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1071                         bias-disable;
1072                         drive-strength = <2>;
1073                 };
1074
1075                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1076                         bias-pull-up;
1077                         drive-strength = <2>;
1078                 };
1079
1080                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1081                         bias-pull-up;
1082                         drive-strength = <4>;
1083                 };
1084
1085                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1086                         bias-disable;
1087                         drive-strength = <4>;
1088                 };
1089
1090                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1091                         bias-pull-down;
1092                         drive-strength = <4>;
1093                 };
1094
1095                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1096                         bias-disable;
1097                         drive-strength = <8>;
1098                 };
1099
1100                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1101                         bias-pull-up;
1102                         drive-strength = <8>;
1103                 };
1104
1105                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1106                         bias-disable;
1107                         drive-strength = <12>;
1108                 };
1109
1110                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1111                         bias-pull-up;
1112                         drive-strength = <12>;
1113                 };
1114
1115                 pcfg_output_high: pcfg-output-high {
1116                         output-high;
1117                 };
1118
1119                 pcfg_output_low: pcfg-output-low {
1120                         output-low;
1121                 };
1122
1123                 pcfg_input_high: pcfg-input-high {
1124                         bias-pull-up;
1125                         input-enable;
1126                 };
1127
1128                 pcfg_input: pcfg-input {
1129                         input-enable;
1130                 };
1131
1132                 i2c0 {
1133                         i2c0_xfer: i2c0-xfer {
1134                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1135                                                 <2 RK_PD1 1 &pcfg_pull_none>;
1136                         };
1137                 };
1138
1139                 i2c1 {
1140                         i2c1_xfer: i2c1-xfer {
1141                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1142                                                 <2 RK_PA5 2 &pcfg_pull_none>;
1143                         };
1144                 };
1145
1146                 i2c2 {
1147                         i2c2_xfer: i2c2-xfer {
1148                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1149                                                 <2 RK_PB6 1 &pcfg_pull_none>;
1150                         };
1151                 };
1152
1153                 i2c3 {
1154                         i2c3_xfer: i2c3-xfer {
1155                                 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1156                                                 <0 RK_PA6 2 &pcfg_pull_none>;
1157                         };
1158                         i2c3_pins: i2c3-pins {
1159                                 rockchip,pins =
1160                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1161                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1162                         };
1163                 };
1164
1165                 hdmi_i2c {
1166                         hdmii2c_xfer: hdmii2c-xfer {
1167                                 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1168                                                 <0 RK_PA6 1 &pcfg_pull_none>;
1169                         };
1170                 };
1171
1172                 pdm-0 {
1173                         pdmm0_clk: pdmm0-clk {
1174                                 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1175                         };
1176
1177                         pdmm0_fsync: pdmm0-fsync {
1178                                 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1179                         };
1180
1181                         pdmm0_sdi0: pdmm0-sdi0 {
1182                                 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1183                         };
1184
1185                         pdmm0_sdi1: pdmm0-sdi1 {
1186                                 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1187                         };
1188
1189                         pdmm0_sdi2: pdmm0-sdi2 {
1190                                 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1191                         };
1192
1193                         pdmm0_sdi3: pdmm0-sdi3 {
1194                                 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1195                         };
1196
1197                         pdmm0_clk_sleep: pdmm0-clk-sleep {
1198                                 rockchip,pins =
1199                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1200                         };
1201
1202                         pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1203                                 rockchip,pins =
1204                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1205                         };
1206
1207                         pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1208                                 rockchip,pins =
1209                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1210                         };
1211
1212                         pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1213                                 rockchip,pins =
1214                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1215                         };
1216
1217                         pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1218                                 rockchip,pins =
1219                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1220                         };
1221
1222                         pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1223                                 rockchip,pins =
1224                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1225                         };
1226                 };
1227
1228                 tsadc {
1229                         otp_pin: otp-pin {
1230                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1231                         };
1232
1233                         otp_out: otp-out {
1234                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1235                         };
1236                 };
1237
1238                 uart0 {
1239                         uart0_xfer: uart0-xfer {
1240                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1241                                                 <1 RK_PB0 1 &pcfg_pull_up>;
1242                         };
1243
1244                         uart0_cts: uart0-cts {
1245                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1246                         };
1247
1248                         uart0_rts: uart0-rts {
1249                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1250                         };
1251
1252                         uart0_rts_pin: uart0-rts-pin {
1253                                 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1254                         };
1255                 };
1256
1257                 uart1 {
1258                         uart1_xfer: uart1-xfer {
1259                                 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1260                                                 <3 RK_PA6 4 &pcfg_pull_up>;
1261                         };
1262
1263                         uart1_cts: uart1-cts {
1264                                 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1265                         };
1266
1267                         uart1_rts: uart1-rts {
1268                                 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1269                         };
1270
1271                         uart1_rts_pin: uart1-rts-pin {
1272                                 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1273                         };
1274                 };
1275
1276                 uart2-0 {
1277                         uart2m0_xfer: uart2m0-xfer {
1278                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1279                                                 <1 RK_PA1 2 &pcfg_pull_up>;
1280                         };
1281                 };
1282
1283                 uart2-1 {
1284                         uart2m1_xfer: uart2m1-xfer {
1285                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1286                                                 <2 RK_PA1 1 &pcfg_pull_up>;
1287                         };
1288                 };
1289
1290                 spi0-0 {
1291                         spi0m0_clk: spi0m0-clk {
1292                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1293                         };
1294
1295                         spi0m0_cs0: spi0m0-cs0 {
1296                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1297                         };
1298
1299                         spi0m0_tx: spi0m0-tx {
1300                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1301                         };
1302
1303                         spi0m0_rx: spi0m0-rx {
1304                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1305                         };
1306
1307                         spi0m0_cs1: spi0m0-cs1 {
1308                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1309                         };
1310                 };
1311
1312                 spi0-1 {
1313                         spi0m1_clk: spi0m1-clk {
1314                                 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1315                         };
1316
1317                         spi0m1_cs0: spi0m1-cs0 {
1318                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1319                         };
1320
1321                         spi0m1_tx: spi0m1-tx {
1322                                 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1323                         };
1324
1325                         spi0m1_rx: spi0m1-rx {
1326                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1327                         };
1328
1329                         spi0m1_cs1: spi0m1-cs1 {
1330                                 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1331                         };
1332                 };
1333
1334                 spi0-2 {
1335                         spi0m2_clk: spi0m2-clk {
1336                                 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1337                         };
1338
1339                         spi0m2_cs0: spi0m2-cs0 {
1340                                 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1341                         };
1342
1343                         spi0m2_tx: spi0m2-tx {
1344                                 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1345                         };
1346
1347                         spi0m2_rx: spi0m2-rx {
1348                                 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1349                         };
1350                 };
1351
1352                 i2s1 {
1353                         i2s1_mclk: i2s1-mclk {
1354                                 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1355                         };
1356
1357                         i2s1_sclk: i2s1-sclk {
1358                                 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1359                         };
1360
1361                         i2s1_lrckrx: i2s1-lrckrx {
1362                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1363                         };
1364
1365                         i2s1_lrcktx: i2s1-lrcktx {
1366                                 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1367                         };
1368
1369                         i2s1_sdi: i2s1-sdi {
1370                                 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1371                         };
1372
1373                         i2s1_sdo: i2s1-sdo {
1374                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1375                         };
1376
1377                         i2s1_sdio1: i2s1-sdio1 {
1378                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1379                         };
1380
1381                         i2s1_sdio2: i2s1-sdio2 {
1382                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1383                         };
1384
1385                         i2s1_sdio3: i2s1-sdio3 {
1386                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1387                         };
1388
1389                         i2s1_sleep: i2s1-sleep {
1390                                 rockchip,pins =
1391                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1392                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1393                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1394                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1395                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1396                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1397                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1398                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1399                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1400                         };
1401                 };
1402
1403                 i2s2-0 {
1404                         i2s2m0_mclk: i2s2m0-mclk {
1405                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1406                         };
1407
1408                         i2s2m0_sclk: i2s2m0-sclk {
1409                                 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1410                         };
1411
1412                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1413                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1414                         };
1415
1416                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1417                                 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1418                         };
1419
1420                         i2s2m0_sdi: i2s2m0-sdi {
1421                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1422                         };
1423
1424                         i2s2m0_sdo: i2s2m0-sdo {
1425                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1426                         };
1427
1428                         i2s2m0_sleep: i2s2m0-sleep {
1429                                 rockchip,pins =
1430                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1431                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1432                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1433                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1434                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1435                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1436                         };
1437                 };
1438
1439                 i2s2-1 {
1440                         i2s2m1_mclk: i2s2m1-mclk {
1441                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1442                         };
1443
1444                         i2s2m1_sclk: i2s2m1-sclk {
1445                                 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1446                         };
1447
1448                         i2s2m1_lrckrx: i2sm1-lrckrx {
1449                                 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1450                         };
1451
1452                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1453                                 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1454                         };
1455
1456                         i2s2m1_sdi: i2s2m1-sdi {
1457                                 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1458                         };
1459
1460                         i2s2m1_sdo: i2s2m1-sdo {
1461                                 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1462                         };
1463
1464                         i2s2m1_sleep: i2s2m1-sleep {
1465                                 rockchip,pins =
1466                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1467                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1468                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1469                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1470                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1471                         };
1472                 };
1473
1474                 spdif-0 {
1475                         spdifm0_tx: spdifm0-tx {
1476                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1477                         };
1478                 };
1479
1480                 spdif-1 {
1481                         spdifm1_tx: spdifm1-tx {
1482                                 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1483                         };
1484                 };
1485
1486                 spdif-2 {
1487                         spdifm2_tx: spdifm2-tx {
1488                                 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1489                         };
1490                 };
1491
1492                 sdmmc0-0 {
1493                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1494                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1495                         };
1496
1497                         sdmmc0m0_pin: sdmmc0m0-pin {
1498                                 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1499                         };
1500                 };
1501
1502                 sdmmc0-1 {
1503                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1504                                 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1505                         };
1506
1507                         sdmmc0m1_pin: sdmmc0m1-pin {
1508                                 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1509                         };
1510                 };
1511
1512                 sdmmc0 {
1513                         sdmmc0_clk: sdmmc0-clk {
1514                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1515                         };
1516
1517                         sdmmc0_cmd: sdmmc0-cmd {
1518                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1519                         };
1520
1521                         sdmmc0_dectn: sdmmc0-dectn {
1522                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1523                         };
1524
1525                         sdmmc0_wrprt: sdmmc0-wrprt {
1526                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1527                         };
1528
1529                         sdmmc0_bus1: sdmmc0-bus1 {
1530                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1531                         };
1532
1533                         sdmmc0_bus4: sdmmc0-bus4 {
1534                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1535                                                 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1536                                                 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1537                                                 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1538                         };
1539
1540                         sdmmc0_pins: sdmmc0-pins {
1541                                 rockchip,pins =
1542                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1543                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1544                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1545                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1546                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1547                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1548                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1549                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1550                         };
1551                 };
1552
1553                 sdmmc0ext {
1554                         sdmmc0ext_clk: sdmmc0ext-clk {
1555                                 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1556                         };
1557
1558                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1559                                 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1560                         };
1561
1562                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1563                                 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1564                         };
1565
1566                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1567                                 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1568                         };
1569
1570                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1571                                 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1572                         };
1573
1574                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1575                                 rockchip,pins =
1576                                         <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1577                                         <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1578                                         <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1579                                         <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1580                         };
1581
1582                         sdmmc0ext_pins: sdmmc0ext-pins {
1583                                 rockchip,pins =
1584                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1585                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1586                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1587                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1588                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1589                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1590                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1591                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1592                         };
1593                 };
1594
1595                 sdmmc1 {
1596                         sdmmc1_clk: sdmmc1-clk {
1597                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1598                         };
1599
1600                         sdmmc1_cmd: sdmmc1-cmd {
1601                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1602                         };
1603
1604                         sdmmc1_pwren: sdmmc1-pwren {
1605                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1606                         };
1607
1608                         sdmmc1_wrprt: sdmmc1-wrprt {
1609                                 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1610                         };
1611
1612                         sdmmc1_dectn: sdmmc1-dectn {
1613                                 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1614                         };
1615
1616                         sdmmc1_bus1: sdmmc1-bus1 {
1617                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1618                         };
1619
1620                         sdmmc1_bus4: sdmmc1-bus4 {
1621                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1622                                                 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1623                                                 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1624                                                 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1625                         };
1626
1627                         sdmmc1_pins: sdmmc1-pins {
1628                                 rockchip,pins =
1629                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1630                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1631                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1632                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1633                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1634                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1635                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1636                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1637                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1638                         };
1639                 };
1640
1641                 emmc {
1642                         emmc_clk: emmc-clk {
1643                                 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1644                         };
1645
1646                         emmc_cmd: emmc-cmd {
1647                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1648                         };
1649
1650                         emmc_pwren: emmc-pwren {
1651                                 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1652                         };
1653
1654                         emmc_rstnout: emmc-rstnout {
1655                                 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1656                         };
1657
1658                         emmc_bus1: emmc-bus1 {
1659                                 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1660                         };
1661
1662                         emmc_bus4: emmc-bus4 {
1663                                 rockchip,pins =
1664                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1665                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1666                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1667                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1668                         };
1669
1670                         emmc_bus8: emmc-bus8 {
1671                                 rockchip,pins =
1672                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1673                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1674                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1675                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1676                                         <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1677                                         <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1678                                         <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1679                                         <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1680                         };
1681                 };
1682
1683                 pwm0 {
1684                         pwm0_pin: pwm0-pin {
1685                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1686                         };
1687                 };
1688
1689                 pwm1 {
1690                         pwm1_pin: pwm1-pin {
1691                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1692                         };
1693                 };
1694
1695                 pwm2 {
1696                         pwm2_pin: pwm2-pin {
1697                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1698                         };
1699                 };
1700
1701                 pwmir {
1702                         pwmir_pin: pwmir-pin {
1703                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1704                         };
1705                 };
1706
1707                 gmac-1 {
1708                         rgmiim1_pins: rgmiim1-pins {
1709                                 rockchip,pins =
1710                                         /* mac_txclk */
1711                                         <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1712                                         /* mac_rxclk */
1713                                         <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1714                                         /* mac_mdio */
1715                                         <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1716                                         /* mac_txen */
1717                                         <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1718                                         /* mac_clk */
1719                                         <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1720                                         /* mac_rxdv */
1721                                         <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1722                                         /* mac_mdc */
1723                                         <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1724                                         /* mac_rxd1 */
1725                                         <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1726                                         /* mac_rxd0 */
1727                                         <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1728                                         /* mac_txd1 */
1729                                         <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1730                                         /* mac_txd0 */
1731                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1732                                         /* mac_rxd3 */
1733                                         <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1734                                         /* mac_rxd2 */
1735                                         <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1736                                         /* mac_txd3 */
1737                                         <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1738                                         /* mac_txd2 */
1739                                         <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1740
1741                                         /* mac_txclk */
1742                                         <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1743                                         /* mac_txen */
1744                                         <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1745                                         /* mac_clk */
1746                                         <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1747                                         /* mac_txd1 */
1748                                         <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1749                                         /* mac_txd0 */
1750                                         <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1751                                         /* mac_txd3 */
1752                                         <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1753                                         /* mac_txd2 */
1754                                         <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1755                         };
1756
1757                         rmiim1_pins: rmiim1-pins {
1758                                 rockchip,pins =
1759                                         /* mac_mdio */
1760                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1761                                         /* mac_txen */
1762                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1763                                         /* mac_clk */
1764                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1765                                         /* mac_rxer */
1766                                         <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1767                                         /* mac_rxdv */
1768                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1769                                         /* mac_mdc */
1770                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1771                                         /* mac_rxd1 */
1772                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1773                                         /* mac_rxd0 */
1774                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1775                                         /* mac_txd1 */
1776                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1777                                         /* mac_txd0 */
1778                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1779
1780                                         /* mac_mdio */
1781                                         <0 RK_PB3 1 &pcfg_pull_none>,
1782                                         /* mac_txen */
1783                                         <0 RK_PB4 1 &pcfg_pull_none>,
1784                                         /* mac_clk */
1785                                         <0 RK_PD0 1 &pcfg_pull_none>,
1786                                         /* mac_mdc */
1787                                         <0 RK_PC3 1 &pcfg_pull_none>,
1788                                         /* mac_txd1 */
1789                                         <0 RK_PC0 1 &pcfg_pull_none>,
1790                                         /* mac_txd0 */
1791                                         <0 RK_PC1 1 &pcfg_pull_none>;
1792                         };
1793                 };
1794
1795                 gmac2phy {
1796                         fephyled_speed10: fephyled-speed10 {
1797                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1798                         };
1799
1800                         fephyled_duplex: fephyled-duplex {
1801                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1802                         };
1803
1804                         fephyled_rxm1: fephyled-rxm1 {
1805                                 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1806                         };
1807
1808                         fephyled_txm1: fephyled-txm1 {
1809                                 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1810                         };
1811
1812                         fephyled_linkm1: fephyled-linkm1 {
1813                                 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1814                         };
1815                 };
1816
1817                 tsadc_pin {
1818                         tsadc_int: tsadc-int {
1819                                 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1820                         };
1821                         tsadc_pin: tsadc-pin {
1822                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1823                         };
1824                 };
1825
1826                 hdmi_pin {
1827                         hdmi_cec: hdmi-cec {
1828                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1829                         };
1830
1831                         hdmi_hpd: hdmi-hpd {
1832                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1833                         };
1834                 };
1835
1836                 cif-0 {
1837                         dvp_d2d9_m0:dvp-d2d9-m0 {
1838                                 rockchip,pins =
1839                                         /* cif_d0 */
1840                                         <3 RK_PA4 2 &pcfg_pull_none>,
1841                                         /* cif_d1 */
1842                                         <3 RK_PA5 2 &pcfg_pull_none>,
1843                                         /* cif_d2 */
1844                                         <3 RK_PA6 2 &pcfg_pull_none>,
1845                                         /* cif_d3 */
1846                                         <3 RK_PA7 2 &pcfg_pull_none>,
1847                                         /* cif_d4 */
1848                                         <3 RK_PB0 2 &pcfg_pull_none>,
1849                                         /* cif_d5m0 */
1850                                         <3 RK_PB1 2 &pcfg_pull_none>,
1851                                         /* cif_d6m0 */
1852                                         <3 RK_PB2 2 &pcfg_pull_none>,
1853                                         /* cif_d7m0 */
1854                                         <3 RK_PB3 2 &pcfg_pull_none>,
1855                                         /* cif_href */
1856                                         <3 RK_PA1 2 &pcfg_pull_none>,
1857                                         /* cif_vsync */
1858                                         <3 RK_PA0 2 &pcfg_pull_none>,
1859                                         /* cif_clkoutm0 */
1860                                         <3 RK_PA3 2 &pcfg_pull_none>,
1861                                         /* cif_clkin */
1862                                         <3 RK_PA2 2 &pcfg_pull_none>;
1863                         };
1864                 };
1865
1866                 cif-1 {
1867                         dvp_d2d9_m1:dvp-d2d9-m1 {
1868                                 rockchip,pins =
1869                                         /* cif_d0 */
1870                                         <3 RK_PA4 2 &pcfg_pull_none>,
1871                                         /* cif_d1 */
1872                                         <3 RK_PA5 2 &pcfg_pull_none>,
1873                                         /* cif_d2 */
1874                                         <3 RK_PA6 2 &pcfg_pull_none>,
1875                                         /* cif_d3 */
1876                                         <3 RK_PA7 2 &pcfg_pull_none>,
1877                                         /* cif_d4 */
1878                                         <3 RK_PB0 2 &pcfg_pull_none>,
1879                                         /* cif_d5m1 */
1880                                         <2 RK_PC0 4 &pcfg_pull_none>,
1881                                         /* cif_d6m1 */
1882                                         <2 RK_PC1 4 &pcfg_pull_none>,
1883                                         /* cif_d7m1 */
1884                                         <2 RK_PC2 4 &pcfg_pull_none>,
1885                                         /* cif_href */
1886                                         <3 RK_PA1 2 &pcfg_pull_none>,
1887                                         /* cif_vsync */
1888                                         <3 RK_PA0 2 &pcfg_pull_none>,
1889                                         /* cif_clkoutm1 */
1890                                         <2 RK_PB7 4 &pcfg_pull_none>,
1891                                         /* cif_clkin */
1892                                         <3 RK_PA2 2 &pcfg_pull_none>;
1893                         };
1894                 };
1895         };
1896 };