arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Gru-Bob Rev 4+ board device tree source
   4  *
   5  * Copyright 2018 Google, Inc
   6  */
   7
   8 /dts-v1/;
   9 #include "rk3399-gru-chromebook.dtsi"
  10
  11 / {
  12         model = "Google Bob";
  13         compatible = "google,bob-rev13", "google,bob-rev12",
  14                      "google,bob-rev11", "google,bob-rev10",
  15                      "google,bob-rev9", "google,bob-rev8",
  16                      "google,bob-rev7", "google,bob-rev6",
  17                      "google,bob-rev5", "google,bob-rev4",
  18                      "google,bob", "google,gru", "rockchip,rk3399";
  19
  20         edp_panel: edp-panel {
  21                 compatible = "boe,nv101wxmn51";
  22                 backlight = <&backlight>;
  23                 power-supply = <&pp3300_disp>;
  24
  25                 port {
  26                         panel_in_edp: endpoint {
  27                                 remote-endpoint = <&edp_out_panel>;
  28                         };
  29                 };
  30         };
  31 };
  32
  33 &ap_i2c_ts {
  34         touchscreen: touchscreen@10 {
  35                 compatible = "elan,ekth3500";
  36                 reg = <0x10>;
  37                 interrupt-parent = <&gpio3>;
  38                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
  39                 pinctrl-names = "default";
  40                 pinctrl-0 = <&touch_int_l &touch_reset_l>;
  41                 reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
  42         };
  43 };
  44
  45 &ap_i2c_tp {
  46         trackpad: trackpad@15 {
  47                 compatible = "elan,ekth3000";
  48                 reg = <0x15>;
  49                 interrupt-parent = <&gpio1>;
  50                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  51                 pinctrl-names = "default";
  52                 pinctrl-0 = <&trackpad_int_l>;
  53                 wakeup-source;
  54         };
  55 };
  56
  57 &backlight {
  58         pwms = <&cros_ec_pwm 0>;
  59 };
  60
  61 &cpu_alert0 {
  62         temperature = <65000>;
  63 };
  64
  65 &cpu_alert1 {
  66         temperature = <70000>;
  67 };
  68
  69 &spi0 {
  70         status = "okay";
  71
  72         cr50@0 {
  73                 compatible = "google,cr50";
  74                 reg = <0>;
  75                 interrupt-parent = <&gpio0>;
  76                 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&h1_int_od_l>;
  79                 spi-max-frequency = <800000>;
  80         };
  81 };
  82
  83 &pinctrl {
  84         tpm {
  85                 h1_int_od_l: h1-int-od-l {
  86                         rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
  87                 };
  88         };
  89 };