1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
4 * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
8 #include <dt-bindings/input/linux-event-codes.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include "rk3399.dtsi"
11 #include "rk3399-opp.dtsi"
15 stdout-path = "serial2:1500000n8";
18 clkin_gmac: external-gmac-clock {
19 compatible = "fixed-clock";
20 clock-frequency = <125000000>;
21 clock-output-names = "clkin_gmac";
25 sdio_pwrseq: sdio-pwrseq {
26 compatible = "mmc-pwrseq-simple";
28 clock-names = "ext_clock";
29 pinctrl-names = "default";
30 pinctrl-0 = <&wifi_enable_h>;
31 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
35 compatible = "regulator-fixed";
36 regulator-name = "vcc12v_dcin";
39 regulator-min-microvolt = <12000000>;
40 regulator-max-microvolt = <12000000>;
44 compatible = "regulator-fixed";
45 regulator-name = "vcc5v0_sys";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 vin-supply = <&vcc12v_dcin>;
54 compatible = "regulator-fixed";
55 regulator-name = "vcc_0v9";
58 regulator-min-microvolt = <900000>;
59 regulator-max-microvolt = <900000>;
60 vin-supply = <&vcc3v3_sys>;
63 vcc3v3_pcie: vcc3v3-pcie-regulator {
64 compatible = "regulator-fixed";
66 gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pcie_pwr_en>;
69 regulator-name = "vcc3v3_pcie";
72 vin-supply = <&vcc5v0_sys>;
75 vcc3v3_sys: vcc3v3-sys {
76 compatible = "regulator-fixed";
77 regulator-name = "vcc3v3_sys";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
82 vin-supply = <&vcc5v0_sys>;
85 vcc5v0_host: vcc5v0-host-regulator {
86 compatible = "regulator-fixed";
88 gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&vcc5v0_host_en>;
91 regulator-name = "vcc5v0_host";
93 vin-supply = <&vcc5v0_sys>;
96 vcc5v0_typec: vcc5v0-typec-regulator {
97 compatible = "regulator-fixed";
99 gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&vcc5v0_typec_en>;
102 regulator-name = "vcc5v0_typec";
104 vin-supply = <&vcc5v0_sys>;
107 vcc_lan: vcc3v3-phy-regulator {
108 compatible = "regulator-fixed";
109 regulator-name = "vcc_lan";
112 regulator-min-microvolt = <3300000>;
113 regulator-max-microvolt = <3300000>;
117 compatible = "pwm-regulator";
118 pwms = <&pwm2 0 25000 1>;
119 regulator-name = "vdd_log";
122 regulator-min-microvolt = <800000>;
123 regulator-max-microvolt = <1400000>;
124 vin-supply = <&vcc5v0_sys>;
129 cpu-supply = <&vdd_cpu_l>;
133 cpu-supply = <&vdd_cpu_l>;
137 cpu-supply = <&vdd_cpu_l>;
141 cpu-supply = <&vdd_cpu_l>;
145 cpu-supply = <&vdd_cpu_b>;
149 cpu-supply = <&vdd_cpu_b>;
157 assigned-clocks = <&cru SCLK_RMII_SRC>;
158 assigned-clock-parents = <&clkin_gmac>;
159 clock_in_out = "input";
160 phy-supply = <&vcc_lan>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&rgmii_pins>;
164 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
165 snps,reset-active-low;
166 snps,reset-delays-us = <0 10000 50000>;
173 mali-supply = <&vdd_gpu>;
178 ddc-i2c-bus = <&i2c3>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&hdmi_cec>;
189 clock-frequency = <400000>;
190 i2c-scl-rising-time-ns = <168>;
191 i2c-scl-falling-time-ns = <4>;
195 compatible = "rockchip,rk808";
197 interrupt-parent = <&gpio1>;
198 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
200 clock-output-names = "xin32k", "rk808-clkout2";
201 pinctrl-names = "default";
202 pinctrl-0 = <&pmic_int_l>;
203 rockchip,system-power-controller;
206 vcc1-supply = <&vcc5v0_sys>;
207 vcc2-supply = <&vcc5v0_sys>;
208 vcc3-supply = <&vcc5v0_sys>;
209 vcc4-supply = <&vcc5v0_sys>;
210 vcc6-supply = <&vcc5v0_sys>;
211 vcc7-supply = <&vcc5v0_sys>;
212 vcc8-supply = <&vcc3v3_sys>;
213 vcc9-supply = <&vcc5v0_sys>;
214 vcc10-supply = <&vcc5v0_sys>;
215 vcc11-supply = <&vcc5v0_sys>;
216 vcc12-supply = <&vcc3v3_sys>;
217 vddio-supply = <&vcc_1v8>;
220 vdd_center: DCDC_REG1 {
221 regulator-name = "vdd_center";
224 regulator-min-microvolt = <750000>;
225 regulator-max-microvolt = <1350000>;
226 regulator-ramp-delay = <6001>;
227 regulator-state-mem {
228 regulator-off-in-suspend;
232 vdd_cpu_l: DCDC_REG2 {
233 regulator-name = "vdd_cpu_l";
236 regulator-min-microvolt = <750000>;
237 regulator-max-microvolt = <1350000>;
238 regulator-ramp-delay = <6001>;
239 regulator-state-mem {
240 regulator-off-in-suspend;
245 regulator-name = "vcc_ddr";
248 regulator-state-mem {
249 regulator-on-in-suspend;
254 regulator-name = "vcc_1v8";
257 regulator-min-microvolt = <1800000>;
258 regulator-max-microvolt = <1800000>;
259 regulator-state-mem {
260 regulator-on-in-suspend;
261 regulator-suspend-microvolt = <1800000>;
265 vcc1v8_codec: LDO_REG1 {
266 regulator-name = "vcc1v8_codec";
269 regulator-min-microvolt = <1800000>;
270 regulator-max-microvolt = <1800000>;
271 regulator-state-mem {
272 regulator-off-in-suspend;
276 vcc1v8_hdmi: LDO_REG2 {
277 regulator-name = "vcc1v8_hdmi";
280 regulator-min-microvolt = <1800000>;
281 regulator-max-microvolt = <1800000>;
282 regulator-state-mem {
283 regulator-off-in-suspend;
288 regulator-name = "vcca_1v8";
291 regulator-min-microvolt = <1800000>;
292 regulator-max-microvolt = <1800000>;
293 regulator-state-mem {
294 regulator-on-in-suspend;
295 regulator-suspend-microvolt = <1800000>;
300 regulator-name = "vcc_sdio";
303 regulator-min-microvolt = <3000000>;
304 regulator-max-microvolt = <3000000>;
305 regulator-state-mem {
306 regulator-on-in-suspend;
307 regulator-suspend-microvolt = <3000000>;
311 vcca3v0_codec: LDO_REG5 {
312 regulator-name = "vcca3v0_codec";
315 regulator-min-microvolt = <3000000>;
316 regulator-max-microvolt = <3000000>;
317 regulator-state-mem {
318 regulator-off-in-suspend;
323 regulator-name = "vcc_1v5";
326 regulator-min-microvolt = <1500000>;
327 regulator-max-microvolt = <1500000>;
328 regulator-state-mem {
329 regulator-on-in-suspend;
330 regulator-suspend-microvolt = <1500000>;
334 vcc0v9_hdmi: LDO_REG7 {
335 regulator-name = "vcc0v9_hdmi";
338 regulator-min-microvolt = <900000>;
339 regulator-max-microvolt = <900000>;
340 regulator-state-mem {
341 regulator-off-in-suspend;
346 regulator-name = "vcc_3v0";
349 regulator-min-microvolt = <3000000>;
350 regulator-max-microvolt = <3000000>;
351 regulator-state-mem {
352 regulator-on-in-suspend;
353 regulator-suspend-microvolt = <3000000>;
357 vcc_cam: SWITCH_REG1 {
358 regulator-name = "vcc_cam";
361 regulator-state-mem {
362 regulator-off-in-suspend;
366 vcc_mipi: SWITCH_REG2 {
367 regulator-name = "vcc_mipi";
370 regulator-state-mem {
371 regulator-off-in-suspend;
377 vdd_cpu_b: regulator@40 {
378 compatible = "silergy,syr827";
380 fcs,suspend-voltage-selector = <1>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&vsel1_pin>;
383 regulator-name = "vdd_cpu_b";
384 regulator-min-microvolt = <712500>;
385 regulator-max-microvolt = <1500000>;
386 regulator-ramp-delay = <1000>;
389 vin-supply = <&vcc5v0_sys>;
391 regulator-state-mem {
392 regulator-off-in-suspend;
396 vdd_gpu: regulator@41 {
397 compatible = "silergy,syr828";
399 fcs,suspend-voltage-selector = <1>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&vsel2_pin>;
402 regulator-name = "vdd_gpu";
403 regulator-min-microvolt = <712500>;
404 regulator-max-microvolt = <1500000>;
405 regulator-ramp-delay = <1000>;
408 vin-supply = <&vcc5v0_sys>;
410 regulator-state-mem {
411 regulator-off-in-suspend;
417 i2c-scl-rising-time-ns = <300>;
418 i2c-scl-falling-time-ns = <15>;
423 i2c-scl-rising-time-ns = <450>;
424 i2c-scl-falling-time-ns = <15>;
429 i2c-scl-rising-time-ns = <600>;
430 i2c-scl-falling-time-ns = <20>;
435 pinctrl-0 = <&i2s0_2ch_bus>;
436 rockchip,capture-channels = <2>;
437 rockchip,playback-channels = <2>;
442 rockchip,playback-channels = <2>;
443 rockchip,capture-channels = <2>;
454 bt656-supply = <&vcc_3v0>;
455 audio-supply = <&vcc_3v0>;
456 sdmmc-supply = <&vcc_sdio>;
457 gpio1830-supply = <&vcc_3v0>;
463 pmu1830-supply = <&vcc_3v0>;
471 ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
472 max-link-speed = <2>;
474 pinctrl-0 = <&pcie_clkreqnb_cpm>;
475 pinctrl-names = "default";
476 vpcie0v9-supply = <&vcc_0v9>;
477 vpcie1v8-supply = <&vcc_1v8>;
478 vpcie3v3-supply = <&vcc3v3_pcie>;
484 bt_enable_h: bt-enable-h {
485 rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
488 bt_host_wake_l: bt-host-wake-l {
489 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
492 bt_wake_l: bt-wake-l {
493 rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
498 pcie_pwr_en: pcie-pwr-en {
499 rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
504 sdio0_bus4: sdio0-bus4 {
505 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>,
506 <2 RK_PC5 1 &pcfg_pull_up_20ma>,
507 <2 RK_PC6 1 &pcfg_pull_up_20ma>,
508 <2 RK_PC7 1 &pcfg_pull_up_20ma>;
511 sdio0_cmd: sdio0-cmd {
512 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>;
515 sdio0_clk: sdio0-clk {
516 rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>;
521 pmic_int_l: pmic-int-l {
522 rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
525 vsel1_pin: vsel1-pin {
526 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
529 vsel2_pin: vsel2-pin {
530 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
535 vcc5v0_typec_en: vcc5v0-typec-en {
536 rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
541 vcc5v0_host_en: vcc5v0-host-en {
542 rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
547 wifi_enable_h: wifi-enable-h {
548 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
551 wifi_host_wake_l: wifi-host-wake-l {
552 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
564 vref-supply = <&vcc_1v8>;
568 #address-cells = <1>;
571 clock-frequency = <50000000>;
574 keep-power-in-suspend;
575 mmc-pwrseq = <&sdio_pwrseq>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
586 cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
588 max-frequency = <150000000>;
589 pinctrl-names = "default";
590 pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
597 mmc-hs400-enhanced-strobe;
613 /* tshut mode 0:CRU 1:GPIO */
614 rockchip,hw-tshut-mode = <1>;
615 /* tshut polarity 0:LOW 1:HIGH */
616 rockchip,hw-tshut-polarity = <1>;
622 u2phy0_otg: otg-port {
626 u2phy0_host: host-port {
627 phy-supply = <&vcc5v0_host>;
635 u2phy1_otg: otg-port {
639 u2phy1_host: host-port {
640 phy-supply = <&vcc5v0_host>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;