| blob | 15dcfc2598542b284f987a3006484673ff0b90ba |
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Device Tree Source for UniPhier LD11 SoC
4 //
5 // Copyright (C) 2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
11 / {
12 compatible = "socionext,uniphier-ld11";
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
17 cpus {
18 #address-cells = <2>;
19 #size-cells = <0>;
21 cpu-map {
22 cluster0 {
23 core0 {
24 cpu = <&cpu0>;
25 };
26 core1 {
27 cpu = <&cpu1>;
28 };
29 };
30 };
32 cpu0: cpu@0 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a53";
35 reg = <0 0x000>;
36 clocks = <&sys_clk 33>;
37 enable-method = "psci";
38 operating-points-v2 = <&cluster0_opp>;
39 };
41 cpu1: cpu@1 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a53";
44 reg = <0 0x001>;
45 clocks = <&sys_clk 33>;
46 enable-method = "psci";
47 operating-points-v2 = <&cluster0_opp>;
48 };
49 };
51 cluster0_opp: opp-table {
52 compatible = "operating-points-v2";
53 opp-shared;
55 opp-245000000 {
56 opp-hz = /bits/ 64 <245000000>;
57 clock-latency-ns = <300>;
58 };
59 opp-250000000 {
60 opp-hz = /bits/ 64 <250000000>;
61 clock-latency-ns = <300>;
62 };
63 opp-490000000 {
64 opp-hz = /bits/ 64 <490000000>;
65 clock-latency-ns = <300>;
66 };
67 opp-500000000 {
68 opp-hz = /bits/ 64 <500000000>;
69 clock-latency-ns = <300>;
70 };
71 opp-653334000 {
72 opp-hz = /bits/ 64 <653334000>;
73 clock-latency-ns = <300>;
74 };
75 opp-666667000 {
76 opp-hz = /bits/ 64 <666667000>;
77 clock-latency-ns = <300>;
78 };
79 opp-980000000 {
80 opp-hz = /bits/ 64 <980000000>;
81 clock-latency-ns = <300>;
82 };
83 };
85 psci {
86 compatible = "arm,psci-1.0";
87 method = "smc";
88 };
90 clocks {
91 refclk: ref {
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <25000000>;
95 };
96 };
98 emmc_pwrseq: emmc-pwrseq {
99 compatible = "mmc-pwrseq-emmc";
100 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
101 };
103 timer {
104 compatible = "arm,armv8-timer";
105 interrupts = <1 13 4>,
106 <1 14 4>,
107 <1 11 4>,
108 <1 10 4>;
109 };
111 reserved-memory {
112 #address-cells = <2>;
113 #size-cells = <2>;
114 ranges;
116 secure-memory@81000000 {
117 reg = <0x0 0x81000000 0x0 0x01000000>;
118 no-map;
119 };
120 };
122 soc@0 {
123 compatible = "simple-bus";
124 #address-cells = <1>;
125 #size-cells = <1>;
126 ranges = <0 0 0 0xffffffff>;
128 spi0: spi@54006000 {
129 compatible = "socionext,uniphier-scssi";
130 status = "disabled";
131 reg = <0x54006000 0x100>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 interrupts = <0 39 4>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_spi0>;
137 clocks = <&peri_clk 11>;
138 resets = <&peri_rst 11>;
139 };
141 spi1: spi@54006100 {
142 compatible = "socionext,uniphier-scssi";
143 status = "disabled";
144 reg = <0x54006100 0x100>;
145 #address-cells = <1>;
146 #size-cells = <0>;
147 interrupts = <0 216 4>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_spi1>;
150 clocks = <&peri_clk 12>;
151 resets = <&peri_rst 12>;
152 };
154 serial0: serial@54006800 {
155 compatible = "socionext,uniphier-uart";
156 status = "disabled";
157 reg = <0x54006800 0x40>;
158 interrupts = <0 33 4>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_uart0>;
161 clocks = <&peri_clk 0>;
162 resets = <&peri_rst 0>;
163 };
165 serial1: serial@54006900 {
166 compatible = "socionext,uniphier-uart";
167 status = "disabled";
168 reg = <0x54006900 0x40>;
169 interrupts = <0 35 4>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_uart1>;
172 clocks = <&peri_clk 1>;
173 resets = <&peri_rst 1>;
174 };
176 serial2: serial@54006a00 {
177 compatible = "socionext,uniphier-uart";
178 status = "disabled";
179 reg = <0x54006a00 0x40>;
180 interrupts = <0 37 4>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_uart2>;
183 clocks = <&peri_clk 2>;
184 resets = <&peri_rst 2>;
185 };
187 serial3: serial@54006b00 {
188 compatible = "socionext,uniphier-uart";
189 status = "disabled";
190 reg = <0x54006b00 0x40>;
191 interrupts = <0 177 4>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_uart3>;
194 clocks = <&peri_clk 3>;
195 resets = <&peri_rst 3>;
196 };
198 gpio: gpio@55000000 {
199 compatible = "socionext,uniphier-gpio";
200 reg = <0x55000000 0x200>;
201 interrupt-parent = <&aidet>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 gpio-ranges = <&pinctrl 0 0 0>,
207 <&pinctrl 43 0 0>,
208 <&pinctrl 51 0 0>,
209 <&pinctrl 96 0 0>,
210 <&pinctrl 160 0 0>,
211 <&pinctrl 184 0 0>;
212 gpio-ranges-group-names = "gpio_range0",
213 "gpio_range1",
214 "gpio_range2",
215 "gpio_range3",
216 "gpio_range4",
217 "gpio_range5";
218 ngpios = <200>;
219 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
220 <21 217 3>;
221 };
223 audio@56000000 {
224 compatible = "socionext,uniphier-ld11-aio";
225 reg = <0x56000000 0x80000>;
226 interrupts = <0 144 4>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_aout1>,
229 <&pinctrl_aoutiec1>;
230 clock-names = "aio";
231 clocks = <&sys_clk 40>;
232 reset-names = "aio";
233 resets = <&sys_rst 40>;
234 #sound-dai-cells = <1>;
235 socionext,syscon = <&soc_glue>;
237 i2s_port0: port@0 {
238 i2s_hdmi: endpoint {
239 };
240 };
242 i2s_port1: port@1 {
243 i2s_pcmin2: endpoint {
244 };
245 };
247 i2s_port2: port@2 {
248 i2s_line: endpoint {
249 dai-format = "i2s";
250 remote-endpoint = <&evea_line>;
251 };
252 };
254 i2s_port3: port@3 {
255 i2s_hpcmout1: endpoint {
256 };
257 };
259 i2s_port4: port@4 {
260 i2s_hp: endpoint {
261 dai-format = "i2s";
262 remote-endpoint = <&evea_hp>;
263 };
264 };
266 spdif_port0: port@5 {
267 spdif_hiecout1: endpoint {
268 };
269 };
271 src_port0: port@6 {
272 i2s_epcmout2: endpoint {
273 };
274 };
276 src_port1: port@7 {
277 i2s_epcmout3: endpoint {
278 };
279 };
281 comp_spdif_port0: port@8 {
282 comp_spdif_hiecout1: endpoint {
283 };
284 };
285 };
287 codec@57900000 {
288 compatible = "socionext,uniphier-evea";
289 reg = <0x57900000 0x1000>;
290 clock-names = "evea", "exiv";
291 clocks = <&sys_clk 41>, <&sys_clk 42>;
292 reset-names = "evea", "exiv", "adamv";
293 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
294 #sound-dai-cells = <1>;
296 port@0 {
297 evea_line: endpoint {
298 remote-endpoint = <&i2s_line>;
299 };
300 };
302 port@1 {
303 evea_hp: endpoint {
304 remote-endpoint = <&i2s_hp>;
305 };
306 };
307 };
309 adamv@57920000 {
310 compatible = "socionext,uniphier-ld11-adamv",
311 "simple-mfd", "syscon";
312 reg = <0x57920000 0x1000>;
314 adamv_rst: reset {
315 compatible = "socionext,uniphier-ld11-adamv-reset";
316 #reset-cells = <1>;
317 };
318 };
320 i2c0: i2c@58780000 {
321 compatible = "socionext,uniphier-fi2c";
322 status = "disabled";
323 reg = <0x58780000 0x80>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 interrupts = <0 41 4>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_i2c0>;
329 clocks = <&peri_clk 4>;
330 resets = <&peri_rst 4>;
331 clock-frequency = <100000>;
332 };
334 i2c1: i2c@58781000 {
335 compatible = "socionext,uniphier-fi2c";
336 status = "disabled";
337 reg = <0x58781000 0x80>;
338 #address-cells = <1>;
339 #size-cells = <0>;
340 interrupts = <0 42 4>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_i2c1>;
343 clocks = <&peri_clk 5>;
344 resets = <&peri_rst 5>;
345 clock-frequency = <100000>;
346 };
348 i2c2: i2c@58782000 {
349 compatible = "socionext,uniphier-fi2c";
350 reg = <0x58782000 0x80>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353 interrupts = <0 43 4>;
354 clocks = <&peri_clk 6>;
355 resets = <&peri_rst 6>;
356 clock-frequency = <400000>;
357 };
359 i2c3: i2c@58783000 {
360 compatible = "socionext,uniphier-fi2c";
361 status = "disabled";
362 reg = <0x58783000 0x80>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365 interrupts = <0 44 4>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_i2c3>;
368 clocks = <&peri_clk 7>;
369 resets = <&peri_rst 7>;
370 clock-frequency = <100000>;
371 };
373 i2c4: i2c@58784000 {
374 compatible = "socionext,uniphier-fi2c";
375 status = "disabled";
376 reg = <0x58784000 0x80>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379 interrupts = <0 45 4>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_i2c4>;
382 clocks = <&peri_clk 8>;
383 resets = <&peri_rst 8>;
384 clock-frequency = <100000>;
385 };
387 i2c5: i2c@58785000 {
388 compatible = "socionext,uniphier-fi2c";
389 reg = <0x58785000 0x80>;
390 #address-cells = <1>;
391 #size-cells = <0>;
392 interrupts = <0 25 4>;
393 clocks = <&peri_clk 9>;
394 resets = <&peri_rst 9>;
395 clock-frequency = <400000>;
396 };
398 system_bus: system-bus@58c00000 {
399 compatible = "socionext,uniphier-system-bus";
400 status = "disabled";
401 reg = <0x58c00000 0x400>;
402 #address-cells = <2>;
403 #size-cells = <1>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&pinctrl_system_bus>;
406 };
408 smpctrl@59801000 {
409 compatible = "socionext,uniphier-smpctrl";
410 reg = <0x59801000 0x400>;
411 };
413 sdctrl@59810000 {
414 compatible = "socionext,uniphier-ld11-sdctrl",
415 "simple-mfd", "syscon";
416 reg = <0x59810000 0x400>;
418 sd_rst: reset {
419 compatible = "socionext,uniphier-ld11-sd-reset";
420 #reset-cells = <1>;
421 };
422 };
424 perictrl@59820000 {
425 compatible = "socionext,uniphier-ld11-perictrl",
426 "simple-mfd", "syscon";
427 reg = <0x59820000 0x200>;
429 peri_clk: clock {
430 compatible = "socionext,uniphier-ld11-peri-clock";
431 #clock-cells = <1>;
432 };
434 peri_rst: reset {
435 compatible = "socionext,uniphier-ld11-peri-reset";
436 #reset-cells = <1>;
437 };
438 };
440 emmc: mmc@5a000000 {
441 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
442 reg = <0x5a000000 0x400>;
443 interrupts = <0 78 4>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_emmc>;
446 clocks = <&sys_clk 4>;
447 resets = <&sys_rst 4>;
448 bus-width = <8>;
449 mmc-ddr-1_8v;
450 mmc-hs200-1_8v;
451 mmc-pwrseq = <&emmc_pwrseq>;
452 cdns,phy-input-delay-legacy = <9>;
453 cdns,phy-input-delay-mmc-highspeed = <2>;
454 cdns,phy-input-delay-mmc-ddr = <3>;
455 cdns,phy-dll-delay-sdclk = <21>;
456 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
457 };
459 usb0: usb@5a800100 {
460 compatible = "socionext,uniphier-ehci", "generic-ehci";
461 status = "disabled";
462 reg = <0x5a800100 0x100>;
463 interrupts = <0 243 4>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&pinctrl_usb0>;
466 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
467 <&mio_clk 12>;
468 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
469 <&mio_rst 12>;
470 phy-names = "usb";
471 phys = <&usb_phy0>;
472 has-transaction-translator;
473 };
475 usb1: usb@5a810100 {
476 compatible = "socionext,uniphier-ehci", "generic-ehci";
477 status = "disabled";
478 reg = <0x5a810100 0x100>;
479 interrupts = <0 244 4>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_usb1>;
482 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
483 <&mio_clk 13>;
484 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
485 <&mio_rst 13>;
486 phy-names = "usb";
487 phys = <&usb_phy1>;
488 has-transaction-translator;
489 };
491 usb2: usb@5a820100 {
492 compatible = "socionext,uniphier-ehci", "generic-ehci";
493 status = "disabled";
494 reg = <0x5a820100 0x100>;
495 interrupts = <0 245 4>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_usb2>;
498 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
499 <&mio_clk 14>;
500 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
501 <&mio_rst 14>;
502 phy-names = "usb";
503 phys = <&usb_phy2>;
504 has-transaction-translator;
505 };
507 mioctrl@5b3e0000 {
508 compatible = "socionext,uniphier-ld11-mioctrl",
509 "simple-mfd", "syscon";
510 reg = <0x5b3e0000 0x800>;
512 mio_clk: clock {
513 compatible = "socionext,uniphier-ld11-mio-clock";
514 #clock-cells = <1>;
515 };
517 mio_rst: reset {
518 compatible = "socionext,uniphier-ld11-mio-reset";
519 #reset-cells = <1>;
520 resets = <&sys_rst 7>;
521 };
522 };
524 soc_glue: soc-glue@5f800000 {
525 compatible = "socionext,uniphier-ld11-soc-glue",
526 "simple-mfd", "syscon";
527 reg = <0x5f800000 0x2000>;
529 pinctrl: pinctrl {
530 compatible = "socionext,uniphier-ld11-pinctrl";
531 };
533 usb-phy {
534 compatible = "socionext,uniphier-ld11-usb2-phy";
535 #address-cells = <1>;
536 #size-cells = <0>;
538 usb_phy0: phy@0 {
539 reg = <0>;
540 #phy-cells = <0>;
541 };
543 usb_phy1: phy@1 {
544 reg = <1>;
545 #phy-cells = <0>;
546 };
548 usb_phy2: phy@2 {
549 reg = <2>;
550 #phy-cells = <0>;
551 };
552 };
553 };
555 soc-glue@5f900000 {
556 compatible = "socionext,uniphier-ld11-soc-glue-debug",
557 "simple-mfd";
558 #address-cells = <1>;
559 #size-cells = <1>;
560 ranges = <0 0x5f900000 0x2000>;
562 efuse@100 {
563 compatible = "socionext,uniphier-efuse";
564 reg = <0x100 0x28>;
565 };
567 efuse@200 {
568 compatible = "socionext,uniphier-efuse";
569 reg = <0x200 0x68>;
570 };
571 };
573 xdmac: dma-controller@5fc10000 {
574 compatible = "socionext,uniphier-xdmac";
575 reg = <0x5fc10000 0x5300>;
576 interrupts = <0 188 4>;
577 dma-channels = <16>;
578 #dma-cells = <2>;
579 };
581 aidet: interrupt-controller@5fc20000 {
582 compatible = "socionext,uniphier-ld11-aidet";
583 reg = <0x5fc20000 0x200>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
586 };
588 gic: interrupt-controller@5fe00000 {
589 compatible = "arm,gic-v3";
590 reg = <0x5fe00000 0x10000>, /* GICD */
591 <0x5fe40000 0x80000>; /* GICR */
592 interrupt-controller;
593 #interrupt-cells = <3>;
594 interrupts = <1 9 4>;
595 };
597 sysctrl@61840000 {
598 compatible = "socionext,uniphier-ld11-sysctrl",
599 "simple-mfd", "syscon";
600 reg = <0x61840000 0x10000>;
602 sys_clk: clock {
603 compatible = "socionext,uniphier-ld11-clock";
604 #clock-cells = <1>;
605 };
607 sys_rst: reset {
608 compatible = "socionext,uniphier-ld11-reset";
609 #reset-cells = <1>;
610 };
612 watchdog {
613 compatible = "socionext,uniphier-wdt";
614 };
615 };
617 eth: ethernet@65000000 {
618 compatible = "socionext,uniphier-ld11-ave4";
619 status = "disabled";
620 reg = <0x65000000 0x8500>;
621 interrupts = <0 66 4>;
622 clock-names = "ether";
623 clocks = <&sys_clk 6>;
624 reset-names = "ether";
625 resets = <&sys_rst 6>;
626 phy-mode = "internal";
627 local-mac-address = [00 00 00 00 00 00];
628 socionext,syscon-phy-mode = <&soc_glue 0>;
630 mdio: mdio {
631 #address-cells = <1>;
632 #size-cells = <0>;
633 };
634 };
636 nand: nand-controller@68000000 {
637 compatible = "socionext,uniphier-denali-nand-v5b";
638 status = "disabled";
639 reg-names = "nand_data", "denali_reg";
640 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 interrupts = <0 65 4>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_nand>;
646 clock-names = "nand", "nand_x", "ecc";
647 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
648 reset-names = "nand", "reg";
649 resets = <&sys_rst 2>, <&sys_rst 2>;
650 };
651 };
652 };
654 #include "uniphier-pinctrl.dtsi"
656 &pinctrl_aoutiec1 {
657 drive-strength = <4>; /* default: 4mA */
659 ao1arc {
660 pins = "AO1ARC";
661 drive-strength = <8>; /* 8mA */
662 };
663 };