arch/arm64/boot/dts/ti/k3-am654-base-board.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "k3-am654.dtsi"
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/net/ti-dp83867.h>
  11
  12 / {
  13         compatible =  "ti,am654-evm", "ti,am654";
  14         model = "Texas Instruments AM654 Base Board";
  15
  16         chosen {
  17                 stdout-path = "serial2:115200n8";
  18                 bootargs = "earlycon=ns16550a,mmio32,0x02800000";
  19         };
  20
  21         memory@80000000 {
  22                 device_type = "memory";
  23                 /* 4G RAM */
  24                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
  25                       <0x00000008 0x80000000 0x00000000 0x80000000>;
  26         };
  27
  28         reserved-memory {
  29                 #address-cells = <2>;
  30                 #size-cells = <2>;
  31                 ranges;
  32
  33                 secure_ddr: secure-ddr@9e800000 {
  34                         reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
  35                         alignment = <0x1000>;
  36                         no-map;
  37                 };
  38
  39                 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
  40                         compatible = "shared-dma-pool";
  41                         reg = <0 0xa0000000 0 0x100000>;
  42                         no-map;
  43                 };
  44
  45                 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
  46                         compatible = "shared-dma-pool";
  47                         reg = <0 0xa0100000 0 0xf00000>;
  48                         no-map;
  49                 };
  50
  51                 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
  52                         compatible = "shared-dma-pool";
  53                         reg = <0 0xa1000000 0 0x100000>;
  54                         no-map;
  55                 };
  56
  57                 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
  58                         compatible = "shared-dma-pool";
  59                         reg = <0 0xa1100000 0 0xf00000>;
  60                         no-map;
  61                 };
  62
  63                 rtos_ipc_memory_region: ipc-memories@a2000000 {
  64                         reg = <0x00 0xa2000000 0x00 0x00100000>;
  65                         alignment = <0x1000>;
  66                         no-map;
  67                 };
  68         };
  69
  70         gpio-keys {
  71                 compatible = "gpio-keys";
  72                 autorepeat;
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&push_button_pins_default>;
  75
  76                 sw5 {
  77                         label = "GPIO Key USER1";
  78                         linux,code = <BTN_0>;
  79                         gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
  80                 };
  81
  82                 sw6 {
  83                         label = "GPIO Key USER2";
  84                         linux,code = <BTN_1>;
  85                         gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
  86                 };
  87         };
  88
  89         clk_ov5640_fixed: clock {
  90                 compatible = "fixed-clock";
  91                 #clock-cells = <0>;
  92                 clock-frequency = <24000000>;
  93         };
  94 };
  95
  96 &wkup_pmx0 {
  97         wkup_i2c0_pins_default: wkup-i2c0-pins-default {
  98                 pinctrl-single,pins = <
  99                         AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
 100                         AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
 101                 >;
 102         };
 103
 104         push_button_pins_default: push-button-pins-default {
 105                 pinctrl-single,pins = <
 106                         AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
 107                         AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
 108                 >;
 109         };
 110
 111         mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
 112                 pinctrl-single,pins = <
 113                         AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
 114                         AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)   /* (U2) MCU_OSPI0_DQS */
 115                         AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* (U4) MCU_OSPI0_D0 */
 116                         AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* (U5) MCU_OSPI0_D1 */
 117                         AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* (T2) MCU_OSPI0_D2 */
 118                         AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* (T3) MCU_OSPI0_D3 */
 119                         AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* (T4) MCU_OSPI0_D4 */
 120                         AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* (T5) MCU_OSPI0_D5 */
 121                         AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* (R2) MCU_OSPI0_D6 */
 122                         AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* (R3) MCU_OSPI0_D7 */
 123                         AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
 124                 >;
 125         };
 126
 127         wkup_pca554_default: wkup-pca554-default {
 128                 pinctrl-single,pins = <
 129                         AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
 130                 >;
 131         };
 132
 133         mcu_cpsw_pins_default: mcu-cpsw-pins-default {
 134                 pinctrl-single,pins = <
 135                         AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
 136                         AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
 137                         AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
 138                         AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
 139                         AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
 140                         AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
 141                         AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
 142                         AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
 143                         AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
 144                         AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
 145                         AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
 146                         AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
 147                 >;
 148         };
 149
 150         mcu_mdio_pins_default: mcu-mdio1-pins-default {
 151                 pinctrl-single,pins = <
 152                         AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
 153                         AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
 154                 >;
 155         };
 156 };
 157
 158 &main_pmx0 {
 159         main_uart0_pins_default: main-uart0-pins-default {
 160                 pinctrl-single,pins = <
 161                         AM65X_IOPAD(0x01e4, PIN_INPUT, 0)       /* (AF11) UART0_RXD */
 162                         AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)      /* (AE11) UART0_TXD */
 163                         AM65X_IOPAD(0x01ec, PIN_INPUT, 0)       /* (AG11) UART0_CTSn */
 164                         AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)      /* (AD11) UART0_RTSn */
 165                 >;
 166         };
 167
 168         main_i2c2_pins_default: main-i2c2-pins-default {
 169                 pinctrl-single,pins = <
 170                         AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
 171                         AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
 172                 >;
 173         };
 174
 175         main_spi0_pins_default: main-spi0-pins-default {
 176                 pinctrl-single,pins = <
 177                         AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
 178                         AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
 179                         AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
 180                         AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
 181                 >;
 182         };
 183
 184         main_mmc0_pins_default: main-mmc0-pins-default {
 185                 pinctrl-single,pins = <
 186                         AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
 187                         AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
 188                         AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
 189                         AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
 190                         AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
 191                         AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
 192                         AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
 193                         AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
 194                         AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
 195                         AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
 196                         AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
 197                         AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
 198                 >;
 199         };
 200
 201         main_mmc1_pins_default: main-mmc1-pins-default {
 202                 pinctrl-single,pins = <
 203                         AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
 204                         AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
 205                         AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
 206                         AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
 207                         AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
 208                         AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
 209                         AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
 210                         AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
 211                 >;
 212         };
 213
 214         usb1_pins_default: usb1-pins-default {
 215                 pinctrl-single,pins = <
 216                         AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
 217                 >;
 218         };
 219 };
 220
 221 &main_pmx1 {
 222         main_i2c0_pins_default: main-i2c0-pins-default {
 223                 pinctrl-single,pins = <
 224                         AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
 225                         AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
 226                 >;
 227         };
 228
 229         main_i2c1_pins_default: main-i2c1-pins-default {
 230                 pinctrl-single,pins = <
 231                         AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
 232                         AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
 233                 >;
 234         };
 235
 236         ecap0_pins_default: ecap0-pins-default {
 237                 pinctrl-single,pins = <
 238                         AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
 239                 >;
 240         };
 241 };
 242
 243 &wkup_uart0 {
 244         /* Wakeup UART is used by System firmware */
 245         status = "reserved";
 246 };
 247
 248 &main_uart0 {
 249         pinctrl-names = "default";
 250         pinctrl-0 = <&main_uart0_pins_default>;
 251         power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
 252 };
 253
 254 &wkup_i2c0 {
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&wkup_i2c0_pins_default>;
 257         clock-frequency = <400000>;
 258
 259         pca9554: gpio@39 {
 260                 compatible = "nxp,pca9554";
 261                 reg = <0x39>;
 262                 gpio-controller;
 263                 #gpio-cells = <2>;
 264                 pinctrl-names = "default";
 265                 pinctrl-0 = <&wkup_pca554_default>;
 266                 interrupt-parent = <&wkup_gpio0>;
 267                 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
 268                 interrupt-controller;
 269                 #interrupt-cells = <2>;
 270         };
 271 };
 272
 273 &main_i2c0 {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&main_i2c0_pins_default>;
 276         clock-frequency = <400000>;
 277
 278         pca9555: gpio@21 {
 279                 compatible = "nxp,pca9555";
 280                 reg = <0x21>;
 281                 gpio-controller;
 282                 #gpio-cells = <2>;
 283         };
 284 };
 285
 286 &main_i2c1 {
 287         pinctrl-names = "default";
 288         pinctrl-0 = <&main_i2c1_pins_default>;
 289         clock-frequency = <400000>;
 290
 291         ov5640: camera@3c {
 292                 compatible = "ovti,ov5640";
 293                 reg = <0x3c>;
 294
 295                 clocks = <&clk_ov5640_fixed>;
 296                 clock-names = "xclk";
 297
 298                 port {
 299                         csi2_cam0: endpoint {
 300                                 remote-endpoint = <&csi2_phy0>;
 301                                 clock-lanes = <0>;
 302                                 data-lanes = <1 2>;
 303                         };
 304                 };
 305         };
 306
 307 };
 308
 309 &main_i2c2 {
 310         pinctrl-names = "default";
 311         pinctrl-0 = <&main_i2c2_pins_default>;
 312         clock-frequency = <400000>;
 313 };
 314
 315 &ecap0 {
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&ecap0_pins_default>;
 318 };
 319
 320 &main_spi0 {
 321         pinctrl-names = "default";
 322         pinctrl-0 = <&main_spi0_pins_default>;
 323         #address-cells = <1>;
 324         #size-cells= <0>;
 325         ti,pindir-d0-out-d1-in = <1>;
 326
 327         flash@0{
 328                 compatible = "jedec,spi-nor";
 329                 reg = <0x0>;
 330                 spi-tx-bus-width = <1>;
 331                 spi-rx-bus-width = <1>;
 332                 spi-max-frequency = <48000000>;
 333                 #address-cells = <1>;
 334                 #size-cells= <1>;
 335         };
 336 };
 337
 338 &sdhci0 {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&main_mmc0_pins_default>;
 341         bus-width = <8>;
 342         non-removable;
 343         ti,driver-strength-ohm = <50>;
 344         disable-wp;
 345 };
 346
 347 /*
 348  * Because of erratas i2025 and i2026 for silicon revision 1.0, the
 349  * SD card interface might fail. Boards with sr1.0 are recommended to
 350  * disable sdhci1
 351  */
 352 &sdhci1 {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&main_mmc1_pins_default>;
 355         ti,driver-strength-ohm = <50>;
 356         disable-wp;
 357 };
 358
 359 &usb1 {
 360         pinctrl-names = "default";
 361         pinctrl-0 = <&usb1_pins_default>;
 362         dr_mode = "otg";
 363 };
 364
 365 &dwc3_0 {
 366         status = "disabled";
 367 };
 368
 369 &usb0_phy {
 370         status = "disabled";
 371 };
 372
 373 &tscadc0 {
 374         adc {
 375                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 376         };
 377 };
 378
 379 &tscadc1 {
 380         adc {
 381                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 382         };
 383 };
 384
 385 &serdes0 {
 386         status = "disabled";
 387 };
 388
 389 &serdes1 {
 390         status = "disabled";
 391 };
 392
 393 &pcie0_rc {
 394         status = "disabled";
 395 };
 396
 397 &pcie0_ep {
 398         status = "disabled";
 399 };
 400
 401 &pcie1_rc {
 402         status = "disabled";
 403 };
 404
 405 &pcie1_ep {
 406         status = "disabled";
 407 };
 408
 409 &mailbox0_cluster0 {
 410         interrupts = <436>;
 411
 412         mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
 413                 ti,mbox-tx = <1 0 0>;
 414                 ti,mbox-rx = <0 0 0>;
 415         };
 416 };
 417
 418 &mailbox0_cluster1 {
 419         interrupts = <432>;
 420
 421         mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 422                 ti,mbox-tx = <1 0 0>;
 423                 ti,mbox-rx = <0 0 0>;
 424         };
 425 };
 426
 427 &mailbox0_cluster2 {
 428         status = "disabled";
 429 };
 430
 431 &mailbox0_cluster3 {
 432         status = "disabled";
 433 };
 434
 435 &mailbox0_cluster4 {
 436         status = "disabled";
 437 };
 438
 439 &mailbox0_cluster5 {
 440         status = "disabled";
 441 };
 442
 443 &mailbox0_cluster6 {
 444         status = "disabled";
 445 };
 446
 447 &mailbox0_cluster7 {
 448         status = "disabled";
 449 };
 450
 451 &mailbox0_cluster8 {
 452         status = "disabled";
 453 };
 454
 455 &mailbox0_cluster9 {
 456         status = "disabled";
 457 };
 458
 459 &mailbox0_cluster10 {
 460         status = "disabled";
 461 };
 462
 463 &mailbox0_cluster11 {
 464         status = "disabled";
 465 };
 466
 467 &mcu_r5fss0_core0 {
 468         memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 469                         <&mcu_r5fss0_core0_memory_region>;
 470         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
 471 };
 472
 473 &mcu_r5fss0_core1 {
 474         memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 475                         <&mcu_r5fss0_core1_memory_region>;
 476         mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
 477 };
 478
 479 &ospi0 {
 480         pinctrl-names = "default";
 481         pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
 482
 483         flash@0{
 484                 compatible = "jedec,spi-nor";
 485                 reg = <0x0>;
 486                 spi-tx-bus-width = <1>;
 487                 spi-rx-bus-width = <8>;
 488                 spi-max-frequency = <40000000>;
 489                 cdns,tshsl-ns = <60>;
 490                 cdns,tsd2d-ns = <60>;
 491                 cdns,tchsh-ns = <60>;
 492                 cdns,tslch-ns = <60>;
 493                 cdns,read-delay = <0>;
 494                 #address-cells = <1>;
 495                 #size-cells = <1>;
 496         };
 497 };
 498
 499 &csi2_0 {
 500         csi2_phy0: endpoint {
 501                 remote-endpoint = <&csi2_cam0>;
 502                 clock-lanes = <0>;
 503                 data-lanes = <1 2>;
 504         };
 505 };
 506
 507 &mcu_cpsw {
 508         pinctrl-names = "default";
 509         pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
 510 };
 511
 512 &davinci_mdio {
 513         phy0: ethernet-phy@0 {
 514                 reg = <0>;
 515                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 516                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 517         };
 518 };
 519
 520 &cpsw_port1 {
 521         phy-mode = "rgmii-rxid";
 522         phy-handle = <&phy0>;
 523 };
 524
 525 &mcasp0 {
 526         status = "disabled";
 527 };
 528
 529 &mcasp1 {
 530         status = "disabled";
 531 };
 532
 533 &mcasp2 {
 534         status = "disabled";
 535 };
 536
 537 &dss {
 538         status = "disabled";
 539 };