arch/arm64/boot/dts/toshiba/tmpv7708.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Source for the TMPV7708
   4  *
   5  * (C) Copyright 2018 - 2020, Toshiba Corporation.
   6  * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12
  13 /memreserve/ 0x81000000 0x00300000;     /* cpu-release-addr */
  14
  15 / {
  16         compatible = "toshiba,tmpv7708";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu-map {
  25                         cluster0 {
  26                                 core0 {
  27                                         cpu = <&cpu0>;
  28                                 };
  29                                 core1 {
  30                                         cpu = <&cpu1>;
  31                                 };
  32                                 core2 {
  33                                         cpu = <&cpu2>;
  34                                 };
  35                                 core3 {
  36                                         cpu = <&cpu3>;
  37                                 };
  38                         };
  39
  40                         cluster1 {
  41                                 core0 {
  42                                         cpu = <&cpu4>;
  43                                 };
  44                                 core1 {
  45                                         cpu = <&cpu5>;
  46                                 };
  47                                 core2 {
  48                                         cpu = <&cpu6>;
  49                                 };
  50                                 core3 {
  51                                         cpu = <&cpu7>;
  52                                 };
  53                         };
  54                 };
  55
  56                 cpu0: cpu@0 {
  57                         compatible = "arm,cortex-a53";
  58                         device_type = "cpu";
  59                         enable-method = "spin-table";
  60                         cpu-release-addr = <0x0 0x81100000>;
  61                         reg = <0x00>;
  62                 };
  63
  64                 cpu1: cpu@1 {
  65                         compatible = "arm,cortex-a53";
  66                         device_type = "cpu";
  67                         enable-method = "spin-table";
  68                         cpu-release-addr = <0x0 0x81100000>;
  69                         reg = <0x01>;
  70                 };
  71
  72                 cpu2: cpu@2 {
  73                         compatible = "arm,cortex-a53";
  74                         device_type = "cpu";
  75                         enable-method = "spin-table";
  76                         cpu-release-addr = <0x0 0x81100000>;
  77                         reg = <0x02>;
  78                 };
  79
  80                 cpu3: cpu@3 {
  81                         compatible = "arm,cortex-a53";
  82                         device_type = "cpu";
  83                         enable-method = "spin-table";
  84                         cpu-release-addr = <0x0 0x81100000>;
  85                         reg = <0x03>;
  86                 };
  87
  88                 cpu4: cpu@100 {
  89                         compatible = "arm,cortex-a53";
  90                         device_type = "cpu";
  91                         enable-method = "spin-table";
  92                         cpu-release-addr = <0x0 0x81100000>;
  93                         reg = <0x100>;
  94                 };
  95
  96                 cpu5: cpu@101 {
  97                         compatible = "arm,cortex-a53";
  98                         device_type = "cpu";
  99                         enable-method = "spin-table";
 100                         cpu-release-addr = <0x0 0x81100000>;
 101                         reg = <0x101>;
 102                 };
 103
 104                 cpu6: cpu@102 {
 105                         compatible = "arm,cortex-a53";
 106                         device_type = "cpu";
 107                         enable-method = "spin-table";
 108                         cpu-release-addr = <0x0 0x81100000>;
 109                         reg = <0x102>;
 110                 };
 111
 112                 cpu7: cpu@103 {
 113                         compatible = "arm,cortex-a53";
 114                         device_type = "cpu";
 115                         enable-method = "spin-table";
 116                         cpu-release-addr = <0x0 0x81100000>;
 117                         reg = <0x103>;
 118                 };
 119         };
 120
 121         timer {
 122                 compatible = "arm,armv8-timer";
 123                 interrupt-parent = <&gic>;
 124                 interrupts =
 125                         <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 126                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 127                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 128                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 129         };
 130
 131         uart_clk: uart-clk {
 132                 compatible = "fixed-clock";
 133                 clock-frequency = <150000000>;
 134                 #clock-cells = <0>;
 135         };
 136
 137         soc {
 138                 #address-cells = <2>;
 139                 #size-cells = <2>;
 140                 compatible = "simple-bus";
 141                 interrupt-parent = <&gic>;
 142                 ranges;
 143
 144                 gic: interrupt-controller@24001000 {
 145                         compatible = "arm,gic-400";
 146                         interrupt-controller;
 147                         #interrupt-cells = <3>;
 148                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 149                         reg = <0 0x24001000 0 0x1000>,
 150                               <0 0x24002000 0 0x2000>,
 151                               <0 0x24004000 0 0x2000>,
 152                               <0 0x24006000 0 0x2000>;
 153                 };
 154
 155                 pmux: pmux@24190000 {
 156                         compatible = "toshiba,tmpv7708-pinctrl";
 157                         reg = <0 0x24190000 0 0x10000>;
 158                 };
 159
 160                 uart0: serial@28200000 {
 161                         compatible = "arm,pl011", "arm,primecell";
 162                         reg = <0 0x28200000 0 0x1000>;
 163                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 164                         pinctrl-names = "default";
 165                         pinctrl-0 = <&uart0_pins>;
 166                         status = "disabled";
 167                 };
 168
 169                 uart1: serial@28201000 {
 170                         compatible = "arm,pl011", "arm,primecell";
 171                         reg = <0 0x28201000 0 0x1000>;
 172                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 173                         pinctrl-names = "default";
 174                         pinctrl-0 = <&uart1_pins>;
 175                         status = "disabled";
 176                 };
 177
 178                 uart2: serial@28202000 {
 179                         compatible = "arm,pl011", "arm,primecell";
 180                         reg = <0 0x28202000 0 0x1000>;
 181                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 182                         pinctrl-names = "default";
 183                         pinctrl-0 = <&uart2_pins>;
 184                         status = "disabled";
 185                 };
 186
 187                 uart3: serial@28203000 {
 188                         compatible = "arm,pl011", "arm,primecell";
 189                         reg = <0 0x28203000 0 0x1000>;
 190                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 191                         pinctrl-names = "default";
 192                         pinctrl-0 = <&uart3_pins>;
 193                         status = "disabled";
 194                 };
 195
 196                 i2c0: i2c@28030000 {
 197                         compatible = "snps,designware-i2c";
 198                         reg = <0 0x28030000 0 0x1000>;
 199                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 200                         pinctrl-names = "default";
 201                         pinctrl-0 = <&i2c0_pins>;
 202                         clock-frequency = <400000>;
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                         status = "disabled";
 206                 };
 207
 208                 i2c1: i2c@28031000 {
 209                         compatible = "snps,designware-i2c";
 210                         reg = <0 0x28031000 0 0x1000>;
 211                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 212                         pinctrl-names = "default";
 213                         pinctrl-0 = <&i2c1_pins>;
 214                         clock-frequency = <400000>;
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217                         status = "disabled";
 218                 };
 219
 220                 i2c2: i2c@28032000 {
 221                         compatible = "snps,designware-i2c";
 222                         reg = <0 0x28032000 0 0x1000>;
 223                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 224                         pinctrl-names = "default";
 225                         pinctrl-0 = <&i2c2_pins>;
 226                         clock-frequency = <400000>;
 227                         #address-cells = <1>;
 228                         #size-cells = <0>;
 229                         status = "disabled";
 230                 };
 231
 232                 i2c3: i2c@28033000 {
 233                         compatible = "snps,designware-i2c";
 234                         reg = <0 0x28033000 0 0x1000>;
 235                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 236                         pinctrl-names = "default";
 237                         pinctrl-0 = <&i2c3_pins>;
 238                         clock-frequency = <400000>;
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                         status = "disabled";
 242                 };
 243
 244                 i2c4: i2c@28034000 {
 245                         compatible = "snps,designware-i2c";
 246                         reg = <0 0x28034000 0 0x1000>;
 247                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 248                         pinctrl-names = "default";
 249                         pinctrl-0 = <&i2c4_pins>;
 250                         clock-frequency = <400000>;
 251                         #address-cells = <1>;
 252                         #size-cells = <0>;
 253                         status = "disabled";
 254                 };
 255
 256                 i2c5: i2c@28035000 {
 257                         compatible = "snps,designware-i2c";
 258                         reg = <0 0x28035000 0 0x1000>;
 259                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 260                         pinctrl-names = "default";
 261                         pinctrl-0 = <&i2c5_pins>;
 262                         clock-frequency = <400000>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         status = "disabled";
 266                 };
 267
 268                 i2c6: i2c@28036000 {
 269                         compatible = "snps,designware-i2c";
 270                         reg = <0 0x28036000 0 0x1000>;
 271                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 272                         pinctrl-names = "default";
 273                         pinctrl-0 = <&i2c6_pins>;
 274                         clock-frequency = <400000>;
 275                         #address-cells = <1>;
 276                         #size-cells = <0>;
 277                         status = "disabled";
 278                 };
 279
 280                 i2c7: i2c@28037000 {
 281                         compatible = "snps,designware-i2c";
 282                         reg = <0 0x28037000 0 0x1000>;
 283                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 284                         pinctrl-names = "default";
 285                         pinctrl-0 = <&i2c7_pins>;
 286                         clock-frequency = <400000>;
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         status = "disabled";
 290                 };
 291
 292                 i2c8: i2c@28038000 {
 293                         compatible = "snps,designware-i2c";
 294                         reg = <0 0x28038000 0 0x1000>;
 295                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 296                         pinctrl-names = "default";
 297                         pinctrl-0 = <&i2c8_pins>;
 298                         clock-frequency = <400000>;
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         status = "disabled";
 302                 };
 303
 304                 spi0: spi@28140000 {
 305                         compatible = "arm,pl022", "arm,primecell";
 306                         reg = <0 0x28140000 0 0x1000>;
 307                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 308                         pinctrl-names = "default";
 309                         pinctrl-0 = <&spi0_pins>;
 310                         num-cs = <1>;
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         status = "disabled";
 314                 };
 315
 316                 spi1: spi@28141000 {
 317                         compatible = "arm,pl022", "arm,primecell";
 318                         reg = <0 0x28141000 0 0x1000>;
 319                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 320                         pinctrl-names = "default";
 321                         pinctrl-0 = <&spi1_pins>;
 322                         num-cs = <1>;
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         status = "disabled";
 326                 };
 327
 328                 spi2: spi@28142000 {
 329                         compatible = "arm,pl022", "arm,primecell";
 330                         reg = <0 0x28142000 0 0x1000>;
 331                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 332                         pinctrl-names = "default";
 333                         pinctrl-0 = <&spi2_pins>;
 334                         num-cs = <1>;
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         status = "disabled";
 338                 };
 339
 340                 spi3: spi@28143000 {
 341                         compatible = "arm,pl022", "arm,primecell";
 342                         reg = <0 0x28143000 0 0x1000>;
 343                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 344                         pinctrl-names = "default";
 345                         pinctrl-0 = <&spi3_pins>;
 346                         num-cs = <1>;
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                         status = "disabled";
 350                 };
 351
 352                 spi4: spi@28144000 {
 353                         compatible = "arm,pl022", "arm,primecell";
 354                         reg = <0 0x28144000 0 0x1000>;
 355                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 356                         pinctrl-names = "default";
 357                         pinctrl-0 = <&spi4_pins>;
 358                         num-cs = <1>;
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         status = "disabled";
 362                 };
 363
 364                 spi5: spi@28145000 {
 365                         compatible = "arm,pl022", "arm,primecell";
 366                         reg = <0 0x28145000 0 0x1000>;
 367                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 368                         pinctrl-names = "default";
 369                         pinctrl-0 = <&spi5_pins>;
 370                         num-cs = <1>;
 371                         #address-cells = <1>;
 372                         #size-cells = <0>;
 373                         status = "disabled";
 374                 };
 375
 376                 spi6: spi@28146000 {
 377                         compatible = "arm,pl022", "arm,primecell";
 378                         reg = <0 0x28146000 0 0x1000>;
 379                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 380                         pinctrl-names = "default";
 381                         pinctrl-0 = <&spi6_pins>;
 382                         num-cs = <1>;
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         status = "disabled";
 386                 };
 387         };
 388 };
 389
 390 #include "tmpv7708_pins.dtsi"