WIP FPC-III support
[linux/fpc-iii.git] / arch / arm64 / boot / dts / xilinx / zynqmp-zcu102-revA.dts
blobf1255f635dfd7c898104d2d92c6c157681a7f19e
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * dts file for Xilinx ZynqMP ZCU102 RevA
4  *
5  * (C) Copyright 2015 - 2019, Xilinx, Inc.
6  *
7  * Michal Simek <michal.simek@xilinx.com>
8  */
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
17 / {
18         model = "ZynqMP ZCU102 RevA";
19         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
21         aliases {
22                 ethernet0 = &gem3;
23                 i2c0 = &i2c0;
24                 i2c1 = &i2c1;
25                 mmc0 = &sdhci1;
26                 rtc0 = &rtc;
27                 serial0 = &uart0;
28                 serial1 = &uart1;
29                 serial2 = &dcc;
30         };
32         chosen {
33                 bootargs = "earlycon";
34                 stdout-path = "serial0:115200n8";
35         };
37         memory@0 {
38                 device_type = "memory";
39                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
40         };
42         gpio-keys {
43                 compatible = "gpio-keys";
44                 autorepeat;
45                 sw19 {
46                         label = "sw19";
47                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
48                         linux,code = <KEY_DOWN>;
49                         wakeup-source;
50                         autorepeat;
51                 };
52         };
54         leds {
55                 compatible = "gpio-leds";
56                 heartbeat-led {
57                         label = "heartbeat";
58                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
59                         linux,default-trigger = "heartbeat";
60                 };
61         };
63         ina226-u76 {
64                 compatible = "iio-hwmon";
65                 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
66         };
67         ina226-u77 {
68                 compatible = "iio-hwmon";
69                 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
70         };
71         ina226-u78 {
72                 compatible = "iio-hwmon";
73                 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
74         };
75         ina226-u87 {
76                 compatible = "iio-hwmon";
77                 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
78         };
79         ina226-u85 {
80                 compatible = "iio-hwmon";
81                 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
82         };
83         ina226-u86 {
84                 compatible = "iio-hwmon";
85                 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
86         };
87         ina226-u93 {
88                 compatible = "iio-hwmon";
89                 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
90         };
91         ina226-u88 {
92                 compatible = "iio-hwmon";
93                 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
94         };
95         ina226-u15 {
96                 compatible = "iio-hwmon";
97                 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
98         };
99         ina226-u92 {
100                 compatible = "iio-hwmon";
101                 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
102         };
103         ina226-u79 {
104                 compatible = "iio-hwmon";
105                 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
106         };
107         ina226-u81 {
108                 compatible = "iio-hwmon";
109                 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
110         };
111         ina226-u80 {
112                 compatible = "iio-hwmon";
113                 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
114         };
115         ina226-u84 {
116                 compatible = "iio-hwmon";
117                 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
118         };
119         ina226-u16 {
120                 compatible = "iio-hwmon";
121                 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
122         };
123         ina226-u65 {
124                 compatible = "iio-hwmon";
125                 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
126         };
127         ina226-u74 {
128                 compatible = "iio-hwmon";
129                 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
130         };
131         ina226-u75 {
132                 compatible = "iio-hwmon";
133                 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
134         };
137 &can1 {
138         status = "okay";
141 &dcc {
142         status = "okay";
145 &fpd_dma_chan1 {
146         status = "okay";
149 &fpd_dma_chan2 {
150         status = "okay";
153 &fpd_dma_chan3 {
154         status = "okay";
157 &fpd_dma_chan4 {
158         status = "okay";
161 &fpd_dma_chan5 {
162         status = "okay";
165 &fpd_dma_chan6 {
166         status = "okay";
169 &fpd_dma_chan7 {
170         status = "okay";
173 &fpd_dma_chan8 {
174         status = "okay";
177 &gem3 {
178         status = "okay";
179         phy-handle = <&phy0>;
180         phy-mode = "rgmii-id";
181         phy0: ethernet-phy@21 {
182                 reg = <21>;
183                 ti,rx-internal-delay = <0x8>;
184                 ti,tx-internal-delay = <0xa>;
185                 ti,fifo-depth = <0x1>;
186                 ti,dp83867-rxctrl-strap-quirk;
187         };
190 &gpio {
191         status = "okay";
194 &i2c0 {
195         status = "okay";
196         clock-frequency = <400000>;
198         tca6416_u97: gpio@20 {
199                 compatible = "ti,tca6416";
200                 reg = <0x20>;
201                 gpio-controller; /* IRQ not connected */
202                 #gpio-cells = <2>;
203                 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
204                                 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
205                                 "", "", "", "", "", "", "", "", "";
206                 gtr-sel0-hog {
207                         gpio-hog;
208                         gpios = <0 0>;
209                         output-low; /* PCIE = 0, DP = 1 */
210                         line-name = "sel0";
211                 };
212                 gtr-sel1-hog {
213                         gpio-hog;
214                         gpios = <1 0>;
215                         output-high; /* PCIE = 0, DP = 1 */
216                         line-name = "sel1";
217                 };
218                 gtr-sel2-hog {
219                         gpio-hog;
220                         gpios = <2 0>;
221                         output-high; /* PCIE = 0, USB0 = 1 */
222                         line-name = "sel2";
223                 };
224                 gtr-sel3-hog {
225                         gpio-hog;
226                         gpios = <3 0>;
227                         output-high; /* PCIE = 0, SATA = 1 */
228                         line-name = "sel3";
229                 };
230         };
232         tca6416_u61: gpio@21 {
233                 compatible = "ti,tca6416";
234                 reg = <0x21>;
235                 gpio-controller; /* IRQ not connected */
236                 #gpio-cells = <2>;
237                 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
238                                 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
239                                 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
240                                 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
241         };
243         i2c-mux@75 { /* u60 */
244                 compatible = "nxp,pca9544";
245                 #address-cells = <1>;
246                 #size-cells = <0>;
247                 reg = <0x75>;
248                 i2c@0 {
249                         #address-cells = <1>;
250                         #size-cells = <0>;
251                         reg = <0>;
252                         /* PS_PMBUS */
253                         u76: ina226@40 { /* u76 */
254                                 compatible = "ti,ina226";
255                                 #io-channel-cells = <1>;
256                                 label = "ina226-u76";
257                                 reg = <0x40>;
258                                 shunt-resistor = <5000>;
259                         };
260                         u77: ina226@41 { /* u77 */
261                                 compatible = "ti,ina226";
262                                 #io-channel-cells = <1>;
263                                 label = "ina226-u77";
264                                 reg = <0x41>;
265                                 shunt-resistor = <5000>;
266                         };
267                         u78: ina226@42 { /* u78 */
268                                 compatible = "ti,ina226";
269                                 #io-channel-cells = <1>;
270                                 label = "ina226-u78";
271                                 reg = <0x42>;
272                                 shunt-resistor = <5000>;
273                         };
274                         u87: ina226@43 { /* u87 */
275                                 compatible = "ti,ina226";
276                                 #io-channel-cells = <1>;
277                                 label = "ina226-u87";
278                                 reg = <0x43>;
279                                 shunt-resistor = <5000>;
280                         };
281                         u85: ina226@44 { /* u85 */
282                                 compatible = "ti,ina226";
283                                 #io-channel-cells = <1>;
284                                 label = "ina226-u85";
285                                 reg = <0x44>;
286                                 shunt-resistor = <5000>;
287                         };
288                         u86: ina226@45 { /* u86 */
289                                 compatible = "ti,ina226";
290                                 #io-channel-cells = <1>;
291                                 label = "ina226-u86";
292                                 reg = <0x45>;
293                                 shunt-resistor = <5000>;
294                         };
295                         u93: ina226@46 { /* u93 */
296                                 compatible = "ti,ina226";
297                                 #io-channel-cells = <1>;
298                                 label = "ina226-u93";
299                                 reg = <0x46>;
300                                 shunt-resistor = <5000>;
301                         };
302                         u88: ina226@47 { /* u88 */
303                                 compatible = "ti,ina226";
304                                 #io-channel-cells = <1>;
305                                 label = "ina226-u88";
306                                 reg = <0x47>;
307                                 shunt-resistor = <5000>;
308                         };
309                         u15: ina226@4a { /* u15 */
310                                 compatible = "ti,ina226";
311                                 #io-channel-cells = <1>;
312                                 label = "ina226-u15";
313                                 reg = <0x4a>;
314                                 shunt-resistor = <5000>;
315                         };
316                         u92: ina226@4b { /* u92 */
317                                 compatible = "ti,ina226";
318                                 #io-channel-cells = <1>;
319                                 label = "ina226-u92";
320                                 reg = <0x4b>;
321                                 shunt-resistor = <5000>;
322                         };
323                 };
324                 i2c@1 {
325                         #address-cells = <1>;
326                         #size-cells = <0>;
327                         reg = <1>;
328                         /* PL_PMBUS */
329                         u79: ina226@40 { /* u79 */
330                                 compatible = "ti,ina226";
331                                 #io-channel-cells = <1>;
332                                 label = "ina226-u79";
333                                 reg = <0x40>;
334                                 shunt-resistor = <2000>;
335                         };
336                         u81: ina226@41 { /* u81 */
337                                 compatible = "ti,ina226";
338                                 #io-channel-cells = <1>;
339                                 label = "ina226-u81";
340                                 reg = <0x41>;
341                                 shunt-resistor = <5000>;
342                         };
343                         u80: ina226@42 { /* u80 */
344                                 compatible = "ti,ina226";
345                                 #io-channel-cells = <1>;
346                                 label = "ina226-u80";
347                                 reg = <0x42>;
348                                 shunt-resistor = <5000>;
349                         };
350                         u84: ina226@43 { /* u84 */
351                                 compatible = "ti,ina226";
352                                 #io-channel-cells = <1>;
353                                 label = "ina226-u84";
354                                 reg = <0x43>;
355                                 shunt-resistor = <5000>;
356                         };
357                         u16: ina226@44 { /* u16 */
358                                 compatible = "ti,ina226";
359                                 #io-channel-cells = <1>;
360                                 label = "ina226-u16";
361                                 reg = <0x44>;
362                                 shunt-resistor = <5000>;
363                         };
364                         u65: ina226@45 { /* u65 */
365                                 compatible = "ti,ina226";
366                                 #io-channel-cells = <1>;
367                                 label = "ina226-u65";
368                                 reg = <0x45>;
369                                 shunt-resistor = <5000>;
370                         };
371                         u74: ina226@46 { /* u74 */
372                                 compatible = "ti,ina226";
373                                 #io-channel-cells = <1>;
374                                 label = "ina226-u74";
375                                 reg = <0x46>;
376                                 shunt-resistor = <5000>;
377                         };
378                         u75: ina226@47 { /* u75 */
379                                 compatible = "ti,ina226";
380                                 #io-channel-cells = <1>;
381                                 label = "ina226-u75";
382                                 reg = <0x47>;
383                                 shunt-resistor = <5000>;
384                         };
385                 };
386                 i2c@2 {
387                         #address-cells = <1>;
388                         #size-cells = <0>;
389                         reg = <2>;
390                         /* MAXIM_PMBUS - 00 */
391                         max15301@a { /* u46 */
392                                 compatible = "maxim,max15301";
393                                 reg = <0xa>;
394                         };
395                         max15303@b { /* u4 */
396                                 compatible = "maxim,max15303";
397                                 reg = <0xb>;
398                         };
399                         max15303@10 { /* u13 */
400                                 compatible = "maxim,max15303";
401                                 reg = <0x10>;
402                         };
403                         max15301@13 { /* u47 */
404                                 compatible = "maxim,max15301";
405                                 reg = <0x13>;
406                         };
407                         max15303@14 { /* u7 */
408                                 compatible = "maxim,max15303";
409                                 reg = <0x14>;
410                         };
411                         max15303@15 { /* u6 */
412                                 compatible = "maxim,max15303";
413                                 reg = <0x15>;
414                         };
415                         max15303@16 { /* u10 */
416                                 compatible = "maxim,max15303";
417                                 reg = <0x16>;
418                         };
419                         max15303@17 { /* u9 */
420                                 compatible = "maxim,max15303";
421                                 reg = <0x17>;
422                         };
423                         max15301@18 { /* u63 */
424                                 compatible = "maxim,max15301";
425                                 reg = <0x18>;
426                         };
427                         max15303@1a { /* u49 */
428                                 compatible = "maxim,max15303";
429                                 reg = <0x1a>;
430                         };
431                         max15303@1d { /* u18 */
432                                 compatible = "maxim,max15303";
433                                 reg = <0x1d>;
434                         };
435                         max15303@20 { /* u8 */
436                                 compatible = "maxim,max15303";
437                                 status = "disabled"; /* unreachable */
438                                 reg = <0x20>;
439                         };
441                         max20751@72 { /* u95 */
442                                 compatible = "maxim,max20751";
443                                 reg = <0x72>;
444                         };
445                         max20751@73 { /* u96 */
446                                 compatible = "maxim,max20751";
447                                 reg = <0x73>;
448                         };
449                 };
450                 /* Bus 3 is not connected */
451         };
454 &i2c1 {
455         status = "okay";
456         clock-frequency = <400000>;
458         /* PL i2c via PCA9306 - u45 */
459         i2c-mux@74 { /* u34 */
460                 compatible = "nxp,pca9548";
461                 #address-cells = <1>;
462                 #size-cells = <0>;
463                 reg = <0x74>;
464                 i2c@0 {
465                         #address-cells = <1>;
466                         #size-cells = <0>;
467                         reg = <0>;
468                         /*
469                          * IIC_EEPROM 1kB memory which uses 256B blocks
470                          * where every block has different address.
471                          *    0 - 256B address 0x54
472                          * 256B - 512B address 0x55
473                          * 512B - 768B address 0x56
474                          * 768B - 1024B address 0x57
475                          */
476                         eeprom: eeprom@54 { /* u23 */
477                                 compatible = "atmel,24c08";
478                                 reg = <0x54>;
479                         };
480                 };
481                 i2c@1 {
482                         #address-cells = <1>;
483                         #size-cells = <0>;
484                         reg = <1>;
485                         si5341: clock-generator@36 { /* SI5341 - u69 */
486                                 reg = <0x36>;
487                         };
489                 };
490                 i2c@2 {
491                         #address-cells = <1>;
492                         #size-cells = <0>;
493                         reg = <2>;
494                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
495                                 #clock-cells = <0>;
496                                 compatible = "silabs,si570";
497                                 reg = <0x5d>;
498                                 temperature-stability = <50>;
499                                 factory-fout = <300000000>;
500                                 clock-frequency = <300000000>;
501                                 clock-output-names = "si570_user";
502                         };
503                 };
504                 i2c@3 {
505                         #address-cells = <1>;
506                         #size-cells = <0>;
507                         reg = <3>;
508                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
509                                 #clock-cells = <0>;
510                                 compatible = "silabs,si570";
511                                 reg = <0x5d>;
512                                 temperature-stability = <50>; /* copy from zc702 */
513                                 factory-fout = <156250000>;
514                                 clock-frequency = <148500000>;
515                                 clock-output-names = "si570_mgt";
516                         };
517                 };
518                 i2c@4 {
519                         #address-cells = <1>;
520                         #size-cells = <0>;
521                         reg = <4>;
522                         si5328: clock-generator@69 {/* SI5328 - u20 */
523                                 reg = <0x69>;
524                                 /*
525                                  * Chip has interrupt present connected to PL
526                                  * interrupt-parent = <&>;
527                                  * interrupts = <>;
528                                  */
529                         };
530                 };
531                 /* 5 - 7 unconnected */
532         };
534         i2c-mux@75 {
535                 compatible = "nxp,pca9548"; /* u135 */
536                 #address-cells = <1>;
537                 #size-cells = <0>;
538                 reg = <0x75>;
540                 i2c@0 {
541                         #address-cells = <1>;
542                         #size-cells = <0>;
543                         reg = <0>;
544                         /* HPC0_IIC */
545                 };
546                 i2c@1 {
547                         #address-cells = <1>;
548                         #size-cells = <0>;
549                         reg = <1>;
550                         /* HPC1_IIC */
551                 };
552                 i2c@2 {
553                         #address-cells = <1>;
554                         #size-cells = <0>;
555                         reg = <2>;
556                         /* SYSMON */
557                 };
558                 i2c@3 {
559                         #address-cells = <1>;
560                         #size-cells = <0>;
561                         reg = <3>;
562                         /* DDR4 SODIMM */
563                 };
564                 i2c@4 {
565                         #address-cells = <1>;
566                         #size-cells = <0>;
567                         reg = <4>;
568                         /* SEP 3 */
569                 };
570                 i2c@5 {
571                         #address-cells = <1>;
572                         #size-cells = <0>;
573                         reg = <5>;
574                         /* SEP 2 */
575                 };
576                 i2c@6 {
577                         #address-cells = <1>;
578                         #size-cells = <0>;
579                         reg = <6>;
580                         /* SEP 1 */
581                 };
582                 i2c@7 {
583                         #address-cells = <1>;
584                         #size-cells = <0>;
585                         reg = <7>;
586                         /* SEP 0 */
587                 };
588         };
591 &pcie {
592         status = "okay";
595 &rtc {
596         status = "okay";
599 &sata {
600         status = "okay";
601         /* SATA OOB timing settings */
602         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
603         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
604         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
605         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
606         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
607         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
608         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
609         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
612 /* SD1 with level shifter */
613 &sdhci1 {
614         status = "okay";
615         no-1-8-v;
618 &uart0 {
619         status = "okay";
622 &uart1 {
623         status = "okay";
626 /* ULPI SMSC USB3320 */
627 &usb0 {
628         status = "okay";
629         dr_mode = "host";
632 &watchdog0 {
633         status = "okay";