arch/arm64/include/asm/cache.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012 ARM Ltd.
   4  */
   5 #ifndef __ASM_CACHE_H
   6 #define __ASM_CACHE_H
   7
   8 #include <asm/cputype.h>
   9 #include <asm/mte-kasan.h>
  10
  11 #define CTR_L1IP_SHIFT          14
  12 #define CTR_L1IP_MASK           3
  13 #define CTR_DMINLINE_SHIFT      16
  14 #define CTR_IMINLINE_SHIFT      0
  15 #define CTR_IMINLINE_MASK       0xf
  16 #define CTR_ERG_SHIFT           20
  17 #define CTR_CWG_SHIFT           24
  18 #define CTR_CWG_MASK            15
  19 #define CTR_IDC_SHIFT           28
  20 #define CTR_DIC_SHIFT           29
  21
  22 #define CTR_CACHE_MINLINE_MASK  \
  23         (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
  24
  25 #define CTR_L1IP(ctr)           (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
  26
  27 #define ICACHE_POLICY_VPIPT     0
  28 #define ICACHE_POLICY_RESERVED  1
  29 #define ICACHE_POLICY_VIPT      2
  30 #define ICACHE_POLICY_PIPT      3
  31
  32 #define L1_CACHE_SHIFT          (6)
  33 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
  34
  35
  36 #define CLIDR_LOUU_SHIFT        27
  37 #define CLIDR_LOC_SHIFT         24
  38 #define CLIDR_LOUIS_SHIFT       21
  39
  40 #define CLIDR_LOUU(clidr)       (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
  41 #define CLIDR_LOC(clidr)        (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
  42 #define CLIDR_LOUIS(clidr)      (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
  43
  44 /*
  45  * Memory returned by kmalloc() may be used for DMA, so we must make
  46  * sure that all such allocations are cache aligned. Otherwise,
  47  * unrelated code may cause parts of the buffer to be read into the
  48  * cache before the transfer is done, causing old data to be seen by
  49  * the CPU.
  50  */
  51 #define ARCH_DMA_MINALIGN       (128)
  52
  53 #ifdef CONFIG_KASAN_SW_TAGS
  54 #define ARCH_SLAB_MINALIGN      (1ULL << KASAN_SHADOW_SCALE_SHIFT)
  55 #elif defined(CONFIG_KASAN_HW_TAGS)
  56 #define ARCH_SLAB_MINALIGN      MTE_GRANULE_SIZE
  57 #endif
  58
  59 #ifndef __ASSEMBLY__
  60
  61 #include <linux/bitops.h>
  62
  63 #define ICACHEF_ALIASING        0
  64 #define ICACHEF_VPIPT           1
  65 extern unsigned long __icache_flags;
  66
  67 /*
  68  * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
  69  * permitted in the I-cache.
  70  */
  71 static inline int icache_is_aliasing(void)
  72 {
  73         return test_bit(ICACHEF_ALIASING, &__icache_flags);
  74 }
  75
  76 static __always_inline int icache_is_vpipt(void)
  77 {
  78         return test_bit(ICACHEF_VPIPT, &__icache_flags);
  79 }
  80
  81 static inline u32 cache_type_cwg(void)
  82 {
  83         return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
  84 }
  85
  86 #define __read_mostly __section(".data..read_mostly")
  87
  88 static inline int cache_line_size_of_cpu(void)
  89 {
  90         u32 cwg = cache_type_cwg();
  91
  92         return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
  93 }
  94
  95 int cache_line_size(void);
  96
  97 /*
  98  * Read the effective value of CTR_EL0.
  99  *
 100  * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
 101  * section D10.2.33 "CTR_EL0, Cache Type Register" :
 102  *
 103  * CTR_EL0.IDC reports the data cache clean requirements for
 104  * instruction to data coherence.
 105  *
 106  *  0 - dcache clean to PoU is required unless :
 107  *     (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
 108  *  1 - dcache clean to PoU is not required for i-to-d coherence.
 109  *
 110  * This routine provides the CTR_EL0 with the IDC field updated to the
 111  * effective state.
 112  */
 113 static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
 114 {
 115         u32 ctr = read_cpuid_cachetype();
 116
 117         if (!(ctr & BIT(CTR_IDC_SHIFT))) {
 118                 u64 clidr = read_sysreg(clidr_el1);
 119
 120                 if (CLIDR_LOC(clidr) == 0 ||
 121                     (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
 122                         ctr |= BIT(CTR_IDC_SHIFT);
 123         }
 124
 125         return ctr;
 126 }
 127
 128 #endif  /* __ASSEMBLY__ */
 129
 130 #endif