arch/arm64/include/asm/insn.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2013 Huawei Ltd.
   4  * Author: Jiang Liu <liuj97@gmail.com>
   5  *
   6  * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
   7  */
   8 #ifndef __ASM_INSN_H
   9 #define __ASM_INSN_H
  10 #include <linux/build_bug.h>
  11 #include <linux/types.h>
  12
  13 #include <asm/alternative.h>
  14
  15 #ifndef __ASSEMBLY__
  16 /*
  17  * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
  18  * Section C3.1 "A64 instruction index by encoding":
  19  * AArch64 main encoding table
  20  *  Bit position
  21  *   28 27 26 25        Encoding Group
  22  *   0  0  -  -         Unallocated
  23  *   1  0  0  -         Data processing, immediate
  24  *   1  0  1  -         Branch, exception generation and system instructions
  25  *   -  1  -  0         Loads and stores
  26  *   -  1  0  1         Data processing - register
  27  *   0  1  1  1         Data processing - SIMD and floating point
  28  *   1  1  1  1         Data processing - SIMD and floating point
  29  * "-" means "don't care"
  30  */
  31 enum aarch64_insn_encoding_class {
  32         AARCH64_INSN_CLS_UNKNOWN,       /* UNALLOCATED */
  33         AARCH64_INSN_CLS_DP_IMM,        /* Data processing - immediate */
  34         AARCH64_INSN_CLS_DP_REG,        /* Data processing - register */
  35         AARCH64_INSN_CLS_DP_FPSIMD,     /* Data processing - SIMD and FP */
  36         AARCH64_INSN_CLS_LDST,          /* Loads and stores */
  37         AARCH64_INSN_CLS_BR_SYS,        /* Branch, exception generation and
  38                                          * system instructions */
  39 };
  40
  41 enum aarch64_insn_hint_cr_op {
  42         AARCH64_INSN_HINT_NOP   = 0x0 << 5,
  43         AARCH64_INSN_HINT_YIELD = 0x1 << 5,
  44         AARCH64_INSN_HINT_WFE   = 0x2 << 5,
  45         AARCH64_INSN_HINT_WFI   = 0x3 << 5,
  46         AARCH64_INSN_HINT_SEV   = 0x4 << 5,
  47         AARCH64_INSN_HINT_SEVL  = 0x5 << 5,
  48
  49         AARCH64_INSN_HINT_XPACLRI    = 0x07 << 5,
  50         AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
  51         AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
  52         AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
  53         AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5,
  54         AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
  55         AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
  56         AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
  57         AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
  58         AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
  59         AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,
  60         AARCH64_INSN_HINT_AUTIBZ     = 0x1E << 5,
  61         AARCH64_INSN_HINT_AUTIBSP    = 0x1F << 5,
  62
  63         AARCH64_INSN_HINT_ESB  = 0x10 << 5,
  64         AARCH64_INSN_HINT_PSB  = 0x11 << 5,
  65         AARCH64_INSN_HINT_TSB  = 0x12 << 5,
  66         AARCH64_INSN_HINT_CSDB = 0x14 << 5,
  67
  68         AARCH64_INSN_HINT_BTI   = 0x20 << 5,
  69         AARCH64_INSN_HINT_BTIC  = 0x22 << 5,
  70         AARCH64_INSN_HINT_BTIJ  = 0x24 << 5,
  71         AARCH64_INSN_HINT_BTIJC = 0x26 << 5,
  72 };
  73
  74 enum aarch64_insn_imm_type {
  75         AARCH64_INSN_IMM_ADR,
  76         AARCH64_INSN_IMM_26,
  77         AARCH64_INSN_IMM_19,
  78         AARCH64_INSN_IMM_16,
  79         AARCH64_INSN_IMM_14,
  80         AARCH64_INSN_IMM_12,
  81         AARCH64_INSN_IMM_9,
  82         AARCH64_INSN_IMM_7,
  83         AARCH64_INSN_IMM_6,
  84         AARCH64_INSN_IMM_S,
  85         AARCH64_INSN_IMM_R,
  86         AARCH64_INSN_IMM_N,
  87         AARCH64_INSN_IMM_MAX
  88 };
  89
  90 enum aarch64_insn_register_type {
  91         AARCH64_INSN_REGTYPE_RT,
  92         AARCH64_INSN_REGTYPE_RN,
  93         AARCH64_INSN_REGTYPE_RT2,
  94         AARCH64_INSN_REGTYPE_RM,
  95         AARCH64_INSN_REGTYPE_RD,
  96         AARCH64_INSN_REGTYPE_RA,
  97         AARCH64_INSN_REGTYPE_RS,
  98 };
  99
 100 enum aarch64_insn_register {
 101         AARCH64_INSN_REG_0  = 0,
 102         AARCH64_INSN_REG_1  = 1,
 103         AARCH64_INSN_REG_2  = 2,
 104         AARCH64_INSN_REG_3  = 3,
 105         AARCH64_INSN_REG_4  = 4,
 106         AARCH64_INSN_REG_5  = 5,
 107         AARCH64_INSN_REG_6  = 6,
 108         AARCH64_INSN_REG_7  = 7,
 109         AARCH64_INSN_REG_8  = 8,
 110         AARCH64_INSN_REG_9  = 9,
 111         AARCH64_INSN_REG_10 = 10,
 112         AARCH64_INSN_REG_11 = 11,
 113         AARCH64_INSN_REG_12 = 12,
 114         AARCH64_INSN_REG_13 = 13,
 115         AARCH64_INSN_REG_14 = 14,
 116         AARCH64_INSN_REG_15 = 15,
 117         AARCH64_INSN_REG_16 = 16,
 118         AARCH64_INSN_REG_17 = 17,
 119         AARCH64_INSN_REG_18 = 18,
 120         AARCH64_INSN_REG_19 = 19,
 121         AARCH64_INSN_REG_20 = 20,
 122         AARCH64_INSN_REG_21 = 21,
 123         AARCH64_INSN_REG_22 = 22,
 124         AARCH64_INSN_REG_23 = 23,
 125         AARCH64_INSN_REG_24 = 24,
 126         AARCH64_INSN_REG_25 = 25,
 127         AARCH64_INSN_REG_26 = 26,
 128         AARCH64_INSN_REG_27 = 27,
 129         AARCH64_INSN_REG_28 = 28,
 130         AARCH64_INSN_REG_29 = 29,
 131         AARCH64_INSN_REG_FP = 29, /* Frame pointer */
 132         AARCH64_INSN_REG_30 = 30,
 133         AARCH64_INSN_REG_LR = 30, /* Link register */
 134         AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
 135         AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
 136 };
 137
 138 enum aarch64_insn_special_register {
 139         AARCH64_INSN_SPCLREG_SPSR_EL1   = 0xC200,
 140         AARCH64_INSN_SPCLREG_ELR_EL1    = 0xC201,
 141         AARCH64_INSN_SPCLREG_SP_EL0     = 0xC208,
 142         AARCH64_INSN_SPCLREG_SPSEL      = 0xC210,
 143         AARCH64_INSN_SPCLREG_CURRENTEL  = 0xC212,
 144         AARCH64_INSN_SPCLREG_DAIF       = 0xDA11,
 145         AARCH64_INSN_SPCLREG_NZCV       = 0xDA10,
 146         AARCH64_INSN_SPCLREG_FPCR       = 0xDA20,
 147         AARCH64_INSN_SPCLREG_DSPSR_EL0  = 0xDA28,
 148         AARCH64_INSN_SPCLREG_DLR_EL0    = 0xDA29,
 149         AARCH64_INSN_SPCLREG_SPSR_EL2   = 0xE200,
 150         AARCH64_INSN_SPCLREG_ELR_EL2    = 0xE201,
 151         AARCH64_INSN_SPCLREG_SP_EL1     = 0xE208,
 152         AARCH64_INSN_SPCLREG_SPSR_INQ   = 0xE218,
 153         AARCH64_INSN_SPCLREG_SPSR_ABT   = 0xE219,
 154         AARCH64_INSN_SPCLREG_SPSR_UND   = 0xE21A,
 155         AARCH64_INSN_SPCLREG_SPSR_FIQ   = 0xE21B,
 156         AARCH64_INSN_SPCLREG_SPSR_EL3   = 0xF200,
 157         AARCH64_INSN_SPCLREG_ELR_EL3    = 0xF201,
 158         AARCH64_INSN_SPCLREG_SP_EL2     = 0xF210
 159 };
 160
 161 enum aarch64_insn_variant {
 162         AARCH64_INSN_VARIANT_32BIT,
 163         AARCH64_INSN_VARIANT_64BIT
 164 };
 165
 166 enum aarch64_insn_condition {
 167         AARCH64_INSN_COND_EQ = 0x0, /* == */
 168         AARCH64_INSN_COND_NE = 0x1, /* != */
 169         AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
 170         AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
 171         AARCH64_INSN_COND_MI = 0x4, /* < 0 */
 172         AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
 173         AARCH64_INSN_COND_VS = 0x6, /* overflow */
 174         AARCH64_INSN_COND_VC = 0x7, /* no overflow */
 175         AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
 176         AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
 177         AARCH64_INSN_COND_GE = 0xa, /* signed >= */
 178         AARCH64_INSN_COND_LT = 0xb, /* signed < */
 179         AARCH64_INSN_COND_GT = 0xc, /* signed > */
 180         AARCH64_INSN_COND_LE = 0xd, /* signed <= */
 181         AARCH64_INSN_COND_AL = 0xe, /* always */
 182 };
 183
 184 enum aarch64_insn_branch_type {
 185         AARCH64_INSN_BRANCH_NOLINK,
 186         AARCH64_INSN_BRANCH_LINK,
 187         AARCH64_INSN_BRANCH_RETURN,
 188         AARCH64_INSN_BRANCH_COMP_ZERO,
 189         AARCH64_INSN_BRANCH_COMP_NONZERO,
 190 };
 191
 192 enum aarch64_insn_size_type {
 193         AARCH64_INSN_SIZE_8,
 194         AARCH64_INSN_SIZE_16,
 195         AARCH64_INSN_SIZE_32,
 196         AARCH64_INSN_SIZE_64,
 197 };
 198
 199 enum aarch64_insn_ldst_type {
 200         AARCH64_INSN_LDST_LOAD_REG_OFFSET,
 201         AARCH64_INSN_LDST_STORE_REG_OFFSET,
 202         AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
 203         AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
 204         AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
 205         AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
 206         AARCH64_INSN_LDST_LOAD_EX,
 207         AARCH64_INSN_LDST_STORE_EX,
 208 };
 209
 210 enum aarch64_insn_adsb_type {
 211         AARCH64_INSN_ADSB_ADD,
 212         AARCH64_INSN_ADSB_SUB,
 213         AARCH64_INSN_ADSB_ADD_SETFLAGS,
 214         AARCH64_INSN_ADSB_SUB_SETFLAGS
 215 };
 216
 217 enum aarch64_insn_movewide_type {
 218         AARCH64_INSN_MOVEWIDE_ZERO,
 219         AARCH64_INSN_MOVEWIDE_KEEP,
 220         AARCH64_INSN_MOVEWIDE_INVERSE
 221 };
 222
 223 enum aarch64_insn_bitfield_type {
 224         AARCH64_INSN_BITFIELD_MOVE,
 225         AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
 226         AARCH64_INSN_BITFIELD_MOVE_SIGNED
 227 };
 228
 229 enum aarch64_insn_data1_type {
 230         AARCH64_INSN_DATA1_REVERSE_16,
 231         AARCH64_INSN_DATA1_REVERSE_32,
 232         AARCH64_INSN_DATA1_REVERSE_64,
 233 };
 234
 235 enum aarch64_insn_data2_type {
 236         AARCH64_INSN_DATA2_UDIV,
 237         AARCH64_INSN_DATA2_SDIV,
 238         AARCH64_INSN_DATA2_LSLV,
 239         AARCH64_INSN_DATA2_LSRV,
 240         AARCH64_INSN_DATA2_ASRV,
 241         AARCH64_INSN_DATA2_RORV,
 242 };
 243
 244 enum aarch64_insn_data3_type {
 245         AARCH64_INSN_DATA3_MADD,
 246         AARCH64_INSN_DATA3_MSUB,
 247 };
 248
 249 enum aarch64_insn_logic_type {
 250         AARCH64_INSN_LOGIC_AND,
 251         AARCH64_INSN_LOGIC_BIC,
 252         AARCH64_INSN_LOGIC_ORR,
 253         AARCH64_INSN_LOGIC_ORN,
 254         AARCH64_INSN_LOGIC_EOR,
 255         AARCH64_INSN_LOGIC_EON,
 256         AARCH64_INSN_LOGIC_AND_SETFLAGS,
 257         AARCH64_INSN_LOGIC_BIC_SETFLAGS
 258 };
 259
 260 enum aarch64_insn_prfm_type {
 261         AARCH64_INSN_PRFM_TYPE_PLD,
 262         AARCH64_INSN_PRFM_TYPE_PLI,
 263         AARCH64_INSN_PRFM_TYPE_PST,
 264 };
 265
 266 enum aarch64_insn_prfm_target {
 267         AARCH64_INSN_PRFM_TARGET_L1,
 268         AARCH64_INSN_PRFM_TARGET_L2,
 269         AARCH64_INSN_PRFM_TARGET_L3,
 270 };
 271
 272 enum aarch64_insn_prfm_policy {
 273         AARCH64_INSN_PRFM_POLICY_KEEP,
 274         AARCH64_INSN_PRFM_POLICY_STRM,
 275 };
 276
 277 enum aarch64_insn_adr_type {
 278         AARCH64_INSN_ADR_TYPE_ADRP,
 279         AARCH64_INSN_ADR_TYPE_ADR,
 280 };
 281
 282 #define __AARCH64_INSN_FUNCS(abbr, mask, val)                           \
 283 static __always_inline bool aarch64_insn_is_##abbr(u32 code)            \
 284 {                                                                       \
 285         BUILD_BUG_ON(~(mask) & (val));                                  \
 286         return (code & (mask)) == (val);                                \
 287 }                                                                       \
 288 static __always_inline u32 aarch64_insn_get_##abbr##_value(void)        \
 289 {                                                                       \
 290         return (val);                                                   \
 291 }
 292
 293 __AARCH64_INSN_FUNCS(adr,       0x9F000000, 0x10000000)
 294 __AARCH64_INSN_FUNCS(adrp,      0x9F000000, 0x90000000)
 295 __AARCH64_INSN_FUNCS(prfm,      0x3FC00000, 0x39800000)
 296 __AARCH64_INSN_FUNCS(prfm_lit,  0xFF000000, 0xD8000000)
 297 __AARCH64_INSN_FUNCS(str_reg,   0x3FE0EC00, 0x38206800)
 298 __AARCH64_INSN_FUNCS(ldadd,     0x3F20FC00, 0x38200000)
 299 __AARCH64_INSN_FUNCS(ldr_reg,   0x3FE0EC00, 0x38606800)
 300 __AARCH64_INSN_FUNCS(ldr_lit,   0xBF000000, 0x18000000)
 301 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
 302 __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
 303 __AARCH64_INSN_FUNCS(load_ex,   0x3F400000, 0x08400000)
 304 __AARCH64_INSN_FUNCS(store_ex,  0x3F400000, 0x08000000)
 305 __AARCH64_INSN_FUNCS(stp_post,  0x7FC00000, 0x28800000)
 306 __AARCH64_INSN_FUNCS(ldp_post,  0x7FC00000, 0x28C00000)
 307 __AARCH64_INSN_FUNCS(stp_pre,   0x7FC00000, 0x29800000)
 308 __AARCH64_INSN_FUNCS(ldp_pre,   0x7FC00000, 0x29C00000)
 309 __AARCH64_INSN_FUNCS(add_imm,   0x7F000000, 0x11000000)
 310 __AARCH64_INSN_FUNCS(adds_imm,  0x7F000000, 0x31000000)
 311 __AARCH64_INSN_FUNCS(sub_imm,   0x7F000000, 0x51000000)
 312 __AARCH64_INSN_FUNCS(subs_imm,  0x7F000000, 0x71000000)
 313 __AARCH64_INSN_FUNCS(movn,      0x7F800000, 0x12800000)
 314 __AARCH64_INSN_FUNCS(sbfm,      0x7F800000, 0x13000000)
 315 __AARCH64_INSN_FUNCS(bfm,       0x7F800000, 0x33000000)
 316 __AARCH64_INSN_FUNCS(movz,      0x7F800000, 0x52800000)
 317 __AARCH64_INSN_FUNCS(ubfm,      0x7F800000, 0x53000000)
 318 __AARCH64_INSN_FUNCS(movk,      0x7F800000, 0x72800000)
 319 __AARCH64_INSN_FUNCS(add,       0x7F200000, 0x0B000000)
 320 __AARCH64_INSN_FUNCS(adds,      0x7F200000, 0x2B000000)
 321 __AARCH64_INSN_FUNCS(sub,       0x7F200000, 0x4B000000)
 322 __AARCH64_INSN_FUNCS(subs,      0x7F200000, 0x6B000000)
 323 __AARCH64_INSN_FUNCS(madd,      0x7FE08000, 0x1B000000)
 324 __AARCH64_INSN_FUNCS(msub,      0x7FE08000, 0x1B008000)
 325 __AARCH64_INSN_FUNCS(udiv,      0x7FE0FC00, 0x1AC00800)
 326 __AARCH64_INSN_FUNCS(sdiv,      0x7FE0FC00, 0x1AC00C00)
 327 __AARCH64_INSN_FUNCS(lslv,      0x7FE0FC00, 0x1AC02000)
 328 __AARCH64_INSN_FUNCS(lsrv,      0x7FE0FC00, 0x1AC02400)
 329 __AARCH64_INSN_FUNCS(asrv,      0x7FE0FC00, 0x1AC02800)
 330 __AARCH64_INSN_FUNCS(rorv,      0x7FE0FC00, 0x1AC02C00)
 331 __AARCH64_INSN_FUNCS(rev16,     0x7FFFFC00, 0x5AC00400)
 332 __AARCH64_INSN_FUNCS(rev32,     0x7FFFFC00, 0x5AC00800)
 333 __AARCH64_INSN_FUNCS(rev64,     0x7FFFFC00, 0x5AC00C00)
 334 __AARCH64_INSN_FUNCS(and,       0x7F200000, 0x0A000000)
 335 __AARCH64_INSN_FUNCS(bic,       0x7F200000, 0x0A200000)
 336 __AARCH64_INSN_FUNCS(orr,       0x7F200000, 0x2A000000)
 337 __AARCH64_INSN_FUNCS(orn,       0x7F200000, 0x2A200000)
 338 __AARCH64_INSN_FUNCS(eor,       0x7F200000, 0x4A000000)
 339 __AARCH64_INSN_FUNCS(eon,       0x7F200000, 0x4A200000)
 340 __AARCH64_INSN_FUNCS(ands,      0x7F200000, 0x6A000000)
 341 __AARCH64_INSN_FUNCS(bics,      0x7F200000, 0x6A200000)
 342 __AARCH64_INSN_FUNCS(and_imm,   0x7F800000, 0x12000000)
 343 __AARCH64_INSN_FUNCS(orr_imm,   0x7F800000, 0x32000000)
 344 __AARCH64_INSN_FUNCS(eor_imm,   0x7F800000, 0x52000000)
 345 __AARCH64_INSN_FUNCS(ands_imm,  0x7F800000, 0x72000000)
 346 __AARCH64_INSN_FUNCS(extr,      0x7FA00000, 0x13800000)
 347 __AARCH64_INSN_FUNCS(b,         0xFC000000, 0x14000000)
 348 __AARCH64_INSN_FUNCS(bl,        0xFC000000, 0x94000000)
 349 __AARCH64_INSN_FUNCS(cbz,       0x7F000000, 0x34000000)
 350 __AARCH64_INSN_FUNCS(cbnz,      0x7F000000, 0x35000000)
 351 __AARCH64_INSN_FUNCS(tbz,       0x7F000000, 0x36000000)
 352 __AARCH64_INSN_FUNCS(tbnz,      0x7F000000, 0x37000000)
 353 __AARCH64_INSN_FUNCS(bcond,     0xFF000010, 0x54000000)
 354 __AARCH64_INSN_FUNCS(svc,       0xFFE0001F, 0xD4000001)
 355 __AARCH64_INSN_FUNCS(hvc,       0xFFE0001F, 0xD4000002)
 356 __AARCH64_INSN_FUNCS(smc,       0xFFE0001F, 0xD4000003)
 357 __AARCH64_INSN_FUNCS(brk,       0xFFE0001F, 0xD4200000)
 358 __AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
 359 __AARCH64_INSN_FUNCS(hint,      0xFFFFF01F, 0xD503201F)
 360 __AARCH64_INSN_FUNCS(br,        0xFFFFFC1F, 0xD61F0000)
 361 __AARCH64_INSN_FUNCS(br_auth,   0xFEFFF800, 0xD61F0800)
 362 __AARCH64_INSN_FUNCS(blr,       0xFFFFFC1F, 0xD63F0000)
 363 __AARCH64_INSN_FUNCS(blr_auth,  0xFEFFF800, 0xD63F0800)
 364 __AARCH64_INSN_FUNCS(ret,       0xFFFFFC1F, 0xD65F0000)
 365 __AARCH64_INSN_FUNCS(ret_auth,  0xFFFFFBFF, 0xD65F0BFF)
 366 __AARCH64_INSN_FUNCS(eret,      0xFFFFFFFF, 0xD69F03E0)
 367 __AARCH64_INSN_FUNCS(eret_auth, 0xFFFFFBFF, 0xD69F0BFF)
 368 __AARCH64_INSN_FUNCS(mrs,       0xFFF00000, 0xD5300000)
 369 __AARCH64_INSN_FUNCS(msr_imm,   0xFFF8F01F, 0xD500401F)
 370 __AARCH64_INSN_FUNCS(msr_reg,   0xFFF00000, 0xD5100000)
 371
 372 #undef  __AARCH64_INSN_FUNCS
 373
 374 bool aarch64_insn_is_steppable_hint(u32 insn);
 375 bool aarch64_insn_is_branch_imm(u32 insn);
 376
 377 static inline bool aarch64_insn_is_adr_adrp(u32 insn)
 378 {
 379         return aarch64_insn_is_adr(insn) || aarch64_insn_is_adrp(insn);
 380 }
 381
 382 int aarch64_insn_read(void *addr, u32 *insnp);
 383 int aarch64_insn_write(void *addr, u32 insn);
 384 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
 385 bool aarch64_insn_uses_literal(u32 insn);
 386 bool aarch64_insn_is_branch(u32 insn);
 387 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
 388 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
 389                                   u32 insn, u64 imm);
 390 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
 391                                          u32 insn);
 392 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
 393                                 enum aarch64_insn_branch_type type);
 394 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
 395                                      enum aarch64_insn_register reg,
 396                                      enum aarch64_insn_variant variant,
 397                                      enum aarch64_insn_branch_type type);
 398 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
 399                                      enum aarch64_insn_condition cond);
 400 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op);
 401 u32 aarch64_insn_gen_nop(void);
 402 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
 403                                 enum aarch64_insn_branch_type type);
 404 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
 405                                     enum aarch64_insn_register base,
 406                                     enum aarch64_insn_register offset,
 407                                     enum aarch64_insn_size_type size,
 408                                     enum aarch64_insn_ldst_type type);
 409 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
 410                                      enum aarch64_insn_register reg2,
 411                                      enum aarch64_insn_register base,
 412                                      int offset,
 413                                      enum aarch64_insn_variant variant,
 414                                      enum aarch64_insn_ldst_type type);
 415 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
 416                                    enum aarch64_insn_register base,
 417                                    enum aarch64_insn_register state,
 418                                    enum aarch64_insn_size_type size,
 419                                    enum aarch64_insn_ldst_type type);
 420 u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
 421                            enum aarch64_insn_register address,
 422                            enum aarch64_insn_register value,
 423                            enum aarch64_insn_size_type size);
 424 u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
 425                            enum aarch64_insn_register value,
 426                            enum aarch64_insn_size_type size);
 427 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
 428                                  enum aarch64_insn_register src,
 429                                  int imm, enum aarch64_insn_variant variant,
 430                                  enum aarch64_insn_adsb_type type);
 431 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
 432                          enum aarch64_insn_register reg,
 433                          enum aarch64_insn_adr_type type);
 434 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
 435                               enum aarch64_insn_register src,
 436                               int immr, int imms,
 437                               enum aarch64_insn_variant variant,
 438                               enum aarch64_insn_bitfield_type type);
 439 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
 440                               int imm, int shift,
 441                               enum aarch64_insn_variant variant,
 442                               enum aarch64_insn_movewide_type type);
 443 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
 444                                          enum aarch64_insn_register src,
 445                                          enum aarch64_insn_register reg,
 446                                          int shift,
 447                                          enum aarch64_insn_variant variant,
 448                                          enum aarch64_insn_adsb_type type);
 449 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
 450                            enum aarch64_insn_register src,
 451                            enum aarch64_insn_variant variant,
 452                            enum aarch64_insn_data1_type type);
 453 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
 454                            enum aarch64_insn_register src,
 455                            enum aarch64_insn_register reg,
 456                            enum aarch64_insn_variant variant,
 457                            enum aarch64_insn_data2_type type);
 458 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
 459                            enum aarch64_insn_register src,
 460                            enum aarch64_insn_register reg1,
 461                            enum aarch64_insn_register reg2,
 462                            enum aarch64_insn_variant variant,
 463                            enum aarch64_insn_data3_type type);
 464 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
 465                                          enum aarch64_insn_register src,
 466                                          enum aarch64_insn_register reg,
 467                                          int shift,
 468                                          enum aarch64_insn_variant variant,
 469                                          enum aarch64_insn_logic_type type);
 470 u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
 471                               enum aarch64_insn_register src,
 472                               enum aarch64_insn_variant variant);
 473 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
 474                                        enum aarch64_insn_variant variant,
 475                                        enum aarch64_insn_register Rn,
 476                                        enum aarch64_insn_register Rd,
 477                                        u64 imm);
 478 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
 479                           enum aarch64_insn_register Rm,
 480                           enum aarch64_insn_register Rn,
 481                           enum aarch64_insn_register Rd,
 482                           u8 lsb);
 483 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
 484                               enum aarch64_insn_prfm_type type,
 485                               enum aarch64_insn_prfm_target target,
 486                               enum aarch64_insn_prfm_policy policy);
 487 s32 aarch64_get_branch_offset(u32 insn);
 488 u32 aarch64_set_branch_offset(u32 insn, s32 offset);
 489
 490 int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
 491 int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
 492
 493 s32 aarch64_insn_adrp_get_offset(u32 insn);
 494 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
 495
 496 bool aarch32_insn_is_wide(u32 insn);
 497
 498 #define A32_RN_OFFSET   16
 499 #define A32_RT_OFFSET   12
 500 #define A32_RT2_OFFSET   0
 501
 502 u32 aarch64_insn_extract_system_reg(u32 insn);
 503 u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
 504 u32 aarch32_insn_mcr_extract_opc2(u32 insn);
 505 u32 aarch32_insn_mcr_extract_crm(u32 insn);
 506
 507 typedef bool (pstate_check_t)(unsigned long);
 508 extern pstate_check_t * const aarch32_opcode_cond_checks[16];
 509 #endif /* __ASSEMBLY__ */
 510
 511 #endif  /* __ASM_INSN_H */