arch/arm64/include/asm/pgtable.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012 ARM Ltd.
   4  */
   5 #ifndef __ASM_PGTABLE_H
   6 #define __ASM_PGTABLE_H
   7
   8 #include <asm/bug.h>
   9 #include <asm/proc-fns.h>
  10
  11 #include <asm/memory.h>
  12 #include <asm/mte.h>
  13 #include <asm/pgtable-hwdef.h>
  14 #include <asm/pgtable-prot.h>
  15 #include <asm/tlbflush.h>
  16
  17 /*
  18  * VMALLOC range.
  19  *
  20  * VMALLOC_START: beginning of the kernel vmalloc space
  21  * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space
  22  *      and fixed mappings
  23  */
  24 #define VMALLOC_START           (MODULES_END)
  25 #define VMALLOC_END             (VMEMMAP_START - SZ_256M)
  26
  27 #define vmemmap                 ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
  28
  29 #define FIRST_USER_ADDRESS      0UL
  30
  31 #ifndef __ASSEMBLY__
  32
  33 #include <asm/cmpxchg.h>
  34 #include <asm/fixmap.h>
  35 #include <linux/mmdebug.h>
  36 #include <linux/mm_types.h>
  37 #include <linux/sched.h>
  38
  39 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
  40 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
  41
  42 /* Set stride and tlb_level in flush_*_tlb_range */
  43 #define flush_pmd_tlb_range(vma, addr, end)     \
  44         __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
  45 #define flush_pud_tlb_range(vma, addr, end)     \
  46         __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
  47 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
  48
  49 /*
  50  * Outside of a few very special situations (e.g. hibernation), we always
  51  * use broadcast TLB invalidation instructions, therefore a spurious page
  52  * fault on one CPU which has been handled concurrently by another CPU
  53  * does not need to perform additional invalidation.
  54  */
  55 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0)
  56
  57 /*
  58  * ZERO_PAGE is a global shared page that is always zero: used
  59  * for zero-mapped memory areas etc..
  60  */
  61 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
  62 #define ZERO_PAGE(vaddr)        phys_to_page(__pa_symbol(empty_zero_page))
  63
  64 #define pte_ERROR(e)    \
  65         pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
  66
  67 /*
  68  * Macros to convert between a physical address and its placement in a
  69  * page table entry, taking care of 52-bit addresses.
  70  */
  71 #ifdef CONFIG_ARM64_PA_BITS_52
  72 #define __pte_to_phys(pte)      \
  73         ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
  74 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
  75 #else
  76 #define __pte_to_phys(pte)      (pte_val(pte) & PTE_ADDR_MASK)
  77 #define __phys_to_pte_val(phys) (phys)
  78 #endif
  79
  80 #define pte_pfn(pte)            (__pte_to_phys(pte) >> PAGE_SHIFT)
  81 #define pfn_pte(pfn,prot)       \
  82         __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
  83
  84 #define pte_none(pte)           (!pte_val(pte))
  85 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
  86 #define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
  87
  88 /*
  89  * The following only work if pte_present(). Undefined behaviour otherwise.
  90  */
  91 #define pte_present(pte)        (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
  92 #define pte_young(pte)          (!!(pte_val(pte) & PTE_AF))
  93 #define pte_special(pte)        (!!(pte_val(pte) & PTE_SPECIAL))
  94 #define pte_write(pte)          (!!(pte_val(pte) & PTE_WRITE))
  95 #define pte_user_exec(pte)      (!(pte_val(pte) & PTE_UXN))
  96 #define pte_cont(pte)           (!!(pte_val(pte) & PTE_CONT))
  97 #define pte_devmap(pte)         (!!(pte_val(pte) & PTE_DEVMAP))
  98 #define pte_tagged(pte)         ((pte_val(pte) & PTE_ATTRINDX_MASK) == \
  99                                  PTE_ATTRINDX(MT_NORMAL_TAGGED))
 100
 101 #define pte_cont_addr_end(addr, end)                                            \
 102 ({      unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK;    \
 103         (__boundary - 1 < (end) - 1) ? __boundary : (end);                      \
 104 })
 105
 106 #define pmd_cont_addr_end(addr, end)                                            \
 107 ({      unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK;    \
 108         (__boundary - 1 < (end) - 1) ? __boundary : (end);                      \
 109 })
 110
 111 #define pte_hw_dirty(pte)       (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
 112 #define pte_sw_dirty(pte)       (!!(pte_val(pte) & PTE_DIRTY))
 113 #define pte_dirty(pte)          (pte_sw_dirty(pte) || pte_hw_dirty(pte))
 114
 115 #define pte_valid(pte)          (!!(pte_val(pte) & PTE_VALID))
 116 #define pte_valid_not_user(pte) \
 117         ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
 118 #define pte_valid_user(pte) \
 119         ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
 120
 121 /*
 122  * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
 123  * so that we don't erroneously return false for pages that have been
 124  * remapped as PROT_NONE but are yet to be flushed from the TLB.
 125  * Note that we can't make any assumptions based on the state of the access
 126  * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
 127  * TLB.
 128  */
 129 #define pte_accessible(mm, pte) \
 130         (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
 131
 132 /*
 133  * p??_access_permitted() is true for valid user mappings (subject to the
 134  * write permission check). PROT_NONE mappings do not have the PTE_VALID bit
 135  * set.
 136  */
 137 #define pte_access_permitted(pte, write) \
 138         (pte_valid_user(pte) && (!(write) || pte_write(pte)))
 139 #define pmd_access_permitted(pmd, write) \
 140         (pte_access_permitted(pmd_pte(pmd), (write)))
 141 #define pud_access_permitted(pud, write) \
 142         (pte_access_permitted(pud_pte(pud), (write)))
 143
 144 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
 145 {
 146         pte_val(pte) &= ~pgprot_val(prot);
 147         return pte;
 148 }
 149
 150 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
 151 {
 152         pte_val(pte) |= pgprot_val(prot);
 153         return pte;
 154 }
 155
 156 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
 157 {
 158         pmd_val(pmd) &= ~pgprot_val(prot);
 159         return pmd;
 160 }
 161
 162 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
 163 {
 164         pmd_val(pmd) |= pgprot_val(prot);
 165         return pmd;
 166 }
 167
 168 static inline pte_t pte_mkwrite(pte_t pte)
 169 {
 170         pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
 171         pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
 172         return pte;
 173 }
 174
 175 static inline pte_t pte_mkclean(pte_t pte)
 176 {
 177         pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
 178         pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
 179
 180         return pte;
 181 }
 182
 183 static inline pte_t pte_mkdirty(pte_t pte)
 184 {
 185         pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
 186
 187         if (pte_write(pte))
 188                 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
 189
 190         return pte;
 191 }
 192
 193 static inline pte_t pte_wrprotect(pte_t pte)
 194 {
 195         /*
 196          * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
 197          * clear), set the PTE_DIRTY bit.
 198          */
 199         if (pte_hw_dirty(pte))
 200                 pte = pte_mkdirty(pte);
 201
 202         pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
 203         pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
 204         return pte;
 205 }
 206
 207 static inline pte_t pte_mkold(pte_t pte)
 208 {
 209         return clear_pte_bit(pte, __pgprot(PTE_AF));
 210 }
 211
 212 static inline pte_t pte_mkyoung(pte_t pte)
 213 {
 214         return set_pte_bit(pte, __pgprot(PTE_AF));
 215 }
 216
 217 static inline pte_t pte_mkspecial(pte_t pte)
 218 {
 219         return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
 220 }
 221
 222 static inline pte_t pte_mkcont(pte_t pte)
 223 {
 224         pte = set_pte_bit(pte, __pgprot(PTE_CONT));
 225         return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
 226 }
 227
 228 static inline pte_t pte_mknoncont(pte_t pte)
 229 {
 230         return clear_pte_bit(pte, __pgprot(PTE_CONT));
 231 }
 232
 233 static inline pte_t pte_mkpresent(pte_t pte)
 234 {
 235         return set_pte_bit(pte, __pgprot(PTE_VALID));
 236 }
 237
 238 static inline pmd_t pmd_mkcont(pmd_t pmd)
 239 {
 240         return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
 241 }
 242
 243 static inline pte_t pte_mkdevmap(pte_t pte)
 244 {
 245         return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
 246 }
 247
 248 static inline void set_pte(pte_t *ptep, pte_t pte)
 249 {
 250         WRITE_ONCE(*ptep, pte);
 251
 252         /*
 253          * Only if the new pte is valid and kernel, otherwise TLB maintenance
 254          * or update_mmu_cache() have the necessary barriers.
 255          */
 256         if (pte_valid_not_user(pte)) {
 257                 dsb(ishst);
 258                 isb();
 259         }
 260 }
 261
 262 extern void __sync_icache_dcache(pte_t pteval);
 263
 264 /*
 265  * PTE bits configuration in the presence of hardware Dirty Bit Management
 266  * (PTE_WRITE == PTE_DBM):
 267  *
 268  * Dirty  Writable | PTE_RDONLY  PTE_WRITE  PTE_DIRTY (sw)
 269  *   0      0      |   1           0          0
 270  *   0      1      |   1           1          0
 271  *   1      0      |   1           0          1
 272  *   1      1      |   0           1          x
 273  *
 274  * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
 275  * the page fault mechanism. Checking the dirty status of a pte becomes:
 276  *
 277  *   PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
 278  */
 279
 280 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
 281                                            pte_t pte)
 282 {
 283         pte_t old_pte;
 284
 285         if (!IS_ENABLED(CONFIG_DEBUG_VM))
 286                 return;
 287
 288         old_pte = READ_ONCE(*ptep);
 289
 290         if (!pte_valid(old_pte) || !pte_valid(pte))
 291                 return;
 292         if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
 293                 return;
 294
 295         /*
 296          * Check for potential race with hardware updates of the pte
 297          * (ptep_set_access_flags safely changes valid ptes without going
 298          * through an invalid entry).
 299          */
 300         VM_WARN_ONCE(!pte_young(pte),
 301                      "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
 302                      __func__, pte_val(old_pte), pte_val(pte));
 303         VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
 304                      "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
 305                      __func__, pte_val(old_pte), pte_val(pte));
 306 }
 307
 308 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 309                               pte_t *ptep, pte_t pte)
 310 {
 311         if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
 312                 __sync_icache_dcache(pte);
 313
 314         if (system_supports_mte() &&
 315             pte_present(pte) && pte_tagged(pte) && !pte_special(pte))
 316                 mte_sync_tags(ptep, pte);
 317
 318         __check_racy_pte_update(mm, ptep, pte);
 319
 320         set_pte(ptep, pte);
 321 }
 322
 323 /*
 324  * Huge pte definitions.
 325  */
 326 #define pte_mkhuge(pte)         (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
 327
 328 /*
 329  * Hugetlb definitions.
 330  */
 331 #define HUGE_MAX_HSTATE         4
 332 #define HPAGE_SHIFT             PMD_SHIFT
 333 #define HPAGE_SIZE              (_AC(1, UL) << HPAGE_SHIFT)
 334 #define HPAGE_MASK              (~(HPAGE_SIZE - 1))
 335 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
 336
 337 static inline pte_t pgd_pte(pgd_t pgd)
 338 {
 339         return __pte(pgd_val(pgd));
 340 }
 341
 342 static inline pte_t p4d_pte(p4d_t p4d)
 343 {
 344         return __pte(p4d_val(p4d));
 345 }
 346
 347 static inline pte_t pud_pte(pud_t pud)
 348 {
 349         return __pte(pud_val(pud));
 350 }
 351
 352 static inline pud_t pte_pud(pte_t pte)
 353 {
 354         return __pud(pte_val(pte));
 355 }
 356
 357 static inline pmd_t pud_pmd(pud_t pud)
 358 {
 359         return __pmd(pud_val(pud));
 360 }
 361
 362 static inline pte_t pmd_pte(pmd_t pmd)
 363 {
 364         return __pte(pmd_val(pmd));
 365 }
 366
 367 static inline pmd_t pte_pmd(pte_t pte)
 368 {
 369         return __pmd(pte_val(pte));
 370 }
 371
 372 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
 373 {
 374         return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
 375 }
 376
 377 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
 378 {
 379         return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
 380 }
 381
 382 #ifdef CONFIG_NUMA_BALANCING
 383 /*
 384  * See the comment in include/linux/pgtable.h
 385  */
 386 static inline int pte_protnone(pte_t pte)
 387 {
 388         return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
 389 }
 390
 391 static inline int pmd_protnone(pmd_t pmd)
 392 {
 393         return pte_protnone(pmd_pte(pmd));
 394 }
 395 #endif
 396
 397 #define pmd_present_invalid(pmd)     (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
 398
 399 static inline int pmd_present(pmd_t pmd)
 400 {
 401         return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
 402 }
 403
 404 /*
 405  * THP definitions.
 406  */
 407
 408 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 409 static inline int pmd_trans_huge(pmd_t pmd)
 410 {
 411         return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
 412 }
 413 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 414
 415 #define pmd_dirty(pmd)          pte_dirty(pmd_pte(pmd))
 416 #define pmd_young(pmd)          pte_young(pmd_pte(pmd))
 417 #define pmd_valid(pmd)          pte_valid(pmd_pte(pmd))
 418 #define pmd_cont(pmd)           pte_cont(pmd_pte(pmd))
 419 #define pmd_wrprotect(pmd)      pte_pmd(pte_wrprotect(pmd_pte(pmd)))
 420 #define pmd_mkold(pmd)          pte_pmd(pte_mkold(pmd_pte(pmd)))
 421 #define pmd_mkwrite(pmd)        pte_pmd(pte_mkwrite(pmd_pte(pmd)))
 422 #define pmd_mkclean(pmd)        pte_pmd(pte_mkclean(pmd_pte(pmd)))
 423 #define pmd_mkdirty(pmd)        pte_pmd(pte_mkdirty(pmd_pte(pmd)))
 424 #define pmd_mkyoung(pmd)        pte_pmd(pte_mkyoung(pmd_pte(pmd)))
 425
 426 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
 427 {
 428         pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
 429         pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
 430
 431         return pmd;
 432 }
 433
 434 #define pmd_thp_or_huge(pmd)    (pmd_huge(pmd) || pmd_trans_huge(pmd))
 435
 436 #define pmd_write(pmd)          pte_write(pmd_pte(pmd))
 437
 438 #define pmd_mkhuge(pmd)         (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
 439
 440 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 441 #define pmd_devmap(pmd)         pte_devmap(pmd_pte(pmd))
 442 #endif
 443 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
 444 {
 445         return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
 446 }
 447
 448 #define __pmd_to_phys(pmd)      __pte_to_phys(pmd_pte(pmd))
 449 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
 450 #define pmd_pfn(pmd)            ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
 451 #define pfn_pmd(pfn,prot)       __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
 452 #define mk_pmd(page,prot)       pfn_pmd(page_to_pfn(page),prot)
 453
 454 #define pud_young(pud)          pte_young(pud_pte(pud))
 455 #define pud_mkyoung(pud)        pte_pud(pte_mkyoung(pud_pte(pud)))
 456 #define pud_write(pud)          pte_write(pud_pte(pud))
 457
 458 #define pud_mkhuge(pud)         (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
 459
 460 #define __pud_to_phys(pud)      __pte_to_phys(pud_pte(pud))
 461 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
 462 #define pud_pfn(pud)            ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
 463 #define pfn_pud(pfn,prot)       __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
 464
 465 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
 466 #define set_pud_at(mm, addr, pudp, pud) set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud))
 467
 468 #define __p4d_to_phys(p4d)      __pte_to_phys(p4d_pte(p4d))
 469 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
 470
 471 #define __pgd_to_phys(pgd)      __pte_to_phys(pgd_pte(pgd))
 472 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
 473
 474 #define __pgprot_modify(prot,mask,bits) \
 475         __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
 476
 477 #define pgprot_nx(prot) \
 478         __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
 479
 480 /*
 481  * Mark the prot value as uncacheable and unbufferable.
 482  */
 483 #define pgprot_noncached(prot) \
 484         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
 485 #define pgprot_writecombine(prot) \
 486         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
 487 #define pgprot_device(prot) \
 488         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
 489 /*
 490  * DMA allocations for non-coherent devices use what the Arm architecture calls
 491  * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
 492  * and merging of writes.  This is different from "Device-nGnR[nE]" memory which
 493  * is intended for MMIO and thus forbids speculation, preserves access size,
 494  * requires strict alignment and can also force write responses to come from the
 495  * endpoint.
 496  */
 497 #define pgprot_dmacoherent(prot) \
 498         __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
 499                         PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
 500
 501 #define __HAVE_PHYS_MEM_ACCESS_PROT
 502 struct file;
 503 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 504                                      unsigned long size, pgprot_t vma_prot);
 505
 506 #define pmd_none(pmd)           (!pmd_val(pmd))
 507
 508 #define pmd_bad(pmd)            (!(pmd_val(pmd) & PMD_TABLE_BIT))
 509
 510 #define pmd_table(pmd)          ((pmd_val(pmd) & PMD_TYPE_MASK) == \
 511                                  PMD_TYPE_TABLE)
 512 #define pmd_sect(pmd)           ((pmd_val(pmd) & PMD_TYPE_MASK) == \
 513                                  PMD_TYPE_SECT)
 514 #define pmd_leaf(pmd)           pmd_sect(pmd)
 515
 516 #define pmd_leaf_size(pmd)      (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)
 517 #define pte_leaf_size(pte)      (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)
 518
 519 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
 520 static inline bool pud_sect(pud_t pud) { return false; }
 521 static inline bool pud_table(pud_t pud) { return true; }
 522 #else
 523 #define pud_sect(pud)           ((pud_val(pud) & PUD_TYPE_MASK) == \
 524                                  PUD_TYPE_SECT)
 525 #define pud_table(pud)          ((pud_val(pud) & PUD_TYPE_MASK) == \
 526                                  PUD_TYPE_TABLE)
 527 #endif
 528
 529 extern pgd_t init_pg_dir[PTRS_PER_PGD];
 530 extern pgd_t init_pg_end[];
 531 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 532 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
 533 extern pgd_t idmap_pg_end[];
 534 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
 535 extern pgd_t reserved_pg_dir[PTRS_PER_PGD];
 536
 537 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
 538
 539 static inline bool in_swapper_pgdir(void *addr)
 540 {
 541         return ((unsigned long)addr & PAGE_MASK) ==
 542                 ((unsigned long)swapper_pg_dir & PAGE_MASK);
 543 }
 544
 545 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
 546 {
 547 #ifdef __PAGETABLE_PMD_FOLDED
 548         if (in_swapper_pgdir(pmdp)) {
 549                 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
 550                 return;
 551         }
 552 #endif /* __PAGETABLE_PMD_FOLDED */
 553
 554         WRITE_ONCE(*pmdp, pmd);
 555
 556         if (pmd_valid(pmd)) {
 557                 dsb(ishst);
 558                 isb();
 559         }
 560 }
 561
 562 static inline void pmd_clear(pmd_t *pmdp)
 563 {
 564         set_pmd(pmdp, __pmd(0));
 565 }
 566
 567 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
 568 {
 569         return __pmd_to_phys(pmd);
 570 }
 571
 572 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
 573 {
 574         return (unsigned long)__va(pmd_page_paddr(pmd));
 575 }
 576
 577 /* Find an entry in the third-level page table. */
 578 #define pte_offset_phys(dir,addr)       (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
 579
 580 #define pte_set_fixmap(addr)            ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
 581 #define pte_set_fixmap_offset(pmd, addr)        pte_set_fixmap(pte_offset_phys(pmd, addr))
 582 #define pte_clear_fixmap()              clear_fixmap(FIX_PTE)
 583
 584 #define pmd_page(pmd)                   phys_to_page(__pmd_to_phys(pmd))
 585
 586 /* use ONLY for statically allocated translation tables */
 587 #define pte_offset_kimg(dir,addr)       ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
 588
 589 /*
 590  * Conversion functions: convert a page and protection to a page entry,
 591  * and a page entry and page directory to the page they refer to.
 592  */
 593 #define mk_pte(page,prot)       pfn_pte(page_to_pfn(page),prot)
 594
 595 #if CONFIG_PGTABLE_LEVELS > 2
 596
 597 #define pmd_ERROR(e)    \
 598         pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
 599
 600 #define pud_none(pud)           (!pud_val(pud))
 601 #define pud_bad(pud)            (!(pud_val(pud) & PUD_TABLE_BIT))
 602 #define pud_present(pud)        pte_present(pud_pte(pud))
 603 #define pud_leaf(pud)           pud_sect(pud)
 604 #define pud_valid(pud)          pte_valid(pud_pte(pud))
 605
 606 static inline void set_pud(pud_t *pudp, pud_t pud)
 607 {
 608 #ifdef __PAGETABLE_PUD_FOLDED
 609         if (in_swapper_pgdir(pudp)) {
 610                 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
 611                 return;
 612         }
 613 #endif /* __PAGETABLE_PUD_FOLDED */
 614
 615         WRITE_ONCE(*pudp, pud);
 616
 617         if (pud_valid(pud)) {
 618                 dsb(ishst);
 619                 isb();
 620         }
 621 }
 622
 623 static inline void pud_clear(pud_t *pudp)
 624 {
 625         set_pud(pudp, __pud(0));
 626 }
 627
 628 static inline phys_addr_t pud_page_paddr(pud_t pud)
 629 {
 630         return __pud_to_phys(pud);
 631 }
 632
 633 static inline unsigned long pud_page_vaddr(pud_t pud)
 634 {
 635         return (unsigned long)__va(pud_page_paddr(pud));
 636 }
 637
 638 /* Find an entry in the second-level page table. */
 639 #define pmd_offset_phys(dir, addr)      (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
 640
 641 #define pmd_set_fixmap(addr)            ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
 642 #define pmd_set_fixmap_offset(pud, addr)        pmd_set_fixmap(pmd_offset_phys(pud, addr))
 643 #define pmd_clear_fixmap()              clear_fixmap(FIX_PMD)
 644
 645 #define pud_page(pud)                   phys_to_page(__pud_to_phys(pud))
 646
 647 /* use ONLY for statically allocated translation tables */
 648 #define pmd_offset_kimg(dir,addr)       ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
 649
 650 #else
 651
 652 #define pud_page_paddr(pud)     ({ BUILD_BUG(); 0; })
 653
 654 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
 655 #define pmd_set_fixmap(addr)            NULL
 656 #define pmd_set_fixmap_offset(pudp, addr)       ((pmd_t *)pudp)
 657 #define pmd_clear_fixmap()
 658
 659 #define pmd_offset_kimg(dir,addr)       ((pmd_t *)dir)
 660
 661 #endif  /* CONFIG_PGTABLE_LEVELS > 2 */
 662
 663 #if CONFIG_PGTABLE_LEVELS > 3
 664
 665 #define pud_ERROR(e)    \
 666         pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
 667
 668 #define p4d_none(p4d)           (!p4d_val(p4d))
 669 #define p4d_bad(p4d)            (!(p4d_val(p4d) & 2))
 670 #define p4d_present(p4d)        (p4d_val(p4d))
 671
 672 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
 673 {
 674         if (in_swapper_pgdir(p4dp)) {
 675                 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
 676                 return;
 677         }
 678
 679         WRITE_ONCE(*p4dp, p4d);
 680         dsb(ishst);
 681         isb();
 682 }
 683
 684 static inline void p4d_clear(p4d_t *p4dp)
 685 {
 686         set_p4d(p4dp, __p4d(0));
 687 }
 688
 689 static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
 690 {
 691         return __p4d_to_phys(p4d);
 692 }
 693
 694 static inline unsigned long p4d_page_vaddr(p4d_t p4d)
 695 {
 696         return (unsigned long)__va(p4d_page_paddr(p4d));
 697 }
 698
 699 /* Find an entry in the frst-level page table. */
 700 #define pud_offset_phys(dir, addr)      (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
 701
 702 #define pud_set_fixmap(addr)            ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
 703 #define pud_set_fixmap_offset(p4d, addr)        pud_set_fixmap(pud_offset_phys(p4d, addr))
 704 #define pud_clear_fixmap()              clear_fixmap(FIX_PUD)
 705
 706 #define p4d_page(p4d)           pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
 707
 708 /* use ONLY for statically allocated translation tables */
 709 #define pud_offset_kimg(dir,addr)       ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
 710
 711 #else
 712
 713 #define p4d_page_paddr(p4d)     ({ BUILD_BUG(); 0;})
 714 #define pgd_page_paddr(pgd)     ({ BUILD_BUG(); 0;})
 715
 716 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
 717 #define pud_set_fixmap(addr)            NULL
 718 #define pud_set_fixmap_offset(pgdp, addr)       ((pud_t *)pgdp)
 719 #define pud_clear_fixmap()
 720
 721 #define pud_offset_kimg(dir,addr)       ((pud_t *)dir)
 722
 723 #endif  /* CONFIG_PGTABLE_LEVELS > 3 */
 724
 725 #define pgd_ERROR(e)    \
 726         pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
 727
 728 #define pgd_set_fixmap(addr)    ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
 729 #define pgd_clear_fixmap()      clear_fixmap(FIX_PGD)
 730
 731 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 732 {
 733         /*
 734          * Normal and Normal-Tagged are two different memory types and indices
 735          * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
 736          */
 737         const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
 738                               PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
 739                               PTE_ATTRINDX_MASK;
 740         /* preserve the hardware dirty information */
 741         if (pte_hw_dirty(pte))
 742                 pte = pte_mkdirty(pte);
 743         pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
 744         return pte;
 745 }
 746
 747 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
 748 {
 749         return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
 750 }
 751
 752 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 753 extern int ptep_set_access_flags(struct vm_area_struct *vma,
 754                                  unsigned long address, pte_t *ptep,
 755                                  pte_t entry, int dirty);
 756
 757 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 758 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
 759 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
 760                                         unsigned long address, pmd_t *pmdp,
 761                                         pmd_t entry, int dirty)
 762 {
 763         return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
 764 }
 765
 766 static inline int pud_devmap(pud_t pud)
 767 {
 768         return 0;
 769 }
 770
 771 static inline int pgd_devmap(pgd_t pgd)
 772 {
 773         return 0;
 774 }
 775 #endif
 776
 777 /*
 778  * Atomic pte/pmd modifications.
 779  */
 780 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 781 static inline int __ptep_test_and_clear_young(pte_t *ptep)
 782 {
 783         pte_t old_pte, pte;
 784
 785         pte = READ_ONCE(*ptep);
 786         do {
 787                 old_pte = pte;
 788                 pte = pte_mkold(pte);
 789                 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
 790                                                pte_val(old_pte), pte_val(pte));
 791         } while (pte_val(pte) != pte_val(old_pte));
 792
 793         return pte_young(pte);
 794 }
 795
 796 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
 797                                             unsigned long address,
 798                                             pte_t *ptep)
 799 {
 800         return __ptep_test_and_clear_young(ptep);
 801 }
 802
 803 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
 804 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
 805                                          unsigned long address, pte_t *ptep)
 806 {
 807         int young = ptep_test_and_clear_young(vma, address, ptep);
 808
 809         if (young) {
 810                 /*
 811                  * We can elide the trailing DSB here since the worst that can
 812                  * happen is that a CPU continues to use the young entry in its
 813                  * TLB and we mistakenly reclaim the associated page. The
 814                  * window for such an event is bounded by the next
 815                  * context-switch, which provides a DSB to complete the TLB
 816                  * invalidation.
 817                  */
 818                 flush_tlb_page_nosync(vma, address);
 819         }
 820
 821         return young;
 822 }
 823
 824 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 825 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
 826 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
 827                                             unsigned long address,
 828                                             pmd_t *pmdp)
 829 {
 830         return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
 831 }
 832 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 833
 834 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 835 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
 836                                        unsigned long address, pte_t *ptep)
 837 {
 838         return __pte(xchg_relaxed(&pte_val(*ptep), 0));
 839 }
 840
 841 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 842 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
 843 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
 844                                             unsigned long address, pmd_t *pmdp)
 845 {
 846         return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
 847 }
 848 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 849
 850 /*
 851  * ptep_set_wrprotect - mark read-only while trasferring potential hardware
 852  * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
 853  */
 854 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 855 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
 856 {
 857         pte_t old_pte, pte;
 858
 859         pte = READ_ONCE(*ptep);
 860         do {
 861                 old_pte = pte;
 862                 pte = pte_wrprotect(pte);
 863                 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
 864                                                pte_val(old_pte), pte_val(pte));
 865         } while (pte_val(pte) != pte_val(old_pte));
 866 }
 867
 868 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 869 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
 870 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
 871                                       unsigned long address, pmd_t *pmdp)
 872 {
 873         ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
 874 }
 875
 876 #define pmdp_establish pmdp_establish
 877 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
 878                 unsigned long address, pmd_t *pmdp, pmd_t pmd)
 879 {
 880         return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
 881 }
 882 #endif
 883
 884 /*
 885  * Encode and decode a swap entry:
 886  *      bits 0-1:       present (must be zero)
 887  *      bits 2-7:       swap type
 888  *      bits 8-57:      swap offset
 889  *      bit  58:        PTE_PROT_NONE (must be zero)
 890  */
 891 #define __SWP_TYPE_SHIFT        2
 892 #define __SWP_TYPE_BITS         6
 893 #define __SWP_OFFSET_BITS       50
 894 #define __SWP_TYPE_MASK         ((1 << __SWP_TYPE_BITS) - 1)
 895 #define __SWP_OFFSET_SHIFT      (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
 896 #define __SWP_OFFSET_MASK       ((1UL << __SWP_OFFSET_BITS) - 1)
 897
 898 #define __swp_type(x)           (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
 899 #define __swp_offset(x)         (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
 900 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
 901
 902 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 903 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
 904
 905 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
 906 #define __pmd_to_swp_entry(pmd)         ((swp_entry_t) { pmd_val(pmd) })
 907 #define __swp_entry_to_pmd(swp)         __pmd((swp).val)
 908 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
 909
 910 /*
 911  * Ensure that there are not more swap files than can be encoded in the kernel
 912  * PTEs.
 913  */
 914 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
 915
 916 extern int kern_addr_valid(unsigned long addr);
 917
 918 #ifdef CONFIG_ARM64_MTE
 919
 920 #define __HAVE_ARCH_PREPARE_TO_SWAP
 921 static inline int arch_prepare_to_swap(struct page *page)
 922 {
 923         if (system_supports_mte())
 924                 return mte_save_tags(page);
 925         return 0;
 926 }
 927
 928 #define __HAVE_ARCH_SWAP_INVALIDATE
 929 static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
 930 {
 931         if (system_supports_mte())
 932                 mte_invalidate_tags(type, offset);
 933 }
 934
 935 static inline void arch_swap_invalidate_area(int type)
 936 {
 937         if (system_supports_mte())
 938                 mte_invalidate_tags_area(type);
 939 }
 940
 941 #define __HAVE_ARCH_SWAP_RESTORE
 942 static inline void arch_swap_restore(swp_entry_t entry, struct page *page)
 943 {
 944         if (system_supports_mte() && mte_restore_tags(entry, page))
 945                 set_bit(PG_mte_tagged, &page->flags);
 946 }
 947
 948 #endif /* CONFIG_ARM64_MTE */
 949
 950 /*
 951  * On AArch64, the cache coherency is handled via the set_pte_at() function.
 952  */
 953 static inline void update_mmu_cache(struct vm_area_struct *vma,
 954                                     unsigned long addr, pte_t *ptep)
 955 {
 956         /*
 957          * We don't do anything here, so there's a very small chance of
 958          * us retaking a user fault which we just fixed up. The alternative
 959          * is doing a dsb(ishst), but that penalises the fastpath.
 960          */
 961 }
 962
 963 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
 964
 965 #ifdef CONFIG_ARM64_PA_BITS_52
 966 #define phys_to_ttbr(addr)      (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
 967 #else
 968 #define phys_to_ttbr(addr)      (addr)
 969 #endif
 970
 971 /*
 972  * On arm64 without hardware Access Flag, copying from user will fail because
 973  * the pte is old and cannot be marked young. So we always end up with zeroed
 974  * page after fork() + CoW for pfn mappings. We don't always have a
 975  * hardware-managed access flag on arm64.
 976  */
 977 static inline bool arch_faults_on_old_pte(void)
 978 {
 979         WARN_ON(preemptible());
 980
 981         return !cpu_has_hw_af();
 982 }
 983 #define arch_faults_on_old_pte arch_faults_on_old_pte
 984
 985 #endif /* !__ASSEMBLY__ */
 986
 987 #endif /* __ASM_PGTABLE_H */