WIP FPC-III support
[linux/fpc-iii.git] / arch / arm64 / kernel / cpuinfo.c
blob77605aec25fec843e6169c639b7f3b16392947d8
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Record and handle CPU attributes.
5 * Copyright (C) 2014 ARM Ltd.
6 */
7 #include <asm/arch_timer.h>
8 #include <asm/cache.h>
9 #include <asm/cpu.h>
10 #include <asm/cputype.h>
11 #include <asm/cpufeature.h>
12 #include <asm/fpsimd.h>
14 #include <linux/bitops.h>
15 #include <linux/bug.h>
16 #include <linux/compat.h>
17 #include <linux/elf.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/personality.h>
21 #include <linux/preempt.h>
22 #include <linux/printk.h>
23 #include <linux/seq_file.h>
24 #include <linux/sched.h>
25 #include <linux/smp.h>
26 #include <linux/delay.h>
29 * In case the boot CPU is hotpluggable, we record its initial state and
30 * current state separately. Certain system registers may contain different
31 * values depending on configuration at or after reset.
33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
34 static struct cpuinfo_arm64 boot_cpu_data;
36 static const char *icache_policy_str[] = {
37 [ICACHE_POLICY_VPIPT] = "VPIPT",
38 [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
39 [ICACHE_POLICY_VIPT] = "VIPT",
40 [ICACHE_POLICY_PIPT] = "PIPT",
43 unsigned long __icache_flags;
45 static const char *const hwcap_str[] = {
46 [KERNEL_HWCAP_FP] = "fp",
47 [KERNEL_HWCAP_ASIMD] = "asimd",
48 [KERNEL_HWCAP_EVTSTRM] = "evtstrm",
49 [KERNEL_HWCAP_AES] = "aes",
50 [KERNEL_HWCAP_PMULL] = "pmull",
51 [KERNEL_HWCAP_SHA1] = "sha1",
52 [KERNEL_HWCAP_SHA2] = "sha2",
53 [KERNEL_HWCAP_CRC32] = "crc32",
54 [KERNEL_HWCAP_ATOMICS] = "atomics",
55 [KERNEL_HWCAP_FPHP] = "fphp",
56 [KERNEL_HWCAP_ASIMDHP] = "asimdhp",
57 [KERNEL_HWCAP_CPUID] = "cpuid",
58 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm",
59 [KERNEL_HWCAP_JSCVT] = "jscvt",
60 [KERNEL_HWCAP_FCMA] = "fcma",
61 [KERNEL_HWCAP_LRCPC] = "lrcpc",
62 [KERNEL_HWCAP_DCPOP] = "dcpop",
63 [KERNEL_HWCAP_SHA3] = "sha3",
64 [KERNEL_HWCAP_SM3] = "sm3",
65 [KERNEL_HWCAP_SM4] = "sm4",
66 [KERNEL_HWCAP_ASIMDDP] = "asimddp",
67 [KERNEL_HWCAP_SHA512] = "sha512",
68 [KERNEL_HWCAP_SVE] = "sve",
69 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm",
70 [KERNEL_HWCAP_DIT] = "dit",
71 [KERNEL_HWCAP_USCAT] = "uscat",
72 [KERNEL_HWCAP_ILRCPC] = "ilrcpc",
73 [KERNEL_HWCAP_FLAGM] = "flagm",
74 [KERNEL_HWCAP_SSBS] = "ssbs",
75 [KERNEL_HWCAP_SB] = "sb",
76 [KERNEL_HWCAP_PACA] = "paca",
77 [KERNEL_HWCAP_PACG] = "pacg",
78 [KERNEL_HWCAP_DCPODP] = "dcpodp",
79 [KERNEL_HWCAP_SVE2] = "sve2",
80 [KERNEL_HWCAP_SVEAES] = "sveaes",
81 [KERNEL_HWCAP_SVEPMULL] = "svepmull",
82 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm",
83 [KERNEL_HWCAP_SVESHA3] = "svesha3",
84 [KERNEL_HWCAP_SVESM4] = "svesm4",
85 [KERNEL_HWCAP_FLAGM2] = "flagm2",
86 [KERNEL_HWCAP_FRINT] = "frint",
87 [KERNEL_HWCAP_SVEI8MM] = "svei8mm",
88 [KERNEL_HWCAP_SVEF32MM] = "svef32mm",
89 [KERNEL_HWCAP_SVEF64MM] = "svef64mm",
90 [KERNEL_HWCAP_SVEBF16] = "svebf16",
91 [KERNEL_HWCAP_I8MM] = "i8mm",
92 [KERNEL_HWCAP_BF16] = "bf16",
93 [KERNEL_HWCAP_DGH] = "dgh",
94 [KERNEL_HWCAP_RNG] = "rng",
95 [KERNEL_HWCAP_BTI] = "bti",
96 [KERNEL_HWCAP_MTE] = "mte",
99 #ifdef CONFIG_COMPAT
100 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x)
101 static const char *const compat_hwcap_str[] = {
102 [COMPAT_KERNEL_HWCAP(SWP)] = "swp",
103 [COMPAT_KERNEL_HWCAP(HALF)] = "half",
104 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb",
105 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */
106 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
107 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */
108 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp",
109 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp",
110 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */
111 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */
112 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */
113 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */
114 [COMPAT_KERNEL_HWCAP(NEON)] = "neon",
115 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3",
116 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
117 [COMPAT_KERNEL_HWCAP(TLS)] = "tls",
118 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4",
119 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva",
120 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt",
121 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */
122 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae",
123 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
126 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
127 static const char *const compat_hwcap2_str[] = {
128 [COMPAT_KERNEL_HWCAP2(AES)] = "aes",
129 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull",
130 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1",
131 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
132 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
134 #endif /* CONFIG_COMPAT */
136 static int c_show(struct seq_file *m, void *v)
138 int i, j;
139 bool compat = personality(current->personality) == PER_LINUX32;
141 for_each_online_cpu(i) {
142 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
143 u32 midr = cpuinfo->reg_midr;
146 * glibc reads /proc/cpuinfo to determine the number of
147 * online processors, looking for lines beginning with
148 * "processor". Give glibc what it expects.
150 seq_printf(m, "processor\t: %d\n", i);
151 if (compat)
152 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
153 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
155 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
156 loops_per_jiffy / (500000UL/HZ),
157 loops_per_jiffy / (5000UL/HZ) % 100);
160 * Dump out the common processor features in a single line.
161 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
162 * rather than attempting to parse this, but there's a body of
163 * software which does already (at least for 32-bit).
165 seq_puts(m, "Features\t:");
166 if (compat) {
167 #ifdef CONFIG_COMPAT
168 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
169 if (compat_elf_hwcap & (1 << j)) {
171 * Warn once if any feature should not
172 * have been present on arm64 platform.
174 if (WARN_ON_ONCE(!compat_hwcap_str[j]))
175 continue;
177 seq_printf(m, " %s", compat_hwcap_str[j]);
181 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
182 if (compat_elf_hwcap2 & (1 << j))
183 seq_printf(m, " %s", compat_hwcap2_str[j]);
184 #endif /* CONFIG_COMPAT */
185 } else {
186 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
187 if (cpu_have_feature(j))
188 seq_printf(m, " %s", hwcap_str[j]);
190 seq_puts(m, "\n");
192 seq_printf(m, "CPU implementer\t: 0x%02x\n",
193 MIDR_IMPLEMENTOR(midr));
194 seq_printf(m, "CPU architecture: 8\n");
195 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
196 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
197 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
200 return 0;
203 static void *c_start(struct seq_file *m, loff_t *pos)
205 return *pos < 1 ? (void *)1 : NULL;
208 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
210 ++*pos;
211 return NULL;
214 static void c_stop(struct seq_file *m, void *v)
218 const struct seq_operations cpuinfo_op = {
219 .start = c_start,
220 .next = c_next,
221 .stop = c_stop,
222 .show = c_show
226 static struct kobj_type cpuregs_kobj_type = {
227 .sysfs_ops = &kobj_sysfs_ops,
231 * The ARM ARM uses the phrase "32-bit register" to describe a register
232 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
233 * no statement is made as to whether the upper 32 bits will or will not
234 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
235 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
237 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
238 * registers, we expose them both as 64 bit values to cater for possible
239 * future expansion without an ABI break.
241 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
242 #define CPUREGS_ATTR_RO(_name, _field) \
243 static ssize_t _name##_show(struct kobject *kobj, \
244 struct kobj_attribute *attr, char *buf) \
246 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
248 if (info->reg_midr) \
249 return sprintf(buf, "0x%016x\n", info->reg_##_field); \
250 else \
251 return 0; \
253 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
255 CPUREGS_ATTR_RO(midr_el1, midr);
256 CPUREGS_ATTR_RO(revidr_el1, revidr);
258 static struct attribute *cpuregs_id_attrs[] = {
259 &cpuregs_attr_midr_el1.attr,
260 &cpuregs_attr_revidr_el1.attr,
261 NULL
264 static const struct attribute_group cpuregs_attr_group = {
265 .attrs = cpuregs_id_attrs,
266 .name = "identification"
269 static int cpuid_cpu_online(unsigned int cpu)
271 int rc;
272 struct device *dev;
273 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
275 dev = get_cpu_device(cpu);
276 if (!dev) {
277 rc = -ENODEV;
278 goto out;
280 rc = kobject_add(&info->kobj, &dev->kobj, "regs");
281 if (rc)
282 goto out;
283 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
284 if (rc)
285 kobject_del(&info->kobj);
286 out:
287 return rc;
290 static int cpuid_cpu_offline(unsigned int cpu)
292 struct device *dev;
293 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
295 dev = get_cpu_device(cpu);
296 if (!dev)
297 return -ENODEV;
298 if (info->kobj.parent) {
299 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
300 kobject_del(&info->kobj);
303 return 0;
306 static int __init cpuinfo_regs_init(void)
308 int cpu, ret;
310 for_each_possible_cpu(cpu) {
311 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
313 kobject_init(&info->kobj, &cpuregs_kobj_type);
316 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
317 cpuid_cpu_online, cpuid_cpu_offline);
318 if (ret < 0) {
319 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
320 return ret;
322 return 0;
324 device_initcall(cpuinfo_regs_init);
326 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
328 unsigned int cpu = smp_processor_id();
329 u32 l1ip = CTR_L1IP(info->reg_ctr);
331 switch (l1ip) {
332 case ICACHE_POLICY_PIPT:
333 break;
334 case ICACHE_POLICY_VPIPT:
335 set_bit(ICACHEF_VPIPT, &__icache_flags);
336 break;
337 case ICACHE_POLICY_RESERVED:
338 case ICACHE_POLICY_VIPT:
339 /* Assume aliasing */
340 set_bit(ICACHEF_ALIASING, &__icache_flags);
341 break;
344 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
347 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
349 info->reg_cntfrq = arch_timer_get_cntfrq();
351 * Use the effective value of the CTR_EL0 than the raw value
352 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
353 * with the CLIDR_EL1 fields to avoid triggering false warnings
354 * when there is a mismatch across the CPUs. Keep track of the
355 * effective value of the CTR_EL0 in our internal records for
356 * acurate sanity check and feature enablement.
358 info->reg_ctr = read_cpuid_effective_cachetype();
359 info->reg_dczid = read_cpuid(DCZID_EL0);
360 info->reg_midr = read_cpuid_id();
361 info->reg_revidr = read_cpuid(REVIDR_EL1);
363 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
364 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
365 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
366 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
367 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
368 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
369 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
370 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
371 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
372 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
374 /* Update the 32bit ID registers only if AArch32 is implemented */
375 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
376 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
377 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
378 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
379 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
380 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
381 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
382 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
383 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
384 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
385 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
386 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
387 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
388 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
389 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
390 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
391 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
392 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
393 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
395 info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
396 info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
397 info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
400 if (IS_ENABLED(CONFIG_ARM64_SVE) &&
401 id_aa64pfr0_sve(info->reg_id_aa64pfr0))
402 info->reg_zcr = read_zcr_features();
404 cpuinfo_detect_icache_policy(info);
407 void cpuinfo_store_cpu(void)
409 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
410 __cpuinfo_store_cpu(info);
411 update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
414 void __init cpuinfo_store_boot_cpu(void)
416 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
417 __cpuinfo_store_cpu(info);
419 boot_cpu_data = *info;
420 init_cpu_features(&boot_cpu_data);