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WIP FPC-III support
[linux/fpc-iii.git] / arch / ia64 / kernel / perfmon_montecito.h
blobc0b5b9110c88478a1a748804ddc568eb292d95d6
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * This file contains the Montecito PMU register description tables
4 * and pmc checker used by perfmon.c.
5 *
6 * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P.
7 * Contributed by Stephane Eranian <eranian@hpl.hp.com>
8 */
9 static int pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs);
10
11 #define RDEP_MONT_ETB (RDEP(38)|RDEP(39)|RDEP(48)|RDEP(49)|RDEP(50)|RDEP(51)|RDEP(52)|RDEP(53)|RDEP(54)|\
12 RDEP(55)|RDEP(56)|RDEP(57)|RDEP(58)|RDEP(59)|RDEP(60)|RDEP(61)|RDEP(62)|RDEP(63))
13 #define RDEP_MONT_DEAR (RDEP(32)|RDEP(33)|RDEP(36))
14 #define RDEP_MONT_IEAR (RDEP(34)|RDEP(35))
15
16 static pfm_reg_desc_t pfm_mont_pmc_desc[PMU_MAX_PMCS]={
17 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
18 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
19 /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
20 /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
21 /* pmc4 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(4),0, 0, 0}, {0,0, 0, 0}},
22 /* pmc5 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(5),0, 0, 0}, {0,0, 0, 0}},
23 /* pmc6 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(6),0, 0, 0}, {0,0, 0, 0}},
24 /* pmc7 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(7),0, 0, 0}, {0,0, 0, 0}},
25 /* pmc8 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(8),0, 0, 0}, {0,0, 0, 0}},
26 /* pmc9 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(9),0, 0, 0}, {0,0, 0, 0}},
27 /* pmc10 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(10),0, 0, 0}, {0,0, 0, 0}},
28 /* pmc11 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(11),0, 0, 0}, {0,0, 0, 0}},
29 /* pmc12 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(12),0, 0, 0}, {0,0, 0, 0}},
30 /* pmc13 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(13),0, 0, 0}, {0,0, 0, 0}},
31 /* pmc14 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(14),0, 0, 0}, {0,0, 0, 0}},
32 /* pmc15 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(15),0, 0, 0}, {0,0, 0, 0}},
33 /* pmc16 */ { PFM_REG_NOTIMPL, },
34 /* pmc17 */ { PFM_REG_NOTIMPL, },
35 /* pmc18 */ { PFM_REG_NOTIMPL, },
36 /* pmc19 */ { PFM_REG_NOTIMPL, },
37 /* pmc20 */ { PFM_REG_NOTIMPL, },
38 /* pmc21 */ { PFM_REG_NOTIMPL, },
39 /* pmc22 */ { PFM_REG_NOTIMPL, },
40 /* pmc23 */ { PFM_REG_NOTIMPL, },
41 /* pmc24 */ { PFM_REG_NOTIMPL, },
42 /* pmc25 */ { PFM_REG_NOTIMPL, },
43 /* pmc26 */ { PFM_REG_NOTIMPL, },
44 /* pmc27 */ { PFM_REG_NOTIMPL, },
45 /* pmc28 */ { PFM_REG_NOTIMPL, },
46 /* pmc29 */ { PFM_REG_NOTIMPL, },
47 /* pmc30 */ { PFM_REG_NOTIMPL, },
48 /* pmc31 */ { PFM_REG_NOTIMPL, },
49 /* pmc32 */ { PFM_REG_CONFIG, 0, 0x30f01ffffffffffUL, 0x30f01ffffffffffUL, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
50 /* pmc33 */ { PFM_REG_CONFIG, 0, 0x0, 0x1ffffffffffUL, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
51 /* pmc34 */ { PFM_REG_CONFIG, 0, 0xf01ffffffffffUL, 0xf01ffffffffffUL, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
52 /* pmc35 */ { PFM_REG_CONFIG, 0, 0x0, 0x1ffffffffffUL, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
53 /* pmc36 */ { PFM_REG_CONFIG, 0, 0xfffffff0, 0xf, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
54 /* pmc37 */ { PFM_REG_MONITOR, 4, 0x0, 0x3fff, NULL, pfm_mont_pmc_check, {RDEP_MONT_IEAR, 0, 0, 0}, {0, 0, 0, 0}},
55 /* pmc38 */ { PFM_REG_CONFIG, 0, 0xdb6, 0x2492, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
56 /* pmc39 */ { PFM_REG_MONITOR, 6, 0x0, 0xffcf, NULL, pfm_mont_pmc_check, {RDEP_MONT_ETB,0, 0, 0}, {0,0, 0, 0}},
57 /* pmc40 */ { PFM_REG_MONITOR, 6, 0x2000000, 0xf01cf, NULL, pfm_mont_pmc_check, {RDEP_MONT_DEAR,0, 0, 0}, {0,0, 0, 0}},
58 /* pmc41 */ { PFM_REG_CONFIG, 0, 0x00002078fefefefeUL, 0x1e00018181818UL, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
59 /* pmc42 */ { PFM_REG_MONITOR, 6, 0x0, 0x7ff4f, NULL, pfm_mont_pmc_check, {RDEP_MONT_ETB,0, 0, 0}, {0,0, 0, 0}},
60 { PFM_REG_END , 0, 0x0, -1, NULL, NULL, {0,}, {0,}}, /* end marker */
61 };
62
63 static pfm_reg_desc_t pfm_mont_pmd_desc[PMU_MAX_PMDS]={
64 /* pmd0 */ { PFM_REG_NOTIMPL, },
65 /* pmd1 */ { PFM_REG_NOTIMPL, },
66 /* pmd2 */ { PFM_REG_NOTIMPL, },
67 /* pmd3 */ { PFM_REG_NOTIMPL, },
68 /* pmd4 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(4),0, 0, 0}},
69 /* pmd5 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(5),0, 0, 0}},
70 /* pmd6 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(6),0, 0, 0}},
71 /* pmd7 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(7),0, 0, 0}},
72 /* pmd8 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(8),0, 0, 0}},
73 /* pmd9 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(9),0, 0, 0}},
74 /* pmd10 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(10),0, 0, 0}},
75 /* pmd11 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(11),0, 0, 0}},
76 /* pmd12 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(12),0, 0, 0}},
77 /* pmd13 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(13),0, 0, 0}},
78 /* pmd14 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(14),0, 0, 0}},
79 /* pmd15 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(15),0, 0, 0}},
80 /* pmd16 */ { PFM_REG_NOTIMPL, },
81 /* pmd17 */ { PFM_REG_NOTIMPL, },
82 /* pmd18 */ { PFM_REG_NOTIMPL, },
83 /* pmd19 */ { PFM_REG_NOTIMPL, },
84 /* pmd20 */ { PFM_REG_NOTIMPL, },
85 /* pmd21 */ { PFM_REG_NOTIMPL, },
86 /* pmd22 */ { PFM_REG_NOTIMPL, },
87 /* pmd23 */ { PFM_REG_NOTIMPL, },
88 /* pmd24 */ { PFM_REG_NOTIMPL, },
89 /* pmd25 */ { PFM_REG_NOTIMPL, },
90 /* pmd26 */ { PFM_REG_NOTIMPL, },
91 /* pmd27 */ { PFM_REG_NOTIMPL, },
92 /* pmd28 */ { PFM_REG_NOTIMPL, },
93 /* pmd29 */ { PFM_REG_NOTIMPL, },
94 /* pmd30 */ { PFM_REG_NOTIMPL, },
95 /* pmd31 */ { PFM_REG_NOTIMPL, },
96 /* pmd32 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(33)|RDEP(36),0, 0, 0}, {RDEP(40),0, 0, 0}},
97 /* pmd33 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(32)|RDEP(36),0, 0, 0}, {RDEP(40),0, 0, 0}},
98 /* pmd34 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(35),0, 0, 0}, {RDEP(37),0, 0, 0}},
99 /* pmd35 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(34),0, 0, 0}, {RDEP(37),0, 0, 0}},
100 /* pmd36 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(32)|RDEP(33),0, 0, 0}, {RDEP(40),0, 0, 0}},
101 /* pmd37 */ { PFM_REG_NOTIMPL, },
102 /* pmd38 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
103 /* pmd39 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
104 /* pmd40 */ { PFM_REG_NOTIMPL, },
105 /* pmd41 */ { PFM_REG_NOTIMPL, },
106 /* pmd42 */ { PFM_REG_NOTIMPL, },
107 /* pmd43 */ { PFM_REG_NOTIMPL, },
108 /* pmd44 */ { PFM_REG_NOTIMPL, },
109 /* pmd45 */ { PFM_REG_NOTIMPL, },
110 /* pmd46 */ { PFM_REG_NOTIMPL, },
111 /* pmd47 */ { PFM_REG_NOTIMPL, },
112 /* pmd48 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
113 /* pmd49 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
114 /* pmd50 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
115 /* pmd51 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
116 /* pmd52 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
117 /* pmd53 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
118 /* pmd54 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
119 /* pmd55 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
120 /* pmd56 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
121 /* pmd57 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
122 /* pmd58 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
123 /* pmd59 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
124 /* pmd60 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
125 /* pmd61 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
126 /* pmd62 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
127 /* pmd63 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
128 { PFM_REG_END , 0, 0x0, -1, NULL, NULL, {0,}, {0,}}, /* end marker */
129 };
130
131 /*
132 * PMC reserved fields must have their power-up values preserved
133 */
134 static int
135 pfm_mont_reserved(unsigned int cnum, unsigned long *val, struct pt_regs *regs)
136 {
137 unsigned long tmp1, tmp2, ival = *val;
138
139 /* remove reserved areas from user value */
140 tmp1 = ival & PMC_RSVD_MASK(cnum);
141
142 /* get reserved fields values */
143 tmp2 = PMC_DFL_VAL(cnum) & ~PMC_RSVD_MASK(cnum);
144
145 *val = tmp1 | tmp2;
146
147 DPRINT(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n",
148 cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val));
149 return 0;
150 }
151
152 /*
153 * task can be NULL if the context is unloaded
154 */
155 static int
156 pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs)
157 {
158 int ret = 0;
159 unsigned long val32 = 0, val38 = 0, val41 = 0;
160 unsigned long tmpval;
161 int check_case1 = 0;
162 int is_loaded;
163
164 /* first preserve the reserved fields */
165 pfm_mont_reserved(cnum, val, regs);
166
167 tmpval = *val;
168
169 /* sanity check */
170 if (ctx == NULL) return -EINVAL;
171
172 is_loaded = ctx->ctx_state == PFM_CTX_LOADED || ctx->ctx_state == PFM_CTX_MASKED;
173
174 /*
175 * we must clear the debug registers if pmc41 has a value which enable
176 * memory pipeline event constraints. In this case we need to clear the
177 * the debug registers if they have not yet been accessed. This is required
178 * to avoid picking stale state.
179 * PMC41 is "active" if:
180 * one of the pmc41.cfg_dtagXX field is different from 0x3
181 * AND
182 * at the corresponding pmc41.en_dbrpXX is set.
183 * AND
184 * ctx_fl_using_dbreg == 0 (i.e., dbr not yet used)
185 */
186 DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, tmpval, ctx->ctx_fl_using_dbreg, is_loaded));
187
188 if (cnum == 41 && is_loaded
189 && (tmpval & 0x1e00000000000UL) && (tmpval & 0x18181818UL) != 0x18181818UL && ctx->ctx_fl_using_dbreg == 0) {
190
191 DPRINT(("pmc[%d]=0x%lx has active pmc41 settings, clearing dbr\n", cnum, tmpval));
192
193 /* don't mix debug with perfmon */
194 if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
195
196 /*
197 * a count of 0 will mark the debug registers if:
198 * AND
199 */
200 ret = pfm_write_ibr_dbr(PFM_DATA_RR, ctx, NULL, 0, regs);
201 if (ret) return ret;
202 }
203 /*
204 * we must clear the (instruction) debug registers if:
205 * pmc38.ig_ibrpX is 0 (enabled)
206 * AND
207 * ctx_fl_using_dbreg == 0 (i.e., dbr not yet used)
208 */
209 if (cnum == 38 && is_loaded && ((tmpval & 0x492UL) != 0x492UL) && ctx->ctx_fl_using_dbreg == 0) {
210
211 DPRINT(("pmc38=0x%lx has active pmc38 settings, clearing ibr\n", tmpval));
212
213 /* don't mix debug with perfmon */
214 if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
215
216 /*
217 * a count of 0 will mark the debug registers as in use and also
218 * ensure that they are properly cleared.
219 */
220 ret = pfm_write_ibr_dbr(PFM_CODE_RR, ctx, NULL, 0, regs);
221 if (ret) return ret;
222
223 }
224 switch(cnum) {
225 case 32: val32 = *val;
226 val38 = ctx->ctx_pmcs[38];
227 val41 = ctx->ctx_pmcs[41];
228 check_case1 = 1;
229 break;
230 case 38: val38 = *val;
231 val32 = ctx->ctx_pmcs[32];
232 val41 = ctx->ctx_pmcs[41];
233 check_case1 = 1;
234 break;
235 case 41: val41 = *val;
236 val32 = ctx->ctx_pmcs[32];
237 val38 = ctx->ctx_pmcs[38];
238 check_case1 = 1;
239 break;
240 }
241 /* check illegal configuration which can produce inconsistencies in tagging
242 * i-side events in L1D and L2 caches
243 */
244 if (check_case1) {
245 ret = (((val41 >> 45) & 0xf) == 0 && ((val32>>57) & 0x1) == 0)
246 && ((((val38>>1) & 0x3) == 0x2 || ((val38>>1) & 0x3) == 0)
247 || (((val38>>4) & 0x3) == 0x2 || ((val38>>4) & 0x3) == 0));
248 if (ret) {
249 DPRINT(("invalid config pmc38=0x%lx pmc41=0x%lx pmc32=0x%lx\n", val38, val41, val32));
250 return -EINVAL;
251 }
252 }
253 *val = tmpval;
254 return 0;
255 }
256
257 /*
258 * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
259 */
260 static pmu_config_t pmu_conf_mont={
261 .pmu_name = "Montecito",
262 .pmu_family = 0x20,
263 .flags = PFM_PMU_IRQ_RESEND,
264 .ovfl_val = (1UL << 47) - 1,
265 .pmd_desc = pfm_mont_pmd_desc,
266 .pmc_desc = pfm_mont_pmc_desc,
267 .num_ibrs = 8,
268 .num_dbrs = 8,
269 .use_rr_dbregs = 1 /* debug register are use for range retrictions */
270 };
Linux with added FPC-III support