arch/m68k/68000/dragen2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1993 Hamish Macdonald
   4  *  Copyright (C) 1999 D. Jeff Dionne
   5  *  Copyright (C) 2001 Georges Menie, Ken Desmet
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file COPYING in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/init.h>
  12 #include <asm/machdep.h>
  13 #include <asm/MC68VZ328.h>
  14
  15 /***************************************************************************/
  16 /*                        Init Drangon Engine hardware                     */
  17 /***************************************************************************/
  18
  19 static void dragen2_reset(void)
  20 {
  21         local_irq_disable();
  22
  23 #ifdef CONFIG_INIT_LCD
  24         PBDATA |= 0x20;                         /* disable CCFL light */
  25         PKDATA |= 0x4;                          /* disable LCD controller */
  26         LCKCON = 0;
  27 #endif
  28
  29         __asm__ __volatile__(
  30                 "reset\n\t"
  31                 "moveal #0x04000000, %a0\n\t"
  32                 "moveal 0(%a0), %sp\n\t"
  33                 "moveal 4(%a0), %a0\n\t"
  34                 "jmp (%a0)"
  35         );
  36 }
  37
  38 void __init init_dragen2(char *command, int size)
  39 {
  40         mach_reset = dragen2_reset;
  41
  42 #ifdef CONFIG_DIRECT_IO_ACCESS
  43         SCR = 0x10;                                     /* allow user access to internal registers */
  44 #endif
  45
  46         /* CSGB Init */
  47         CSGBB = 0x4000;
  48         CSB = 0x1a1;
  49
  50         /* CS8900 init */
  51         /* PK3: hardware sleep function pin, active low */
  52         PKSEL |= PK(3);                         /* select pin as I/O */
  53         PKDIR |= PK(3);                         /* select pin as output */
  54         PKDATA |= PK(3);                        /* set pin high */
  55
  56         /* PF5: hardware reset function pin, active high */
  57         PFSEL |= PF(5);                         /* select pin as I/O */
  58         PFDIR |= PF(5);                         /* select pin as output */
  59         PFDATA &= ~PF(5);                       /* set pin low */
  60
  61         /* cs8900 hardware reset */
  62         PFDATA |= PF(5);
  63         { int i; for (i = 0; i < 32000; ++i); }
  64         PFDATA &= ~PF(5);
  65
  66         /* INT1 enable (cs8900 IRQ) */
  67         PDPOL &= ~PD(1);                        /* active high signal */
  68         PDIQEG &= ~PD(1);
  69         PDIRQEN |= PD(1);                       /* IRQ enabled */
  70
  71 #ifdef CONFIG_INIT_LCD
  72         /* initialize LCD controller */
  73         LSSA = (long) screen_bits;
  74         LVPW = 0x14;
  75         LXMAX = 0x140;
  76         LYMAX = 0xef;
  77         LRRA = 0;
  78         LPXCD = 3;
  79         LPICF = 0x08;
  80         LPOLCF = 0;
  81         LCKCON = 0x80;
  82         PCPDEN = 0xff;
  83         PCSEL = 0;
  84
  85         /* Enable LCD controller */
  86         PKDIR |= 0x4;
  87         PKSEL |= 0x4;
  88         PKDATA &= ~0x4;
  89
  90         /* Enable CCFL backlighting circuit */
  91         PBDIR |= 0x20;
  92         PBSEL |= 0x20;
  93         PBDATA &= ~0x20;
  94
  95         /* contrast control register */
  96         PFDIR |= 0x1;
  97         PFSEL &= ~0x1;
  98         PWMR = 0x037F;
  99 #endif
 100 }