arch/microblaze/include/asm/pvr.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Support for the MicroBlaze PVR (Processor Version Register)
   4  *
   5  * Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu>
   6  * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
   7  * Copyright (C) 2007 - 2011 PetaLogix
   8  */
   9
  10 #ifndef _ASM_MICROBLAZE_PVR_H
  11 #define _ASM_MICROBLAZE_PVR_H
  12
  13 #define PVR_MSR_BIT 0x400
  14
  15 struct pvr_s {
  16         unsigned pvr[12];
  17 };
  18
  19 /* The following taken from Xilinx's standalone BSP pvr.h */
  20
  21 /* Basic PVR mask */
  22 #define PVR0_PVR_FULL_MASK              0x80000000
  23 #define PVR0_USE_BARREL_MASK            0x40000000
  24 #define PVR0_USE_DIV_MASK               0x20000000
  25 #define PVR0_USE_HW_MUL_MASK            0x10000000
  26 #define PVR0_USE_FPU_MASK               0x08000000
  27 #define PVR0_USE_EXC_MASK               0x04000000
  28 #define PVR0_USE_ICACHE_MASK            0x02000000
  29 #define PVR0_USE_DCACHE_MASK            0x01000000
  30 #define PVR0_USE_MMU                    0x00800000
  31 #define PVR0_USE_BTC                    0x00400000
  32 #define PVR0_ENDI                       0x00200000
  33 #define PVR0_VERSION_MASK               0x0000FF00
  34 #define PVR0_USER1_MASK                 0x000000FF
  35
  36 /* User 2 PVR mask */
  37 #define PVR1_USER2_MASK                 0xFFFFFFFF
  38
  39 /* Configuration PVR masks */
  40 #define PVR2_D_OPB_MASK                 0x80000000 /* or AXI */
  41 #define PVR2_D_LMB_MASK                 0x40000000
  42 #define PVR2_I_OPB_MASK                 0x20000000 /* or AXI */
  43 #define PVR2_I_LMB_MASK                 0x10000000
  44 #define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
  45 #define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
  46 #define PVR2_D_PLB_MASK                 0x02000000 /* new */
  47 #define PVR2_I_PLB_MASK                 0x01000000 /* new */
  48 #define PVR2_INTERCONNECT               0x00800000 /* new */
  49 #define PVR2_USE_EXTEND_FSL             0x00080000 /* new */
  50 #define PVR2_USE_FSL_EXC                0x00040000 /* new */
  51 #define PVR2_USE_MSR_INSTR              0x00020000
  52 #define PVR2_USE_PCMP_INSTR             0x00010000
  53 #define PVR2_AREA_OPTIMISED             0x00008000
  54 #define PVR2_USE_BARREL_MASK            0x00004000
  55 #define PVR2_USE_DIV_MASK               0x00002000
  56 #define PVR2_USE_HW_MUL_MASK            0x00001000
  57 #define PVR2_USE_FPU_MASK               0x00000800
  58 #define PVR2_USE_MUL64_MASK             0x00000400
  59 #define PVR2_USE_FPU2_MASK              0x00000200 /* new */
  60 #define PVR2_USE_IPLBEXC                0x00000100
  61 #define PVR2_USE_DPLBEXC                0x00000080
  62 #define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
  63 #define PVR2_UNALIGNED_EXC_MASK         0x00000020
  64 #define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
  65 #define PVR2_IOPB_BUS_EXC_MASK          0x00000008 /* or AXI */
  66 #define PVR2_DOPB_BUS_EXC_MASK          0x00000004 /* or AXI */
  67 #define PVR2_DIV_ZERO_EXC_MASK          0x00000002
  68 #define PVR2_FPU_EXC_MASK               0x00000001
  69
  70 /* Debug and exception PVR masks */
  71 #define PVR3_DEBUG_ENABLED_MASK         0x80000000
  72 #define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
  73 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
  74 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
  75 #define PVR3_FSL_LINKS_MASK             0x00000380
  76
  77 /* ICache config PVR masks */
  78 #define PVR4_USE_ICACHE_MASK            0x80000000 /* ICU */
  79 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000 /* ICTS */
  80 #define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000 /* ICW */
  81 #define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000 /* ICLL */
  82 #define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000 /* ICBS */
  83 #define PVR4_ICACHE_ALWAYS_USED         0x00008000 /* IAU */
  84 #define PVR4_ICACHE_INTERFACE           0x00002000 /* ICI */
  85
  86 /* DCache config PVR masks */
  87 #define PVR5_USE_DCACHE_MASK            0x80000000 /* DCU */
  88 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000 /* DCTS */
  89 #define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000 /* DCW */
  90 #define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000 /* DCLL */
  91 #define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000 /* DCBS */
  92 #define PVR5_DCACHE_ALWAYS_USED         0x00008000 /* DAU */
  93 #define PVR5_DCACHE_USE_WRITEBACK       0x00004000 /* DWB */
  94 #define PVR5_DCACHE_INTERFACE           0x00002000 /* DCI */
  95
  96 /* ICache base address PVR mask */
  97 #define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF
  98
  99 /* ICache high address PVR mask */
 100 #define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF
 101
 102 /* DCache base address PVR mask */
 103 #define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF
 104
 105 /* DCache high address PVR mask */
 106 #define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF
 107
 108 /* Target family PVR mask */
 109 #define PVR10_TARGET_FAMILY_MASK        0xFF000000
 110
 111 /* MMU description */
 112 #define PVR11_USE_MMU                   0xC0000000
 113 #define PVR11_MMU_ITLB_SIZE             0x38000000
 114 #define PVR11_MMU_DTLB_SIZE             0x07000000
 115 #define PVR11_MMU_TLB_ACCESS            0x00C00000
 116 #define PVR11_MMU_ZONES                 0x003C0000
 117 #define PVR11_MMU_PRIVINS               0x00010000
 118 /* MSR Reset value PVR mask */
 119 #define PVR11_MSR_RESET_VALUE_MASK      0x000007FF
 120
 121 /* PVR access macros */
 122 #define PVR_IS_FULL(_pvr)       (_pvr.pvr[0] & PVR0_PVR_FULL_MASK)
 123 #define PVR_USE_BARREL(_pvr)    (_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
 124 #define PVR_USE_DIV(_pvr)       (_pvr.pvr[0] & PVR0_USE_DIV_MASK)
 125 #define PVR_USE_HW_MUL(_pvr)    (_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
 126 #define PVR_USE_FPU(_pvr)       (_pvr.pvr[0] & PVR0_USE_FPU_MASK)
 127 #define PVR_USE_FPU2(_pvr)      (_pvr.pvr[2] & PVR2_USE_FPU2_MASK)
 128 #define PVR_USE_ICACHE(_pvr)    (_pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
 129 #define PVR_USE_DCACHE(_pvr)    (_pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
 130 #define PVR_VERSION(_pvr)       ((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
 131 #define PVR_USER1(_pvr)         (_pvr.pvr[0] & PVR0_USER1_MASK)
 132 #define PVR_USER2(_pvr)         (_pvr.pvr[1] & PVR1_USER2_MASK)
 133
 134 #define PVR_D_OPB(_pvr)         (_pvr.pvr[2] & PVR2_D_OPB_MASK)
 135 #define PVR_D_LMB(_pvr)         (_pvr.pvr[2] & PVR2_D_LMB_MASK)
 136 #define PVR_I_OPB(_pvr)         (_pvr.pvr[2] & PVR2_I_OPB_MASK)
 137 #define PVR_I_LMB(_pvr)         (_pvr.pvr[2] & PVR2_I_LMB_MASK)
 138 #define PVR_INTERRUPT_IS_EDGE(_pvr) \
 139                         (_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
 140 #define PVR_EDGE_IS_POSITIVE(_pvr) \
 141                         (_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
 142 #define PVR_USE_MSR_INSTR(_pvr)         (_pvr.pvr[2] & PVR2_USE_MSR_INSTR)
 143 #define PVR_USE_PCMP_INSTR(_pvr)        (_pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
 144 #define PVR_AREA_OPTIMISED(_pvr)        (_pvr.pvr[2] & PVR2_AREA_OPTIMISED)
 145 #define PVR_USE_MUL64(_pvr)             (_pvr.pvr[2] & PVR2_USE_MUL64_MASK)
 146 #define PVR_OPCODE_0x0_ILLEGAL(_pvr) \
 147                         (_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
 148 #define PVR_UNALIGNED_EXCEPTION(_pvr) \
 149                         (_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
 150 #define PVR_ILL_OPCODE_EXCEPTION(_pvr) \
 151                         (_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
 152 #define PVR_IOPB_BUS_EXCEPTION(_pvr) \
 153                         (_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
 154 #define PVR_DOPB_BUS_EXCEPTION(_pvr) \
 155                         (_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
 156 #define PVR_DIV_ZERO_EXCEPTION(_pvr) \
 157                         (_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
 158 #define PVR_FPU_EXCEPTION(_pvr)         (_pvr.pvr[2] & PVR2_FPU_EXC_MASK)
 159 #define PVR_FSL_EXCEPTION(_pvr)         (_pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
 160
 161 #define PVR_DEBUG_ENABLED(_pvr)         (_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
 162 #define PVR_NUMBER_OF_PC_BRK(_pvr) \
 163                         ((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
 164 #define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \
 165                         ((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
 166 #define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \
 167                         ((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
 168 #define PVR_FSL_LINKS(_pvr)     ((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
 169
 170 #define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \
 171                 ((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
 172 #define PVR_ICACHE_USE_FSL(_pvr) \
 173                 (_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
 174 #define PVR_ICACHE_ALLOW_WR(_pvr) \
 175                 (_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
 176 #define PVR_ICACHE_LINE_LEN(_pvr) \
 177                 (1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
 178 #define PVR_ICACHE_BYTE_SIZE(_pvr) \
 179                 (1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
 180
 181 #define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \
 182                         ((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
 183 #define PVR_DCACHE_USE_FSL(_pvr)        (_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
 184 #define PVR_DCACHE_ALLOW_WR(_pvr) \
 185                         (_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
 186 /* FIXME two shifts on one line needs any comment */
 187 #define PVR_DCACHE_LINE_LEN(_pvr) \
 188                 (1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
 189 #define PVR_DCACHE_BYTE_SIZE(_pvr) \
 190                 (1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
 191
 192 #define PVR_DCACHE_USE_WRITEBACK(_pvr) \
 193                         ((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
 194
 195 #define PVR_ICACHE_BASEADDR(_pvr) \
 196                         (_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
 197 #define PVR_ICACHE_HIGHADDR(_pvr) \
 198                         (_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
 199 #define PVR_DCACHE_BASEADDR(_pvr) \
 200                         (_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
 201 #define PVR_DCACHE_HIGHADDR(_pvr) \
 202                         (_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
 203
 204 #define PVR_TARGET_FAMILY(_pvr) \
 205                         ((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
 206
 207 #define PVR_MSR_RESET_VALUE(_pvr) \
 208                         (_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
 209
 210 /* mmu */
 211 #define PVR_USE_MMU(_pvr)               ((_pvr.pvr[11] & PVR11_USE_MMU) >> 30)
 212 #define PVR_MMU_ITLB_SIZE(_pvr)         (_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
 213 #define PVR_MMU_DTLB_SIZE(_pvr)         (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
 214 #define PVR_MMU_TLB_ACCESS(_pvr)        (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
 215 #define PVR_MMU_ZONES(_pvr)             (_pvr.pvr[11] & PVR11_MMU_ZONES)
 216 #define PVR_MMU_PRIVINS(pvr)            (pvr.pvr[11] & PVR11_MMU_PRIVINS)
 217
 218 /* endian */
 219 #define PVR_ENDIAN(_pvr)        (_pvr.pvr[0] & PVR0_ENDI)
 220
 221 int cpu_has_pvr(void);
 222 void get_pvr(struct pvr_s *pvr);
 223
 224 #endif /* _ASM_MICROBLAZE_PVR_H */