arch/mips/include/asm/asmmacro.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Ralf Baechle
   7  */
   8 #ifndef _ASM_ASMMACRO_H
   9 #define _ASM_ASMMACRO_H
  10
  11 #include <asm/hazards.h>
  12 #include <asm/asm-offsets.h>
  13 #include <asm/msa.h>
  14
  15 #ifdef CONFIG_32BIT
  16 #include <asm/asmmacro-32.h>
  17 #endif
  18 #ifdef CONFIG_64BIT
  19 #include <asm/asmmacro-64.h>
  20 #endif
  21
  22 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
  23 #undef fp
  24
  25 /*
  26  * Helper macros for generating raw instruction encodings.
  27  */
  28 #ifdef CONFIG_CPU_MICROMIPS
  29         .macro  insn32_if_mm enc
  30         .insn
  31         .hword ((\enc) >> 16)
  32         .hword ((\enc) & 0xffff)
  33         .endm
  34
  35         .macro  insn_if_mips enc
  36         .endm
  37 #else
  38         .macro  insn32_if_mm enc
  39         .endm
  40
  41         .macro  insn_if_mips enc
  42         .insn
  43         .word (\enc)
  44         .endm
  45 #endif
  46
  47 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
  48     defined(CONFIG_CPU_MIPSR6)
  49         .macro  local_irq_enable reg=t0
  50         ei
  51         irq_enable_hazard
  52         .endm
  53
  54         .macro  local_irq_disable reg=t0
  55         di
  56         irq_disable_hazard
  57         .endm
  58 #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
  59         .macro  local_irq_enable reg=t0
  60         mfc0    \reg, CP0_STATUS
  61         ori     \reg, \reg, 1
  62         mtc0    \reg, CP0_STATUS
  63         irq_enable_hazard
  64         .endm
  65
  66         .macro  local_irq_disable reg=t0
  67 #ifdef CONFIG_PREEMPTION
  68         lw      \reg, TI_PRE_COUNT($28)
  69         addi    \reg, \reg, 1
  70         sw      \reg, TI_PRE_COUNT($28)
  71 #endif
  72         mfc0    \reg, CP0_STATUS
  73         ori     \reg, \reg, 1
  74         xori    \reg, \reg, 1
  75         mtc0    \reg, CP0_STATUS
  76         irq_disable_hazard
  77 #ifdef CONFIG_PREEMPTION
  78         lw      \reg, TI_PRE_COUNT($28)
  79         addi    \reg, \reg, -1
  80         sw      \reg, TI_PRE_COUNT($28)
  81 #endif
  82         .endm
  83 #endif  /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
  84
  85         .macro  fpu_save_16even thread tmp=t0
  86         .set    push
  87         SET_HARDFLOAT
  88         cfc1    \tmp, fcr31
  89         sdc1    $f0,  THREAD_FPR0(\thread)
  90         sdc1    $f2,  THREAD_FPR2(\thread)
  91         sdc1    $f4,  THREAD_FPR4(\thread)
  92         sdc1    $f6,  THREAD_FPR6(\thread)
  93         sdc1    $f8,  THREAD_FPR8(\thread)
  94         sdc1    $f10, THREAD_FPR10(\thread)
  95         sdc1    $f12, THREAD_FPR12(\thread)
  96         sdc1    $f14, THREAD_FPR14(\thread)
  97         sdc1    $f16, THREAD_FPR16(\thread)
  98         sdc1    $f18, THREAD_FPR18(\thread)
  99         sdc1    $f20, THREAD_FPR20(\thread)
 100         sdc1    $f22, THREAD_FPR22(\thread)
 101         sdc1    $f24, THREAD_FPR24(\thread)
 102         sdc1    $f26, THREAD_FPR26(\thread)
 103         sdc1    $f28, THREAD_FPR28(\thread)
 104         sdc1    $f30, THREAD_FPR30(\thread)
 105         sw      \tmp, THREAD_FCR31(\thread)
 106         .set    pop
 107         .endm
 108
 109         .macro  fpu_save_16odd thread
 110         .set    push
 111         .set    mips64r2
 112         .set    fp=64
 113         SET_HARDFLOAT
 114         sdc1    $f1,  THREAD_FPR1(\thread)
 115         sdc1    $f3,  THREAD_FPR3(\thread)
 116         sdc1    $f5,  THREAD_FPR5(\thread)
 117         sdc1    $f7,  THREAD_FPR7(\thread)
 118         sdc1    $f9,  THREAD_FPR9(\thread)
 119         sdc1    $f11, THREAD_FPR11(\thread)
 120         sdc1    $f13, THREAD_FPR13(\thread)
 121         sdc1    $f15, THREAD_FPR15(\thread)
 122         sdc1    $f17, THREAD_FPR17(\thread)
 123         sdc1    $f19, THREAD_FPR19(\thread)
 124         sdc1    $f21, THREAD_FPR21(\thread)
 125         sdc1    $f23, THREAD_FPR23(\thread)
 126         sdc1    $f25, THREAD_FPR25(\thread)
 127         sdc1    $f27, THREAD_FPR27(\thread)
 128         sdc1    $f29, THREAD_FPR29(\thread)
 129         sdc1    $f31, THREAD_FPR31(\thread)
 130         .set    pop
 131         .endm
 132
 133         .macro  fpu_save_double thread status tmp
 134 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
 135     defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
 136         sll     \tmp, \status, 5
 137         bgez    \tmp, 10f
 138         fpu_save_16odd \thread
 139 10:
 140 #endif
 141         fpu_save_16even \thread \tmp
 142         .endm
 143
 144         .macro  fpu_restore_16even thread tmp=t0
 145         .set    push
 146         SET_HARDFLOAT
 147         lw      \tmp, THREAD_FCR31(\thread)
 148         ldc1    $f0,  THREAD_FPR0(\thread)
 149         ldc1    $f2,  THREAD_FPR2(\thread)
 150         ldc1    $f4,  THREAD_FPR4(\thread)
 151         ldc1    $f6,  THREAD_FPR6(\thread)
 152         ldc1    $f8,  THREAD_FPR8(\thread)
 153         ldc1    $f10, THREAD_FPR10(\thread)
 154         ldc1    $f12, THREAD_FPR12(\thread)
 155         ldc1    $f14, THREAD_FPR14(\thread)
 156         ldc1    $f16, THREAD_FPR16(\thread)
 157         ldc1    $f18, THREAD_FPR18(\thread)
 158         ldc1    $f20, THREAD_FPR20(\thread)
 159         ldc1    $f22, THREAD_FPR22(\thread)
 160         ldc1    $f24, THREAD_FPR24(\thread)
 161         ldc1    $f26, THREAD_FPR26(\thread)
 162         ldc1    $f28, THREAD_FPR28(\thread)
 163         ldc1    $f30, THREAD_FPR30(\thread)
 164         ctc1    \tmp, fcr31
 165         .set    pop
 166         .endm
 167
 168         .macro  fpu_restore_16odd thread
 169         .set    push
 170         .set    mips64r2
 171         .set    fp=64
 172         SET_HARDFLOAT
 173         ldc1    $f1,  THREAD_FPR1(\thread)
 174         ldc1    $f3,  THREAD_FPR3(\thread)
 175         ldc1    $f5,  THREAD_FPR5(\thread)
 176         ldc1    $f7,  THREAD_FPR7(\thread)
 177         ldc1    $f9,  THREAD_FPR9(\thread)
 178         ldc1    $f11, THREAD_FPR11(\thread)
 179         ldc1    $f13, THREAD_FPR13(\thread)
 180         ldc1    $f15, THREAD_FPR15(\thread)
 181         ldc1    $f17, THREAD_FPR17(\thread)
 182         ldc1    $f19, THREAD_FPR19(\thread)
 183         ldc1    $f21, THREAD_FPR21(\thread)
 184         ldc1    $f23, THREAD_FPR23(\thread)
 185         ldc1    $f25, THREAD_FPR25(\thread)
 186         ldc1    $f27, THREAD_FPR27(\thread)
 187         ldc1    $f29, THREAD_FPR29(\thread)
 188         ldc1    $f31, THREAD_FPR31(\thread)
 189         .set    pop
 190         .endm
 191
 192         .macro  fpu_restore_double thread status tmp
 193 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
 194     defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
 195         sll     \tmp, \status, 5
 196         bgez    \tmp, 10f                               # 16 register mode?
 197
 198         fpu_restore_16odd \thread
 199 10:
 200 #endif
 201         fpu_restore_16even \thread \tmp
 202         .endm
 203
 204 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
 205     defined(CONFIG_CPU_MIPSR6)
 206         .macro  _EXT    rd, rs, p, s
 207         ext     \rd, \rs, \p, \s
 208         .endm
 209 #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
 210         .macro  _EXT    rd, rs, p, s
 211         srl     \rd, \rs, \p
 212         andi    \rd, \rd, (1 << \s) - 1
 213         .endm
 214 #endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
 215
 216 /*
 217  * Temporary until all gas have MT ASE support
 218  */
 219         .macro  DMT     reg=0
 220         .word   0x41600bc1 | (\reg << 16)
 221         .endm
 222
 223         .macro  EMT     reg=0
 224         .word   0x41600be1 | (\reg << 16)
 225         .endm
 226
 227         .macro  DVPE    reg=0
 228         .word   0x41600001 | (\reg << 16)
 229         .endm
 230
 231         .macro  EVPE    reg=0
 232         .word   0x41600021 | (\reg << 16)
 233         .endm
 234
 235         .macro  MFTR    rt=0, rd=0, u=0, sel=0
 236          .word  0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
 237         .endm
 238
 239         .macro  MTTR    rt=0, rd=0, u=0, sel=0
 240          .word  0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
 241         .endm
 242
 243 #ifdef TOOLCHAIN_SUPPORTS_MSA
 244         .macro  _cfcmsa rd, cs
 245         .set    push
 246         .set    mips32r2
 247         .set    fp=64
 248         .set    msa
 249         cfcmsa  \rd, $\cs
 250         .set    pop
 251         .endm
 252
 253         .macro  _ctcmsa cd, rs
 254         .set    push
 255         .set    mips32r2
 256         .set    fp=64
 257         .set    msa
 258         ctcmsa  $\cd, \rs
 259         .set    pop
 260         .endm
 261
 262         .macro  ld_b    wd, off, base
 263         .set    push
 264         .set    mips32r2
 265         .set    fp=64
 266         .set    msa
 267         ld.b    $w\wd, \off(\base)
 268         .set    pop
 269         .endm
 270
 271         .macro  ld_h    wd, off, base
 272         .set    push
 273         .set    mips32r2
 274         .set    fp=64
 275         .set    msa
 276         ld.h    $w\wd, \off(\base)
 277         .set    pop
 278         .endm
 279
 280         .macro  ld_w    wd, off, base
 281         .set    push
 282         .set    mips32r2
 283         .set    fp=64
 284         .set    msa
 285         ld.w    $w\wd, \off(\base)
 286         .set    pop
 287         .endm
 288
 289         .macro  ld_d    wd, off, base
 290         .set    push
 291         .set    mips32r2
 292         .set    fp=64
 293         .set    msa
 294         ld.d    $w\wd, \off(\base)
 295         .set    pop
 296         .endm
 297
 298         .macro  st_b    wd, off, base
 299         .set    push
 300         .set    mips32r2
 301         .set    fp=64
 302         .set    msa
 303         st.b    $w\wd, \off(\base)
 304         .set    pop
 305         .endm
 306
 307         .macro  st_h    wd, off, base
 308         .set    push
 309         .set    mips32r2
 310         .set    fp=64
 311         .set    msa
 312         st.h    $w\wd, \off(\base)
 313         .set    pop
 314         .endm
 315
 316         .macro  st_w    wd, off, base
 317         .set    push
 318         .set    mips32r2
 319         .set    fp=64
 320         .set    msa
 321         st.w    $w\wd, \off(\base)
 322         .set    pop
 323         .endm
 324
 325         .macro  st_d    wd, off, base
 326         .set    push
 327         .set    mips32r2
 328         .set    fp=64
 329         .set    msa
 330         st.d    $w\wd, \off(\base)
 331         .set    pop
 332         .endm
 333
 334         .macro  copy_s_w        ws, n
 335         .set    push
 336         .set    mips32r2
 337         .set    fp=64
 338         .set    msa
 339         copy_s.w $1, $w\ws[\n]
 340         .set    pop
 341         .endm
 342
 343         .macro  copy_s_d        ws, n
 344         .set    push
 345         .set    mips64r2
 346         .set    fp=64
 347         .set    msa
 348         copy_s.d $1, $w\ws[\n]
 349         .set    pop
 350         .endm
 351
 352         .macro  insert_w        wd, n
 353         .set    push
 354         .set    mips32r2
 355         .set    fp=64
 356         .set    msa
 357         insert.w $w\wd[\n], $1
 358         .set    pop
 359         .endm
 360
 361         .macro  insert_d        wd, n
 362         .set    push
 363         .set    mips64r2
 364         .set    fp=64
 365         .set    msa
 366         insert.d $w\wd[\n], $1
 367         .set    pop
 368         .endm
 369 #else
 370
 371         /*
 372          * Temporary until all toolchains in use include MSA support.
 373          */
 374         .macro  _cfcmsa rd, cs
 375         .set    push
 376         .set    noat
 377         SET_HARDFLOAT
 378         insn_if_mips 0x787e0059 | (\cs << 11)
 379         insn32_if_mm 0x587e0056 | (\cs << 11)
 380         move    \rd, $1
 381         .set    pop
 382         .endm
 383
 384         .macro  _ctcmsa cd, rs
 385         .set    push
 386         .set    noat
 387         SET_HARDFLOAT
 388         move    $1, \rs
 389         insn_if_mips 0x783e0819 | (\cd << 6)
 390         insn32_if_mm 0x583e0816 | (\cd << 6)
 391         .set    pop
 392         .endm
 393
 394         .macro  ld_b    wd, off, base
 395         .set    push
 396         .set    noat
 397         SET_HARDFLOAT
 398         PTR_ADDU $1, \base, \off
 399         insn_if_mips 0x78000820 | (\wd << 6)
 400         insn32_if_mm 0x58000807 | (\wd << 6)
 401         .set    pop
 402         .endm
 403
 404         .macro  ld_h    wd, off, base
 405         .set    push
 406         .set    noat
 407         SET_HARDFLOAT
 408         PTR_ADDU $1, \base, \off
 409         insn_if_mips 0x78000821 | (\wd << 6)
 410         insn32_if_mm 0x58000817 | (\wd << 6)
 411         .set    pop
 412         .endm
 413
 414         .macro  ld_w    wd, off, base
 415         .set    push
 416         .set    noat
 417         SET_HARDFLOAT
 418         PTR_ADDU $1, \base, \off
 419         insn_if_mips 0x78000822 | (\wd << 6)
 420         insn32_if_mm 0x58000827 | (\wd << 6)
 421         .set    pop
 422         .endm
 423
 424         .macro  ld_d    wd, off, base
 425         .set    push
 426         .set    noat
 427         SET_HARDFLOAT
 428         PTR_ADDU $1, \base, \off
 429         insn_if_mips 0x78000823 | (\wd << 6)
 430         insn32_if_mm 0x58000837 | (\wd << 6)
 431         .set    pop
 432         .endm
 433
 434         .macro  st_b    wd, off, base
 435         .set    push
 436         .set    noat
 437         SET_HARDFLOAT
 438         PTR_ADDU $1, \base, \off
 439         insn_if_mips 0x78000824 | (\wd << 6)
 440         insn32_if_mm 0x5800080f | (\wd << 6)
 441         .set    pop
 442         .endm
 443
 444         .macro  st_h    wd, off, base
 445         .set    push
 446         .set    noat
 447         SET_HARDFLOAT
 448         PTR_ADDU $1, \base, \off
 449         insn_if_mips 0x78000825 | (\wd << 6)
 450         insn32_if_mm 0x5800081f | (\wd << 6)
 451         .set    pop
 452         .endm
 453
 454         .macro  st_w    wd, off, base
 455         .set    push
 456         .set    noat
 457         SET_HARDFLOAT
 458         PTR_ADDU $1, \base, \off
 459         insn_if_mips 0x78000826 | (\wd << 6)
 460         insn32_if_mm 0x5800082f | (\wd << 6)
 461         .set    pop
 462         .endm
 463
 464         .macro  st_d    wd, off, base
 465         .set    push
 466         .set    noat
 467         SET_HARDFLOAT
 468         PTR_ADDU $1, \base, \off
 469         insn_if_mips 0x78000827 | (\wd << 6)
 470         insn32_if_mm 0x5800083f | (\wd << 6)
 471         .set    pop
 472         .endm
 473
 474         .macro  copy_s_w        ws, n
 475         .set    push
 476         .set    noat
 477         SET_HARDFLOAT
 478         insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
 479         insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
 480         .set    pop
 481         .endm
 482
 483         .macro  copy_s_d        ws, n
 484         .set    push
 485         .set    noat
 486         SET_HARDFLOAT
 487         insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
 488         insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
 489         .set    pop
 490         .endm
 491
 492         .macro  insert_w        wd, n
 493         .set    push
 494         .set    noat
 495         SET_HARDFLOAT
 496         insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
 497         insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
 498         .set    pop
 499         .endm
 500
 501         .macro  insert_d        wd, n
 502         .set    push
 503         .set    noat
 504         SET_HARDFLOAT
 505         insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
 506         insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
 507         .set    pop
 508         .endm
 509 #endif
 510
 511 #ifdef TOOLCHAIN_SUPPORTS_MSA
 512 #define FPR_BASE_OFFS   THREAD_FPR0
 513 #define FPR_BASE        $1
 514 #else
 515 #define FPR_BASE_OFFS   0
 516 #define FPR_BASE        \thread
 517 #endif
 518
 519         .macro  msa_save_all    thread
 520         .set    push
 521         .set    noat
 522 #ifdef TOOLCHAIN_SUPPORTS_MSA
 523         PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
 524 #endif
 525         st_d     0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
 526         st_d     1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
 527         st_d     2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
 528         st_d     3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
 529         st_d     4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
 530         st_d     5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
 531         st_d     6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
 532         st_d     7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
 533         st_d     8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
 534         st_d     9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
 535         st_d    10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
 536         st_d    11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
 537         st_d    12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
 538         st_d    13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
 539         st_d    14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
 540         st_d    15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
 541         st_d    16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
 542         st_d    17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
 543         st_d    18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
 544         st_d    19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
 545         st_d    20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
 546         st_d    21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
 547         st_d    22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
 548         st_d    23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
 549         st_d    24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
 550         st_d    25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
 551         st_d    26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
 552         st_d    27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
 553         st_d    28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
 554         st_d    29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
 555         st_d    30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
 556         st_d    31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
 557         SET_HARDFLOAT
 558         _cfcmsa $1, MSA_CSR
 559         sw      $1, THREAD_MSA_CSR(\thread)
 560         .set    pop
 561         .endm
 562
 563         .macro  msa_restore_all thread
 564         .set    push
 565         .set    noat
 566         SET_HARDFLOAT
 567         lw      $1, THREAD_MSA_CSR(\thread)
 568         _ctcmsa MSA_CSR, $1
 569 #ifdef TOOLCHAIN_SUPPORTS_MSA
 570         PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
 571 #endif
 572         ld_d     0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
 573         ld_d     1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
 574         ld_d     2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
 575         ld_d     3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
 576         ld_d     4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
 577         ld_d     5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
 578         ld_d     6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
 579         ld_d     7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
 580         ld_d     8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
 581         ld_d     9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
 582         ld_d    10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
 583         ld_d    11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
 584         ld_d    12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
 585         ld_d    13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
 586         ld_d    14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
 587         ld_d    15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
 588         ld_d    16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
 589         ld_d    17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
 590         ld_d    18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
 591         ld_d    19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
 592         ld_d    20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
 593         ld_d    21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
 594         ld_d    22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
 595         ld_d    23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
 596         ld_d    24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
 597         ld_d    25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
 598         ld_d    26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
 599         ld_d    27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
 600         ld_d    28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
 601         ld_d    29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
 602         ld_d    30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
 603         ld_d    31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
 604         .set pop
 605         .endm
 606
 607 #undef FPR_BASE_OFFS
 608 #undef FPR_BASE
 609
 610         .macro  msa_init_upper wd
 611 #ifdef CONFIG_64BIT
 612         insert_d \wd, 1
 613 #else
 614         insert_w \wd, 2
 615         insert_w \wd, 3
 616 #endif
 617         .endm
 618
 619         .macro  msa_init_all_upper
 620         .set    push
 621         .set    noat
 622         SET_HARDFLOAT
 623         not     $1, zero
 624         msa_init_upper  0
 625         msa_init_upper  1
 626         msa_init_upper  2
 627         msa_init_upper  3
 628         msa_init_upper  4
 629         msa_init_upper  5
 630         msa_init_upper  6
 631         msa_init_upper  7
 632         msa_init_upper  8
 633         msa_init_upper  9
 634         msa_init_upper  10
 635         msa_init_upper  11
 636         msa_init_upper  12
 637         msa_init_upper  13
 638         msa_init_upper  14
 639         msa_init_upper  15
 640         msa_init_upper  16
 641         msa_init_upper  17
 642         msa_init_upper  18
 643         msa_init_upper  19
 644         msa_init_upper  20
 645         msa_init_upper  21
 646         msa_init_upper  22
 647         msa_init_upper  23
 648         msa_init_upper  24
 649         msa_init_upper  25
 650         msa_init_upper  26
 651         msa_init_upper  27
 652         msa_init_upper  28
 653         msa_init_upper  29
 654         msa_init_upper  30
 655         msa_init_upper  31
 656         .set    pop
 657         .endm
 658
 659 #endif /* _ASM_ASMMACRO_H */