arch/mips/include/asm/octeon/cvmx-mixx-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2012 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_MIXX_DEFS_H__
  29 #define __CVMX_MIXX_DEFS_H__
  30
  31 #define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
  32 #define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
  33 #define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
  34 #define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
  35 #define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
  36 #define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
  37 #define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
  38 #define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
  39 #define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
  40 #define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
  41 #define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
  42 #define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
  43 #define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
  44 #define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
  45 #define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
  46
  47 union cvmx_mixx_bist {
  48         uint64_t u64;
  49         struct cvmx_mixx_bist_s {
  50 #ifdef __BIG_ENDIAN_BITFIELD
  51                 uint64_t reserved_6_63:58;
  52                 uint64_t opfdat:1;
  53                 uint64_t mrgdat:1;
  54                 uint64_t mrqdat:1;
  55                 uint64_t ipfdat:1;
  56                 uint64_t irfdat:1;
  57                 uint64_t orfdat:1;
  58 #else
  59                 uint64_t orfdat:1;
  60                 uint64_t irfdat:1;
  61                 uint64_t ipfdat:1;
  62                 uint64_t mrqdat:1;
  63                 uint64_t mrgdat:1;
  64                 uint64_t opfdat:1;
  65                 uint64_t reserved_6_63:58;
  66 #endif
  67         } s;
  68         struct cvmx_mixx_bist_cn52xx {
  69 #ifdef __BIG_ENDIAN_BITFIELD
  70                 uint64_t reserved_4_63:60;
  71                 uint64_t mrqdat:1;
  72                 uint64_t ipfdat:1;
  73                 uint64_t irfdat:1;
  74                 uint64_t orfdat:1;
  75 #else
  76                 uint64_t orfdat:1;
  77                 uint64_t irfdat:1;
  78                 uint64_t ipfdat:1;
  79                 uint64_t mrqdat:1;
  80                 uint64_t reserved_4_63:60;
  81 #endif
  82         } cn52xx;
  83 };
  84
  85 union cvmx_mixx_ctl {
  86         uint64_t u64;
  87         struct cvmx_mixx_ctl_s {
  88 #ifdef __BIG_ENDIAN_BITFIELD
  89                 uint64_t reserved_12_63:52;
  90                 uint64_t ts_thresh:4;
  91                 uint64_t crc_strip:1;
  92                 uint64_t busy:1;
  93                 uint64_t en:1;
  94                 uint64_t reset:1;
  95                 uint64_t lendian:1;
  96                 uint64_t nbtarb:1;
  97                 uint64_t mrq_hwm:2;
  98 #else
  99                 uint64_t mrq_hwm:2;
 100                 uint64_t nbtarb:1;
 101                 uint64_t lendian:1;
 102                 uint64_t reset:1;
 103                 uint64_t en:1;
 104                 uint64_t busy:1;
 105                 uint64_t crc_strip:1;
 106                 uint64_t ts_thresh:4;
 107                 uint64_t reserved_12_63:52;
 108 #endif
 109         } s;
 110         struct cvmx_mixx_ctl_cn52xx {
 111 #ifdef __BIG_ENDIAN_BITFIELD
 112                 uint64_t reserved_8_63:56;
 113                 uint64_t crc_strip:1;
 114                 uint64_t busy:1;
 115                 uint64_t en:1;
 116                 uint64_t reset:1;
 117                 uint64_t lendian:1;
 118                 uint64_t nbtarb:1;
 119                 uint64_t mrq_hwm:2;
 120 #else
 121                 uint64_t mrq_hwm:2;
 122                 uint64_t nbtarb:1;
 123                 uint64_t lendian:1;
 124                 uint64_t reset:1;
 125                 uint64_t en:1;
 126                 uint64_t busy:1;
 127                 uint64_t crc_strip:1;
 128                 uint64_t reserved_8_63:56;
 129 #endif
 130         } cn52xx;
 131 };
 132
 133 union cvmx_mixx_intena {
 134         uint64_t u64;
 135         struct cvmx_mixx_intena_s {
 136 #ifdef __BIG_ENDIAN_BITFIELD
 137                 uint64_t reserved_8_63:56;
 138                 uint64_t tsena:1;
 139                 uint64_t orunena:1;
 140                 uint64_t irunena:1;
 141                 uint64_t data_drpena:1;
 142                 uint64_t ithena:1;
 143                 uint64_t othena:1;
 144                 uint64_t ivfena:1;
 145                 uint64_t ovfena:1;
 146 #else
 147                 uint64_t ovfena:1;
 148                 uint64_t ivfena:1;
 149                 uint64_t othena:1;
 150                 uint64_t ithena:1;
 151                 uint64_t data_drpena:1;
 152                 uint64_t irunena:1;
 153                 uint64_t orunena:1;
 154                 uint64_t tsena:1;
 155                 uint64_t reserved_8_63:56;
 156 #endif
 157         } s;
 158         struct cvmx_mixx_intena_cn52xx {
 159 #ifdef __BIG_ENDIAN_BITFIELD
 160                 uint64_t reserved_7_63:57;
 161                 uint64_t orunena:1;
 162                 uint64_t irunena:1;
 163                 uint64_t data_drpena:1;
 164                 uint64_t ithena:1;
 165                 uint64_t othena:1;
 166                 uint64_t ivfena:1;
 167                 uint64_t ovfena:1;
 168 #else
 169                 uint64_t ovfena:1;
 170                 uint64_t ivfena:1;
 171                 uint64_t othena:1;
 172                 uint64_t ithena:1;
 173                 uint64_t data_drpena:1;
 174                 uint64_t irunena:1;
 175                 uint64_t orunena:1;
 176                 uint64_t reserved_7_63:57;
 177 #endif
 178         } cn52xx;
 179 };
 180
 181 union cvmx_mixx_ircnt {
 182         uint64_t u64;
 183         struct cvmx_mixx_ircnt_s {
 184 #ifdef __BIG_ENDIAN_BITFIELD
 185                 uint64_t reserved_20_63:44;
 186                 uint64_t ircnt:20;
 187 #else
 188                 uint64_t ircnt:20;
 189                 uint64_t reserved_20_63:44;
 190 #endif
 191         } s;
 192 };
 193
 194 union cvmx_mixx_irhwm {
 195         uint64_t u64;
 196         struct cvmx_mixx_irhwm_s {
 197 #ifdef __BIG_ENDIAN_BITFIELD
 198                 uint64_t reserved_40_63:24;
 199                 uint64_t ibplwm:20;
 200                 uint64_t irhwm:20;
 201 #else
 202                 uint64_t irhwm:20;
 203                 uint64_t ibplwm:20;
 204                 uint64_t reserved_40_63:24;
 205 #endif
 206         } s;
 207 };
 208
 209 union cvmx_mixx_iring1 {
 210         uint64_t u64;
 211         struct cvmx_mixx_iring1_s {
 212 #ifdef __BIG_ENDIAN_BITFIELD
 213                 uint64_t reserved_60_63:4;
 214                 uint64_t isize:20;
 215                 uint64_t ibase:37;
 216                 uint64_t reserved_0_2:3;
 217 #else
 218                 uint64_t reserved_0_2:3;
 219                 uint64_t ibase:37;
 220                 uint64_t isize:20;
 221                 uint64_t reserved_60_63:4;
 222 #endif
 223         } s;
 224         struct cvmx_mixx_iring1_cn52xx {
 225 #ifdef __BIG_ENDIAN_BITFIELD
 226                 uint64_t reserved_60_63:4;
 227                 uint64_t isize:20;
 228                 uint64_t reserved_36_39:4;
 229                 uint64_t ibase:33;
 230                 uint64_t reserved_0_2:3;
 231 #else
 232                 uint64_t reserved_0_2:3;
 233                 uint64_t ibase:33;
 234                 uint64_t reserved_36_39:4;
 235                 uint64_t isize:20;
 236                 uint64_t reserved_60_63:4;
 237 #endif
 238         } cn52xx;
 239 };
 240
 241 union cvmx_mixx_iring2 {
 242         uint64_t u64;
 243         struct cvmx_mixx_iring2_s {
 244 #ifdef __BIG_ENDIAN_BITFIELD
 245                 uint64_t reserved_52_63:12;
 246                 uint64_t itlptr:20;
 247                 uint64_t reserved_20_31:12;
 248                 uint64_t idbell:20;
 249 #else
 250                 uint64_t idbell:20;
 251                 uint64_t reserved_20_31:12;
 252                 uint64_t itlptr:20;
 253                 uint64_t reserved_52_63:12;
 254 #endif
 255         } s;
 256 };
 257
 258 union cvmx_mixx_isr {
 259         uint64_t u64;
 260         struct cvmx_mixx_isr_s {
 261 #ifdef __BIG_ENDIAN_BITFIELD
 262                 uint64_t reserved_8_63:56;
 263                 uint64_t ts:1;
 264                 uint64_t orun:1;
 265                 uint64_t irun:1;
 266                 uint64_t data_drp:1;
 267                 uint64_t irthresh:1;
 268                 uint64_t orthresh:1;
 269                 uint64_t idblovf:1;
 270                 uint64_t odblovf:1;
 271 #else
 272                 uint64_t odblovf:1;
 273                 uint64_t idblovf:1;
 274                 uint64_t orthresh:1;
 275                 uint64_t irthresh:1;
 276                 uint64_t data_drp:1;
 277                 uint64_t irun:1;
 278                 uint64_t orun:1;
 279                 uint64_t ts:1;
 280                 uint64_t reserved_8_63:56;
 281 #endif
 282         } s;
 283         struct cvmx_mixx_isr_cn52xx {
 284 #ifdef __BIG_ENDIAN_BITFIELD
 285                 uint64_t reserved_7_63:57;
 286                 uint64_t orun:1;
 287                 uint64_t irun:1;
 288                 uint64_t data_drp:1;
 289                 uint64_t irthresh:1;
 290                 uint64_t orthresh:1;
 291                 uint64_t idblovf:1;
 292                 uint64_t odblovf:1;
 293 #else
 294                 uint64_t odblovf:1;
 295                 uint64_t idblovf:1;
 296                 uint64_t orthresh:1;
 297                 uint64_t irthresh:1;
 298                 uint64_t data_drp:1;
 299                 uint64_t irun:1;
 300                 uint64_t orun:1;
 301                 uint64_t reserved_7_63:57;
 302 #endif
 303         } cn52xx;
 304 };
 305
 306 union cvmx_mixx_orcnt {
 307         uint64_t u64;
 308         struct cvmx_mixx_orcnt_s {
 309 #ifdef __BIG_ENDIAN_BITFIELD
 310                 uint64_t reserved_20_63:44;
 311                 uint64_t orcnt:20;
 312 #else
 313                 uint64_t orcnt:20;
 314                 uint64_t reserved_20_63:44;
 315 #endif
 316         } s;
 317 };
 318
 319 union cvmx_mixx_orhwm {
 320         uint64_t u64;
 321         struct cvmx_mixx_orhwm_s {
 322 #ifdef __BIG_ENDIAN_BITFIELD
 323                 uint64_t reserved_20_63:44;
 324                 uint64_t orhwm:20;
 325 #else
 326                 uint64_t orhwm:20;
 327                 uint64_t reserved_20_63:44;
 328 #endif
 329         } s;
 330 };
 331
 332 union cvmx_mixx_oring1 {
 333         uint64_t u64;
 334         struct cvmx_mixx_oring1_s {
 335 #ifdef __BIG_ENDIAN_BITFIELD
 336                 uint64_t reserved_60_63:4;
 337                 uint64_t osize:20;
 338                 uint64_t obase:37;
 339                 uint64_t reserved_0_2:3;
 340 #else
 341                 uint64_t reserved_0_2:3;
 342                 uint64_t obase:37;
 343                 uint64_t osize:20;
 344                 uint64_t reserved_60_63:4;
 345 #endif
 346         } s;
 347         struct cvmx_mixx_oring1_cn52xx {
 348 #ifdef __BIG_ENDIAN_BITFIELD
 349                 uint64_t reserved_60_63:4;
 350                 uint64_t osize:20;
 351                 uint64_t reserved_36_39:4;
 352                 uint64_t obase:33;
 353                 uint64_t reserved_0_2:3;
 354 #else
 355                 uint64_t reserved_0_2:3;
 356                 uint64_t obase:33;
 357                 uint64_t reserved_36_39:4;
 358                 uint64_t osize:20;
 359                 uint64_t reserved_60_63:4;
 360 #endif
 361         } cn52xx;
 362 };
 363
 364 union cvmx_mixx_oring2 {
 365         uint64_t u64;
 366         struct cvmx_mixx_oring2_s {
 367 #ifdef __BIG_ENDIAN_BITFIELD
 368                 uint64_t reserved_52_63:12;
 369                 uint64_t otlptr:20;
 370                 uint64_t reserved_20_31:12;
 371                 uint64_t odbell:20;
 372 #else
 373                 uint64_t odbell:20;
 374                 uint64_t reserved_20_31:12;
 375                 uint64_t otlptr:20;
 376                 uint64_t reserved_52_63:12;
 377 #endif
 378         } s;
 379 };
 380
 381 union cvmx_mixx_remcnt {
 382         uint64_t u64;
 383         struct cvmx_mixx_remcnt_s {
 384 #ifdef __BIG_ENDIAN_BITFIELD
 385                 uint64_t reserved_52_63:12;
 386                 uint64_t iremcnt:20;
 387                 uint64_t reserved_20_31:12;
 388                 uint64_t oremcnt:20;
 389 #else
 390                 uint64_t oremcnt:20;
 391                 uint64_t reserved_20_31:12;
 392                 uint64_t iremcnt:20;
 393                 uint64_t reserved_52_63:12;
 394 #endif
 395         } s;
 396 };
 397
 398 union cvmx_mixx_tsctl {
 399         uint64_t u64;
 400         struct cvmx_mixx_tsctl_s {
 401 #ifdef __BIG_ENDIAN_BITFIELD
 402                 uint64_t reserved_21_63:43;
 403                 uint64_t tsavl:5;
 404                 uint64_t reserved_13_15:3;
 405                 uint64_t tstot:5;
 406                 uint64_t reserved_5_7:3;
 407                 uint64_t tscnt:5;
 408 #else
 409                 uint64_t tscnt:5;
 410                 uint64_t reserved_5_7:3;
 411                 uint64_t tstot:5;
 412                 uint64_t reserved_13_15:3;
 413                 uint64_t tsavl:5;
 414                 uint64_t reserved_21_63:43;
 415 #endif
 416         } s;
 417 };
 418
 419 union cvmx_mixx_tstamp {
 420         uint64_t u64;
 421         struct cvmx_mixx_tstamp_s {
 422 #ifdef __BIG_ENDIAN_BITFIELD
 423                 uint64_t tstamp:64;
 424 #else
 425                 uint64_t tstamp:64;
 426 #endif
 427         } s;
 428 };
 429
 430 #endif