arch/mips/include/asm/sni.h

   1 /*
   2  * SNI specific definitions
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1997, 1998 by Ralf Baechle
   9  * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
  10  */
  11 #ifndef __ASM_SNI_H
  12 #define __ASM_SNI_H
  13
  14 #include <linux/irqreturn.h>
  15
  16 extern unsigned int sni_brd_type;
  17
  18 #define SNI_BRD_10                 2
  19 #define SNI_BRD_10NEW              3
  20 #define SNI_BRD_TOWER_OASIC        4
  21 #define SNI_BRD_MINITOWER          5
  22 #define SNI_BRD_PCI_TOWER          6
  23 #define SNI_BRD_RM200              7
  24 #define SNI_BRD_PCI_MTOWER         8
  25 #define SNI_BRD_PCI_DESKTOP        9
  26 #define SNI_BRD_PCI_TOWER_CPLUS   10
  27 #define SNI_BRD_PCI_MTOWER_CPLUS  11
  28
  29 /* RM400 cpu types */
  30 #define SNI_CPU_M8021           0x01
  31 #define SNI_CPU_M8030           0x04
  32 #define SNI_CPU_M8031           0x06
  33 #define SNI_CPU_M8034           0x0f
  34 #define SNI_CPU_M8037           0x07
  35 #define SNI_CPU_M8040           0x05
  36 #define SNI_CPU_M8043           0x09
  37 #define SNI_CPU_M8050           0x0b
  38 #define SNI_CPU_M8053           0x0d
  39
  40 #define SNI_PORT_BASE           CKSEG1ADDR(0xb4000000)
  41
  42 #ifndef __MIPSEL__
  43 /*
  44  * ASIC PCI registers for big endian configuration.
  45  */
  46 #define PCIMT_UCONF             CKSEG1ADDR(0xbfff0004)
  47 #define PCIMT_IOADTIMEOUT2      CKSEG1ADDR(0xbfff000c)
  48 #define PCIMT_IOMEMCONF         CKSEG1ADDR(0xbfff0014)
  49 #define PCIMT_IOMMU             CKSEG1ADDR(0xbfff001c)
  50 #define PCIMT_IOADTIMEOUT1      CKSEG1ADDR(0xbfff0024)
  51 #define PCIMT_DMAACCESS         CKSEG1ADDR(0xbfff002c)
  52 #define PCIMT_DMAHIT            CKSEG1ADDR(0xbfff0034)
  53 #define PCIMT_ERRSTATUS         CKSEG1ADDR(0xbfff003c)
  54 #define PCIMT_ERRADDR           CKSEG1ADDR(0xbfff0044)
  55 #define PCIMT_SYNDROME          CKSEG1ADDR(0xbfff004c)
  56 #define PCIMT_ITPEND            CKSEG1ADDR(0xbfff0054)
  57 #define  IT_INT2                0x01
  58 #define  IT_INTD                0x02
  59 #define  IT_INTC                0x04
  60 #define  IT_INTB                0x08
  61 #define  IT_INTA                0x10
  62 #define  IT_EISA                0x20
  63 #define  IT_SCSI                0x40
  64 #define  IT_ETH                 0x80
  65 #define PCIMT_IRQSEL            CKSEG1ADDR(0xbfff005c)
  66 #define PCIMT_TESTMEM           CKSEG1ADDR(0xbfff0064)
  67 #define PCIMT_ECCREG            CKSEG1ADDR(0xbfff006c)
  68 #define PCIMT_CONFIG_ADDRESS    CKSEG1ADDR(0xbfff0074)
  69 #define PCIMT_ASIC_ID           CKSEG1ADDR(0xbfff007c)  /* read */
  70 #define PCIMT_SOFT_RESET        CKSEG1ADDR(0xbfff007c)  /* write */
  71 #define PCIMT_PIA_OE            CKSEG1ADDR(0xbfff0084)
  72 #define PCIMT_PIA_DATAOUT       CKSEG1ADDR(0xbfff008c)
  73 #define PCIMT_PIA_DATAIN        CKSEG1ADDR(0xbfff0094)
  74 #define PCIMT_CACHECONF         CKSEG1ADDR(0xbfff009c)
  75 #define PCIMT_INVSPACE          CKSEG1ADDR(0xbfff00a4)
  76 #else
  77 /*
  78  * ASIC PCI registers for little endian configuration.
  79  */
  80 #define PCIMT_UCONF             CKSEG1ADDR(0xbfff0000)
  81 #define PCIMT_IOADTIMEOUT2      CKSEG1ADDR(0xbfff0008)
  82 #define PCIMT_IOMEMCONF         CKSEG1ADDR(0xbfff0010)
  83 #define PCIMT_IOMMU             CKSEG1ADDR(0xbfff0018)
  84 #define PCIMT_IOADTIMEOUT1      CKSEG1ADDR(0xbfff0020)
  85 #define PCIMT_DMAACCESS         CKSEG1ADDR(0xbfff0028)
  86 #define PCIMT_DMAHIT            CKSEG1ADDR(0xbfff0030)
  87 #define PCIMT_ERRSTATUS         CKSEG1ADDR(0xbfff0038)
  88 #define PCIMT_ERRADDR           CKSEG1ADDR(0xbfff0040)
  89 #define PCIMT_SYNDROME          CKSEG1ADDR(0xbfff0048)
  90 #define PCIMT_ITPEND            CKSEG1ADDR(0xbfff0050)
  91 #define  IT_INT2                0x01
  92 #define  IT_INTD                0x02
  93 #define  IT_INTC                0x04
  94 #define  IT_INTB                0x08
  95 #define  IT_INTA                0x10
  96 #define  IT_EISA                0x20
  97 #define  IT_SCSI                0x40
  98 #define  IT_ETH                 0x80
  99 #define PCIMT_IRQSEL            CKSEG1ADDR(0xbfff0058)
 100 #define PCIMT_TESTMEM           CKSEG1ADDR(0xbfff0060)
 101 #define PCIMT_ECCREG            CKSEG1ADDR(0xbfff0068)
 102 #define PCIMT_CONFIG_ADDRESS    CKSEG1ADDR(0xbfff0070)
 103 #define PCIMT_ASIC_ID           CKSEG1ADDR(0xbfff0078)  /* read */
 104 #define PCIMT_SOFT_RESET        CKSEG1ADDR(0xbfff0078)  /* write */
 105 #define PCIMT_PIA_OE            CKSEG1ADDR(0xbfff0080)
 106 #define PCIMT_PIA_DATAOUT       CKSEG1ADDR(0xbfff0088)
 107 #define PCIMT_PIA_DATAIN        CKSEG1ADDR(0xbfff0090)
 108 #define PCIMT_CACHECONF         CKSEG1ADDR(0xbfff0098)
 109 #define PCIMT_INVSPACE          CKSEG1ADDR(0xbfff00a0)
 110 #endif
 111
 112 #define PCIMT_PCI_CONF          CKSEG1ADDR(0xbfff0100)
 113
 114 /*
 115  * Data port for the PCI bus in IO space
 116  */
 117 #define PCIMT_CONFIG_DATA       0x0cfc
 118
 119 /*
 120  * Board specific registers
 121  */
 122 #define PCIMT_CSMSR             CKSEG1ADDR(0xbfd00000)
 123 #define PCIMT_CSSWITCH          CKSEG1ADDR(0xbfd10000)
 124 #define PCIMT_CSITPEND          CKSEG1ADDR(0xbfd20000)
 125 #define PCIMT_AUTO_PO_EN        CKSEG1ADDR(0xbfd30000)
 126 #define PCIMT_CLR_TEMP          CKSEG1ADDR(0xbfd40000)
 127 #define PCIMT_AUTO_PO_DIS       CKSEG1ADDR(0xbfd50000)
 128 #define PCIMT_EXMSR             CKSEG1ADDR(0xbfd60000)
 129 #define PCIMT_UNUSED1           CKSEG1ADDR(0xbfd70000)
 130 #define PCIMT_CSWCSM            CKSEG1ADDR(0xbfd80000)
 131 #define PCIMT_UNUSED2           CKSEG1ADDR(0xbfd90000)
 132 #define PCIMT_CSLED             CKSEG1ADDR(0xbfda0000)
 133 #define PCIMT_CSMAPISA          CKSEG1ADDR(0xbfdb0000)
 134 #define PCIMT_CSRSTBP           CKSEG1ADDR(0xbfdc0000)
 135 #define PCIMT_CLRPOFF           CKSEG1ADDR(0xbfdd0000)
 136 #define PCIMT_CSTIMER           CKSEG1ADDR(0xbfde0000)
 137 #define PCIMT_PWDN              CKSEG1ADDR(0xbfdf0000)
 138
 139 /*
 140  * A20R based boards
 141  */
 142 #define A20R_PT_CLOCK_BASE      CKSEG1ADDR(0xbc040000)
 143 #define A20R_PT_TIM0_ACK        CKSEG1ADDR(0xbc050000)
 144 #define A20R_PT_TIM1_ACK        CKSEG1ADDR(0xbc060000)
 145
 146 #define SNI_A20R_IRQ_BASE       MIPS_CPU_IRQ_BASE
 147 #define SNI_A20R_IRQ_TIMER      (SNI_A20R_IRQ_BASE+5)
 148
 149 #define SNI_PCIT_INT_REG        CKSEG1ADDR(0xbfff000c)
 150
 151 #define SNI_PCIT_INT_START      24
 152 #define SNI_PCIT_INT_END        30
 153
 154 #define PCIT_IRQ_ETHERNET       (MIPS_CPU_IRQ_BASE + 5)
 155 #define PCIT_IRQ_INTA           (SNI_PCIT_INT_START + 0)
 156 #define PCIT_IRQ_INTB           (SNI_PCIT_INT_START + 1)
 157 #define PCIT_IRQ_INTC           (SNI_PCIT_INT_START + 2)
 158 #define PCIT_IRQ_INTD           (SNI_PCIT_INT_START + 3)
 159 #define PCIT_IRQ_SCSI0          (SNI_PCIT_INT_START + 4)
 160 #define PCIT_IRQ_SCSI1          (SNI_PCIT_INT_START + 5)
 161
 162
 163 /*
 164  * Interrupt 0-16 are EISA interrupts.  Interrupts from 16 on are assigned
 165  * to the other interrupts generated by ASIC PCI.
 166  *
 167  * INT2 is a wired-or of the push button interrupt, high temperature interrupt
 168  * ASIC PCI interrupt.
 169  */
 170 #define PCIMT_KEYBOARD_IRQ       1
 171 #define PCIMT_IRQ_INT2          24
 172 #define PCIMT_IRQ_INTD          25
 173 #define PCIMT_IRQ_INTC          26
 174 #define PCIMT_IRQ_INTB          27
 175 #define PCIMT_IRQ_INTA          28
 176 #define PCIMT_IRQ_EISA          29
 177 #define PCIMT_IRQ_SCSI          30
 178
 179 #define PCIMT_IRQ_ETHERNET      (MIPS_CPU_IRQ_BASE+6)
 180
 181 #if 0
 182 #define PCIMT_IRQ_TEMPERATURE   24
 183 #define PCIMT_IRQ_EISA_NMI      25
 184 #define PCIMT_IRQ_POWER_OFF     26
 185 #define PCIMT_IRQ_BUTTON        27
 186 #endif
 187
 188 /*
 189  * Base address for the mapped 16mb EISA bus segment.
 190  */
 191 #define PCIMT_EISA_BASE         CKSEG1ADDR(0xb0000000)
 192
 193 /* PCI EISA Interrupt acknowledge  */
 194 #define PCIMT_INT_ACKNOWLEDGE   CKSEG1ADDR(0xba000000)
 195
 196 /*
 197  *  SNI ID PROM
 198  *
 199  * SNI_IDPROM_MEMSIZE  Memsize in 16MB quantities
 200  * SNI_IDPROM_BRDTYPE  Board Type
 201  * SNI_IDPROM_CPUTYPE  CPU Type on RM400
 202  */
 203 #ifdef CONFIG_CPU_BIG_ENDIAN
 204 #define __SNI_END 0
 205 #endif
 206 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 207 #define __SNI_END 3
 208 #endif
 209 #define SNI_IDPROM_BASE        CKSEG1ADDR(0x1ff00000)
 210 #define SNI_IDPROM_MEMSIZE     (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
 211 #define SNI_IDPROM_BRDTYPE     (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
 212 #define SNI_IDPROM_CPUTYPE     (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
 213
 214 #define SNI_IDPROM_SIZE 0x1000
 215
 216 /* board specific init functions */
 217 extern void sni_a20r_init(void);
 218 extern void sni_pcit_init(void);
 219 extern void sni_rm200_init(void);
 220 extern void sni_pcimt_init(void);
 221
 222 /* board specific irq init functions */
 223 extern void sni_a20r_irq_init(void);
 224 extern void sni_pcit_irq_init(void);
 225 extern void sni_pcit_cplus_irq_init(void);
 226 extern void sni_rm200_irq_init(void);
 227 extern void sni_pcimt_irq_init(void);
 228
 229 /* timer inits */
 230 extern void sni_cpu_time_init(void);
 231
 232 /* eisa init for RM200/400 */
 233 #ifdef CONFIG_EISA
 234 extern int sni_eisa_root_init(void);
 235 #else
 236 static inline int sni_eisa_root_init(void)
 237 {
 238         return 0;
 239 }
 240 #endif
 241
 242 /* common irq stuff */
 243 extern void (*sni_hwint)(void);
 244 extern irqreturn_t sni_isa_irq_handler(int dummy, void *p);
 245
 246 #endif /* __ASM_SNI_H */