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WIP FPC-III support
[linux/fpc-iii.git] / arch / mips / txx9 / generic / setup_tx4939.c
blobbf8a3cdababf75b7e67fa0097729775e7e445771
1 /*
2 * TX4939 setup routines
3 * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/netdevice.h>
17 #include <linux/notifier.h>
18 #include <linux/device.h>
19 #include <linux/ethtool.h>
20 #include <linux/param.h>
21 #include <linux/ptrace.h>
22 #include <linux/mtd/physmap.h>
23 #include <linux/platform_device.h>
24 #include <linux/platform_data/txx9/ndfmc.h>
25 #include <asm/reboot.h>
26 #include <asm/traps.h>
27 #include <asm/txx9irq.h>
28 #include <asm/txx9tmr.h>
29 #include <asm/txx9/generic.h>
30 #include <asm/txx9/dmac.h>
31 #include <asm/txx9/tx4939.h>
32
33 static void __init tx4939_wdr_init(void)
34 {
35 /* report watchdog reset status */
36 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
37 pr_warn("Watchdog reset detected at 0x%lx\n",
38 read_c0_errorepc());
39 /* clear WatchDogReset (W1C) */
40 tx4939_ccfg_set(TX4939_CCFG_WDRST);
41 /* do reset on watchdog */
42 tx4939_ccfg_set(TX4939_CCFG_WR);
43 }
44
45 void __init tx4939_wdt_init(void)
46 {
47 txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
48 }
49
50 static void tx4939_machine_restart(char *command)
51 {
52 local_irq_disable();
53 pr_emerg("Rebooting (with %s watchdog reset)...\n",
54 (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
55 "external" : "internal");
56 /* clear watchdog status */
57 tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
58 txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
59 while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
60 ;
61 mdelay(10);
62 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
63 pr_emerg("Rebooting (with internal watchdog reset)...\n");
64 /* External WDRST failed. Do internal watchdog reset */
65 tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
66 }
67 /* fallback */
68 (*_machine_halt)();
69 }
70
71 void show_registers(struct pt_regs *regs);
72 static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
73 {
74 int data = regs->cp0_cause & 4;
75 console_verbose();
76 pr_err("%cBE exception at %#lx\n",
77 data ? 'D' : 'I', regs->cp0_epc);
78 pr_err("ccfg:%llx, toea:%llx\n",
79 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
80 (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
81 #ifdef CONFIG_PCI
82 tx4927_report_pcic_status();
83 #endif
84 show_registers(regs);
85 panic("BusError!");
86 }
87 static void __init tx4939_be_init(void)
88 {
89 board_be_handler = tx4939_be_handler;
90 }
91
92 static struct resource tx4939_sdram_resource[4];
93 static struct resource tx4939_sram_resource;
94 #define TX4939_SRAM_SIZE 0x800
95
96 void __init tx4939_setup(void)
97 {
98 int i;
99 __u32 divmode;
100 __u64 pcfg;
101 unsigned int cpuclk = 0;
102
103 txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
104 TX4939_REG_SIZE);
105 set_c0_config(TX49_CONF_CWFON);
106
107 /* SDRAMC,EBUSC are configured by PROM */
108 for (i = 0; i < 4; i++) {
109 if (!(TX4939_EBUSC_CR(i) & 0x8))
110 continue; /* disabled */
111 txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
112 txx9_ce_res[i].end =
113 txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
114 request_resource(&iomem_resource, &txx9_ce_res[i]);
115 }
116
117 /* clocks */
118 if (txx9_master_clock) {
119 /* calculate cpu_clock from master_clock */
120 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
121 TX4939_CCFG_MULCLK_MASK;
122 cpuclk = txx9_master_clock * 20 / 2;
123 switch (divmode) {
124 case TX4939_CCFG_MULCLK_8:
125 cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
126 case TX4939_CCFG_MULCLK_9:
127 cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
128 case TX4939_CCFG_MULCLK_10:
129 cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
130 case TX4939_CCFG_MULCLK_11:
131 cpuclk = cpuclk / 6 * 11; break;
132 case TX4939_CCFG_MULCLK_12:
133 cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
134 case TX4939_CCFG_MULCLK_13:
135 cpuclk = cpuclk / 6 * 13; break;
136 case TX4939_CCFG_MULCLK_14:
137 cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
138 case TX4939_CCFG_MULCLK_15:
139 cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
140 }
141 txx9_cpu_clock = cpuclk;
142 } else {
143 if (txx9_cpu_clock == 0)
144 txx9_cpu_clock = 400000000; /* 400MHz */
145 /* calculate master_clock from cpu_clock */
146 cpuclk = txx9_cpu_clock;
147 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
148 TX4939_CCFG_MULCLK_MASK;
149 switch (divmode) {
150 case TX4939_CCFG_MULCLK_8:
151 txx9_master_clock = cpuclk * 6 / 8; break;
152 case TX4939_CCFG_MULCLK_9:
153 txx9_master_clock = cpuclk * 6 / 9; break;
154 case TX4939_CCFG_MULCLK_10:
155 txx9_master_clock = cpuclk * 6 / 10; break;
156 case TX4939_CCFG_MULCLK_11:
157 txx9_master_clock = cpuclk * 6 / 11; break;
158 case TX4939_CCFG_MULCLK_12:
159 txx9_master_clock = cpuclk * 6 / 12; break;
160 case TX4939_CCFG_MULCLK_13:
161 txx9_master_clock = cpuclk * 6 / 13; break;
162 case TX4939_CCFG_MULCLK_14:
163 txx9_master_clock = cpuclk * 6 / 14; break;
164 case TX4939_CCFG_MULCLK_15:
165 txx9_master_clock = cpuclk * 6 / 15; break;
166 }
167 txx9_master_clock /= 10; /* * 2 / 20 */
168 }
169 /* calculate gbus_clock from cpu_clock */
170 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
171 TX4939_CCFG_YDIVMODE_MASK;
172 txx9_gbus_clock = txx9_cpu_clock;
173 switch (divmode) {
174 case TX4939_CCFG_YDIVMODE_2:
175 txx9_gbus_clock /= 2; break;
176 case TX4939_CCFG_YDIVMODE_3:
177 txx9_gbus_clock /= 3; break;
178 case TX4939_CCFG_YDIVMODE_5:
179 txx9_gbus_clock /= 5; break;
180 case TX4939_CCFG_YDIVMODE_6:
181 txx9_gbus_clock /= 6; break;
182 }
183 /* change default value to udelay/mdelay take reasonable time */
184 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
185
186 /* CCFG */
187 tx4939_wdr_init();
188 /* clear BusErrorOnWrite flag (W1C) */
189 tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
190 /* enable Timeout BusError */
191 if (txx9_ccfg_toeon)
192 tx4939_ccfg_set(TX4939_CCFG_TOE);
193
194 /* DMA selection */
195 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
196
197 /* Use external clock for external arbiter */
198 if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
199 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
200
201 pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
202 txx9_pcode_str,
203 (cpuclk + 500000) / 1000000,
204 (txx9_master_clock + 500000) / 1000000,
205 (txx9_gbus_clock + 500000) / 1000000,
206 (__u32)____raw_readq(&tx4939_ccfgptr->crir),
207 ____raw_readq(&tx4939_ccfgptr->ccfg),
208 ____raw_readq(&tx4939_ccfgptr->pcfg));
209
210 pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
211 (__u32)____raw_readq(&tx4939_ddrcptr->winen));
212 for (i = 0; i < 4; i++) {
213 __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
214 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
215 continue; /* disabled */
216 pr_cont(" #%d:%016llx", i, win);
217 tx4939_sdram_resource[i].name = "DDR SDRAM";
218 tx4939_sdram_resource[i].start =
219 (unsigned long)(win >> 48) << 20;
220 tx4939_sdram_resource[i].end =
221 ((((unsigned long)(win >> 32) & 0xffff) + 1) <<
222 20) - 1;
223 tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
224 request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
225 }
226 pr_cont("\n");
227
228 /* SRAM */
229 if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
230 unsigned int size = TX4939_SRAM_SIZE;
231 tx4939_sram_resource.name = "SRAM";
232 tx4939_sram_resource.start =
233 (____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
234 & ~(size - 1);
235 tx4939_sram_resource.end =
236 tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
237 tx4939_sram_resource.flags = IORESOURCE_MEM;
238 request_resource(&iomem_resource, &tx4939_sram_resource);
239 }
240
241 /* TMR */
242 /* disable all timers */
243 for (i = 0; i < TX4939_NR_TMR; i++)
244 txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
245
246 /* set PCIC1 reset (required to prevent hangup on BIST) */
247 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
248 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
249 if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
250 mdelay(1); /* at least 128 cpu clock */
251 /* clear PCIC1 reset */
252 txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
253 } else {
254 pr_info("%s: stop PCIC1\n", txx9_pcode_str);
255 /* stop PCIC1 */
256 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
257 }
258 if (!(pcfg & TX4939_PCFG_ET0MODE)) {
259 pr_info("%s: stop ETH0\n", txx9_pcode_str);
260 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
261 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
262 }
263 if (!(pcfg & TX4939_PCFG_ET1MODE)) {
264 pr_info("%s: stop ETH1\n", txx9_pcode_str);
265 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
266 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
267 }
268
269 _machine_restart = tx4939_machine_restart;
270 board_be_init = tx4939_be_init;
271 }
272
273 void __init tx4939_time_init(unsigned int tmrnr)
274 {
275 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
276 txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
277 TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
278 TXX9_IMCLK);
279 }
280
281 void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
282 {
283 int i;
284 unsigned int ch_mask = 0;
285 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
286
287 cts_mask |= ~1; /* only SIO0 have RTS/CTS */
288 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
289 cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
290 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
291 ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
292 if (pcfg & TX4939_PCFG_SIO3MODE)
293 ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
294 for (i = 0; i < 4; i++) {
295 if ((1 << i) & ch_mask)
296 continue;
297 txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
298 TXX9_IRQ_BASE + TX4939_IR_SIO(i),
299 i, sclk, (1 << i) & cts_mask);
300 }
301 }
302
303 #if IS_ENABLED(CONFIG_TC35815)
304 static u32 tx4939_get_eth_speed(struct net_device *dev)
305 {
306 struct ethtool_link_ksettings cmd;
307
308 if (__ethtool_get_link_ksettings(dev, &cmd))
309 return 100; /* default 100Mbps */
310
311 return cmd.base.speed;
312 }
313
314 static int tx4939_netdev_event(struct notifier_block *this,
315 unsigned long event,
316 void *ptr)
317 {
318 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
319
320 if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
321 __u64 bit = 0;
322 if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
323 bit = TX4939_PCFG_SPEED0;
324 else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
325 bit = TX4939_PCFG_SPEED1;
326 if (bit) {
327 if (tx4939_get_eth_speed(dev) == 100)
328 txx9_set64(&tx4939_ccfgptr->pcfg, bit);
329 else
330 txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
331 }
332 }
333 return NOTIFY_DONE;
334 }
335
336 static struct notifier_block tx4939_netdev_notifier = {
337 .notifier_call = tx4939_netdev_event,
338 .priority = 1,
339 };
340
341 void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
342 {
343 u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
344
345 if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
346 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
347 if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
348 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
349 register_netdevice_notifier(&tx4939_netdev_notifier);
350 }
351 #else
352 void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
353 {
354 }
355 #endif
356
357 void __init tx4939_mtd_init(int ch)
358 {
359 struct physmap_flash_data pdata = {
360 .width = TX4939_EBUSC_WIDTH(ch) / 8,
361 };
362 unsigned long start = txx9_ce_res[ch].start;
363 unsigned long size = txx9_ce_res[ch].end - start + 1;
364
365 if (!(TX4939_EBUSC_CR(ch) & 0x8))
366 return; /* disabled */
367 txx9_physmap_flash_init(ch, start, size, &pdata);
368 }
369
370 #define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
371 void __init tx4939_ata_init(void)
372 {
373 static struct resource ata0_res[] = {
374 {
375 .start = TX4939_ATA_REG_PHYS(0),
376 .end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
377 .flags = IORESOURCE_MEM,
378 }, {
379 .start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
380 .flags = IORESOURCE_IRQ,
381 },
382 };
383 static struct resource ata1_res[] = {
384 {
385 .start = TX4939_ATA_REG_PHYS(1),
386 .end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
387 .flags = IORESOURCE_MEM,
388 }, {
389 .start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
390 .flags = IORESOURCE_IRQ,
391 },
392 };
393 static struct platform_device ata0_dev = {
394 .name = "tx4939ide",
395 .id = 0,
396 .num_resources = ARRAY_SIZE(ata0_res),
397 .resource = ata0_res,
398 };
399 static struct platform_device ata1_dev = {
400 .name = "tx4939ide",
401 .id = 1,
402 .num_resources = ARRAY_SIZE(ata1_res),
403 .resource = ata1_res,
404 };
405 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
406
407 if (pcfg & TX4939_PCFG_ATA0MODE)
408 platform_device_register(&ata0_dev);
409 if ((pcfg & (TX4939_PCFG_ATA1MODE |
410 TX4939_PCFG_ET1MODE |
411 TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
412 platform_device_register(&ata1_dev);
413 }
414
415 void __init tx4939_rtc_init(void)
416 {
417 static struct resource res[] = {
418 {
419 .start = TX4939_RTC_REG & 0xfffffffffULL,
420 .end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1,
421 .flags = IORESOURCE_MEM,
422 }, {
423 .start = TXX9_IRQ_BASE + TX4939_IR_RTC,
424 .flags = IORESOURCE_IRQ,
425 },
426 };
427 static struct platform_device rtc_dev = {
428 .name = "tx4939rtc",
429 .id = -1,
430 .num_resources = ARRAY_SIZE(res),
431 .resource = res,
432 };
433
434 platform_device_register(&rtc_dev);
435 }
436
437 void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
438 unsigned char ch_mask, unsigned char wide_mask)
439 {
440 struct txx9ndfmc_platform_data plat_data = {
441 .shift = 1,
442 .gbus_clock = txx9_gbus_clock,
443 .hold = hold,
444 .spw = spw,
445 .flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD |
446 NDFMC_PLAT_FLAG_DUMMYWRITE,
447 .ch_mask = ch_mask,
448 .wide_mask = wide_mask,
449 };
450 txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data);
451 }
452
453 void __init tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1)
454 {
455 struct txx9dmac_platform_data plat_data = {
456 .have_64bit_regs = true,
457 };
458 int i;
459
460 for (i = 0; i < 2; i++) {
461 plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
462 txx9_dmac_init(i, TX4939_DMA_REG(i) & 0xfffffffffULL,
463 TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0),
464 &plat_data);
465 }
466 }
467
468 void __init tx4939_aclc_init(void)
469 {
470 u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
471
472 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_ACLC)
473 txx9_aclc_init(TX4939_ACLC_REG & 0xfffffffffULL,
474 TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1);
475 }
476
477 void __init tx4939_sramc_init(void)
478 {
479 if (tx4939_sram_resource.start)
480 txx9_sramc_init(&tx4939_sram_resource);
481 }
482
483 void __init tx4939_rng_init(void)
484 {
485 static struct resource res = {
486 .start = TX4939_RNG_REG & 0xfffffffffULL,
487 .end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1,
488 .flags = IORESOURCE_MEM,
489 };
490 static struct platform_device pdev = {
491 .name = "tx4939-rng",
492 .id = -1,
493 .num_resources = 1,
494 .resource = &res,
495 };
496
497 platform_device_register(&pdev);
498 }
499
500 static void __init tx4939_stop_unused_modules(void)
501 {
502 __u64 pcfg, rst = 0, ckd = 0;
503 char buf[128];
504
505 buf[0] = '\0';
506 local_irq_disable();
507 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
508 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
509 TX4939_PCFG_I2SMODE_ACLC) {
510 rst |= TX4939_CLKCTR_ACLRST;
511 ckd |= TX4939_CLKCTR_ACLCKD;
512 strcat(buf, " ACLC");
513 }
514 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
515 TX4939_PCFG_I2SMODE_I2S &&
516 (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
517 TX4939_PCFG_I2SMODE_I2S_ALT) {
518 rst |= TX4939_CLKCTR_I2SRST;
519 ckd |= TX4939_CLKCTR_I2SCKD;
520 strcat(buf, " I2S");
521 }
522 if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
523 rst |= TX4939_CLKCTR_ATA0RST;
524 ckd |= TX4939_CLKCTR_ATA0CKD;
525 strcat(buf, " ATA0");
526 }
527 if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
528 rst |= TX4939_CLKCTR_ATA1RST;
529 ckd |= TX4939_CLKCTR_ATA1CKD;
530 strcat(buf, " ATA1");
531 }
532 if (pcfg & TX4939_PCFG_SPIMODE) {
533 rst |= TX4939_CLKCTR_SPIRST;
534 ckd |= TX4939_CLKCTR_SPICKD;
535 strcat(buf, " SPI");
536 }
537 if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
538 rst |= TX4939_CLKCTR_VPCRST;
539 ckd |= TX4939_CLKCTR_VPCCKD;
540 strcat(buf, " VPC");
541 }
542 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
543 rst |= TX4939_CLKCTR_SIO2RST;
544 ckd |= TX4939_CLKCTR_SIO2CKD;
545 strcat(buf, " SIO2");
546 }
547 if (pcfg & TX4939_PCFG_SIO3MODE) {
548 rst |= TX4939_CLKCTR_SIO3RST;
549 ckd |= TX4939_CLKCTR_SIO3CKD;
550 strcat(buf, " SIO3");
551 }
552 if (rst | ckd) {
553 txx9_set64(&tx4939_ccfgptr->clkctr, rst);
554 txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
555 }
556 local_irq_enable();
557 if (buf[0])
558 pr_info("%s: stop%s\n", txx9_pcode_str, buf);
559 }
560
561 static int __init tx4939_late_init(void)
562 {
563 if (txx9_pcode != 0x4939)
564 return -ENODEV;
565 tx4939_stop_unused_modules();
566 return 0;
567 }
568 late_initcall(tx4939_late_init);
Linux with added FPC-III support