arch/powerpc/boot/dts/currituck.dts

   1 /*
   2  * Device Tree Source for IBM Embedded PPC 476 Platform
   3  *
   4  * Copyright © 2011 Tony Breeds IBM Corporation
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without
   8  * any warranty of any kind, whether express or implied.
   9  */
  10
  11 /dts-v1/;
  12
  13 /memreserve/ 0x01f00000 0x00100000;     // spin table
  14
  15 / {
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18         model = "ibm,currituck";
  19         compatible = "ibm,currituck";
  20         dcr-parent = <&{/cpus/cpu@0}>;
  21
  22         aliases {
  23                 serial0 = &UART0;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         model = "PowerPC,476";
  33                         reg = <0>;
  34                         clock-frequency = <1600000000>; // 1.6 GHz
  35                         timebase-frequency = <100000000>; // 100Mhz
  36                         i-cache-line-size = <32>;
  37                         d-cache-line-size = <32>;
  38                         i-cache-size = <32768>;
  39                         d-cache-size = <32768>;
  40                         dcr-controller;
  41                         dcr-access-method = "native";
  42                         status = "okay";
  43                 };
  44                 cpu@1 {
  45                         device_type = "cpu";
  46                         model = "PowerPC,476";
  47                         reg = <1>;
  48                         clock-frequency = <1600000000>; // 1.6 GHz
  49                         timebase-frequency = <100000000>; // 100Mhz
  50                         i-cache-line-size = <32>;
  51                         d-cache-line-size = <32>;
  52                         i-cache-size = <32768>;
  53                         d-cache-size = <32768>;
  54                         dcr-controller;
  55                         dcr-access-method = "native";
  56                         status = "disabled";
  57                         enable-method = "spin-table";
  58                         cpu-release-addr = <0x0 0x01f00000>;
  59                 };
  60         };
  61
  62         memory {
  63                 device_type = "memory";
  64                 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
  65         };
  66
  67         MPIC: interrupt-controller {
  68                 compatible = "chrp,open-pic";
  69                 interrupt-controller;
  70                 dcr-reg = <0xffc00000 0x00040000>;
  71                 #address-cells = <0>;
  72                 #size-cells = <0>;
  73                 #interrupt-cells = <2>;
  74
  75         };
  76
  77         plb {
  78                 compatible = "ibm,plb6";
  79                 #address-cells = <2>;
  80                 #size-cells = <2>;
  81                 ranges;
  82                 clock-frequency = <200000000>; // 200Mhz
  83
  84                 POB0: opb {
  85                         compatible = "ibm,opb-4xx", "ibm,opb";
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         /* Wish there was a nicer way of specifying a full
  89                          * 32-bit range
  90                          */
  91                         ranges = <0x00000000 0x00000200 0x00000000 0x80000000
  92                                   0x80000000 0x00000200 0x80000000 0x80000000>;
  93                         clock-frequency = <100000000>;
  94
  95                         UART0: serial@10000000 {
  96                                 device_type = "serial";
  97                                 compatible = "ns16750", "ns16550";
  98                                 reg = <0x10000000 0x00000008>;
  99                                 virtual-reg = <0xe1000000>;
 100                                 clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
 101                                 current-speed = <115200>;
 102                                 interrupt-parent = <&MPIC>;
 103                                 interrupts = <34 2>;
 104                         };
 105
 106                         FPGA0: fpga@50000000 {
 107                                 compatible = "ibm,currituck-fpga";
 108                                 reg = <0x50000000 0x4>;
 109                         };
 110
 111                         IIC0: i2c@0 {
 112                                 compatible = "ibm,iic-currituck", "ibm,iic";
 113                                 reg = <0x0 0x00000014>;
 114                                 interrupt-parent = <&MPIC>;
 115                                 interrupts = <79 2>;
 116                                 #address-cells = <1>;
 117                                 #size-cells = <0>;
 118                                 rtc@68 {
 119                                         compatible = "st,m41t80", "m41st85";
 120                                         reg = <0x68>;
 121                                 };
 122                         };
 123                 };
 124
 125                 PCIE0: pcie@10100000000 {               // 4xGBIF1
 126                         device_type = "pci";
 127                         #interrupt-cells = <1>;
 128                         #size-cells = <2>;
 129                         #address-cells = <3>;
 130                         compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
 131                         primary;
 132                         port = <0x0>; /* port number */
 133                         reg = <0x00000101 0x00000000 0x0 0x10000000             /* Config space access */
 134                                0x00000100 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
 135                         dcr-reg = <0x80 0x20>;
 136
 137 //                                pci_space  < pci_addr          > < cpu_addr          > < size       >
 138                         ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
 139                                   0x01000000 0x0        0x0        0x00000140 0x0        0x0 0x00010000>;
 140
 141                         /* Inbound starting at 0 to memsize filled in by zImage */
 142                         dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
 143
 144                         /* This drives busses 0 to 0xf */
 145                         bus-range = <0x0 0xf>;
 146
 147                         /* Legacy interrupts (note the weird polarity, the bridge seems
 148                          * to invert PCIe legacy interrupts).
 149                          * We are de-swizzling here because the numbers are actually for
 150                          * port of the root complex virtual P2P bridge. But I want
 151                          * to avoid putting a node for it in the tree, so the numbers
 152                          * below are basically de-swizzled numbers.
 153                          * The real slot is on idsel 0, so the swizzling is 1:1
 154                          */
 155                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 156                         interrupt-map = <
 157                                 0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
 158                                 0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
 159                                 0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
 160                                 0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
 161                 };
 162
 163                 PCIE1: pcie@30100000000 {               // 4xGBIF0
 164                         device_type = "pci";
 165                         #interrupt-cells = <1>;
 166                         #size-cells = <2>;
 167                         #address-cells = <3>;
 168                         compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
 169                         primary;
 170                         port = <0x1>; /* port number */
 171                         reg = <0x00000301 0x00000000 0x0 0x10000000             /* Config space access */
 172                                0x00000300 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
 173                         dcr-reg = <0x60 0x20>;
 174
 175                         ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
 176                                   0x01000000 0x0        0x0        0x00000340 0x0        0x0 0x00010000>;
 177
 178                         /* Inbound starting at 0 to memsize filled in by zImage */
 179                         dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
 180
 181                         /* This drives busses 0 to 0xf */
 182                         bus-range = <0x0 0xf>;
 183
 184                         /* Legacy interrupts (note the weird polarity, the bridge seems
 185                          * to invert PCIe legacy interrupts).
 186                          * We are de-swizzling here because the numbers are actually for
 187                          * port of the root complex virtual P2P bridge. But I want
 188                          * to avoid putting a node for it in the tree, so the numbers
 189                          * below are basically de-swizzled numbers.
 190                          * The real slot is on idsel 0, so the swizzling is 1:1
 191                          */
 192                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 193                         interrupt-map = <
 194                                 0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
 195                                 0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
 196                                 0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
 197                                 0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
 198                 };
 199
 200                 PCIE2: pcie@38100000000 {               // 2xGBIF0
 201                         device_type = "pci";
 202                         #interrupt-cells = <1>;
 203                         #size-cells = <2>;
 204                         #address-cells = <3>;
 205                         compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
 206                         primary;
 207                         port = <0x2>; /* port number */
 208                         reg = <0x00000381 0x00000000 0x0 0x10000000             /* Config space access */
 209                                0x00000380 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
 210                         dcr-reg = <0xA0 0x20>;
 211
 212                         ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
 213                                   0x01000000 0x0        0x0        0x000003C0 0x0        0x0 0x00010000>;
 214
 215                         /* Inbound starting at 0 to memsize filled in by zImage */
 216                         dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
 217
 218                         /* This drives busses 0 to 0xf */
 219                         bus-range = <0x0 0xf>;
 220
 221                         /* Legacy interrupts (note the weird polarity, the bridge seems
 222                          * to invert PCIe legacy interrupts).
 223                          * We are de-swizzling here because the numbers are actually for
 224                          * port of the root complex virtual P2P bridge. But I want
 225                          * to avoid putting a node for it in the tree, so the numbers
 226                          * below are basically de-swizzled numbers.
 227                          * The real slot is on idsel 0, so the swizzling is 1:1
 228                          */
 229                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 230                         interrupt-map = <
 231                                 0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
 232                                 0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
 233                                 0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
 234                                 0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
 235                 };
 236
 237         };
 238
 239         chosen {
 240                 stdout-path = &UART0;
 241         };
 242 };