| blob | 6c8cb859c55f830c4e7a6d4b86c1bdd785b596fa |
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC8349E MDS Device Tree Source
4 *
5 * Copyright 2005, 2006 Freescale Semiconductor Inc.
6 */
8 /dts-v1/;
10 / {
11 model = "MPC8349EMDS";
12 compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
13 #address-cells = <1>;
14 #size-cells = <1>;
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 serial0 = &serial0;
20 serial1 = &serial1;
21 pci0 = &pci0;
22 pci1 = &pci1;
23 };
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
29 PowerPC,8349@0 {
30 device_type = "cpu";
31 reg = <0x0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <32768>;
35 i-cache-size = <32768>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
39 };
40 };
42 memory {
43 device_type = "memory";
44 reg = <0x00000000 0x10000000>; // 256MB at 0
45 };
47 bcsr@e2400000 {
48 compatible = "fsl,mpc8349mds-bcsr";
49 reg = <0xe2400000 0x8000>;
50 };
52 soc8349@e0000000 {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 device_type = "soc";
56 compatible = "simple-bus";
57 ranges = <0x0 0xe0000000 0x00100000>;
58 reg = <0xe0000000 0x00000200>;
59 bus-frequency = <0>;
61 wdt@200 {
62 device_type = "watchdog";
63 compatible = "mpc83xx_wdt";
64 reg = <0x200 0x100>;
65 };
67 i2c@3000 {
68 #address-cells = <1>;
69 #size-cells = <0>;
70 cell-index = <0>;
71 compatible = "fsl-i2c";
72 reg = <0x3000 0x100>;
73 interrupts = <14 0x8>;
74 interrupt-parent = <&ipic>;
75 dfsrr;
77 rtc@68 {
78 compatible = "dallas,ds1374";
79 reg = <0x68>;
80 };
81 };
83 i2c@3100 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <1>;
87 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>;
89 interrupts = <15 0x8>;
90 interrupt-parent = <&ipic>;
91 dfsrr;
92 };
94 spi@7000 {
95 cell-index = <0>;
96 compatible = "fsl,spi";
97 reg = <0x7000 0x1000>;
98 interrupts = <16 0x8>;
99 interrupt-parent = <&ipic>;
100 mode = "cpu";
101 };
103 dma@82a8 {
104 #address-cells = <1>;
105 #size-cells = <1>;
106 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
107 reg = <0x82a8 4>;
108 ranges = <0 0x8100 0x1a8>;
109 interrupt-parent = <&ipic>;
110 interrupts = <71 8>;
111 cell-index = <0>;
112 dma-channel@0 {
113 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
114 reg = <0 0x80>;
115 cell-index = <0>;
116 interrupt-parent = <&ipic>;
117 interrupts = <71 8>;
118 };
119 dma-channel@80 {
120 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
121 reg = <0x80 0x80>;
122 cell-index = <1>;
123 interrupt-parent = <&ipic>;
124 interrupts = <71 8>;
125 };
126 dma-channel@100 {
127 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
128 reg = <0x100 0x80>;
129 cell-index = <2>;
130 interrupt-parent = <&ipic>;
131 interrupts = <71 8>;
132 };
133 dma-channel@180 {
134 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
135 reg = <0x180 0x28>;
136 cell-index = <3>;
137 interrupt-parent = <&ipic>;
138 interrupts = <71 8>;
139 };
140 };
142 /* phy type (ULPI or SERIAL) are only types supported for MPH */
143 /* port = 0 or 1 */
144 usb@22000 {
145 compatible = "fsl-usb2-mph";
146 reg = <0x22000 0x1000>;
147 #address-cells = <1>;
148 #size-cells = <0>;
149 interrupt-parent = <&ipic>;
150 interrupts = <39 0x8>;
151 phy_type = "ulpi";
152 port0;
153 };
154 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
155 usb@23000 {
156 compatible = "fsl-usb2-dr";
157 reg = <0x23000 0x1000>;
158 #address-cells = <1>;
159 #size-cells = <0>;
160 interrupt-parent = <&ipic>;
161 interrupts = <38 0x8>;
162 dr_mode = "otg";
163 phy_type = "ulpi";
164 };
166 enet0: ethernet@24000 {
167 #address-cells = <1>;
168 #size-cells = <1>;
169 cell-index = <0>;
170 device_type = "network";
171 model = "TSEC";
172 compatible = "gianfar";
173 reg = <0x24000 0x1000>;
174 ranges = <0x0 0x24000 0x1000>;
175 local-mac-address = [ 00 00 00 00 00 00 ];
176 interrupts = <32 0x8 33 0x8 34 0x8>;
177 interrupt-parent = <&ipic>;
178 tbi-handle = <&tbi0>;
179 phy-handle = <&phy0>;
180 linux,network-index = <0>;
182 mdio@520 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,gianfar-mdio";
186 reg = <0x520 0x20>;
188 phy0: ethernet-phy@0 {
189 interrupt-parent = <&ipic>;
190 interrupts = <17 0x8>;
191 reg = <0x0>;
192 };
194 phy1: ethernet-phy@1 {
195 interrupt-parent = <&ipic>;
196 interrupts = <18 0x8>;
197 reg = <0x1>;
198 };
200 tbi0: tbi-phy@11 {
201 reg = <0x11>;
202 device_type = "tbi-phy";
203 };
204 };
205 };
207 enet1: ethernet@25000 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 cell-index = <1>;
211 device_type = "network";
212 model = "TSEC";
213 compatible = "gianfar";
214 reg = <0x25000 0x1000>;
215 ranges = <0x0 0x25000 0x1000>;
216 local-mac-address = [ 00 00 00 00 00 00 ];
217 interrupts = <35 0x8 36 0x8 37 0x8>;
218 interrupt-parent = <&ipic>;
219 tbi-handle = <&tbi1>;
220 phy-handle = <&phy1>;
221 linux,network-index = <1>;
223 mdio@520 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "fsl,gianfar-tbi";
227 reg = <0x520 0x20>;
229 tbi1: tbi-phy@11 {
230 reg = <0x11>;
231 device_type = "tbi-phy";
232 };
233 };
234 };
236 serial0: serial@4500 {
237 cell-index = <0>;
238 device_type = "serial";
239 compatible = "fsl,ns16550", "ns16550";
240 reg = <0x4500 0x100>;
241 clock-frequency = <0>;
242 interrupts = <9 0x8>;
243 interrupt-parent = <&ipic>;
244 };
246 serial1: serial@4600 {
247 cell-index = <1>;
248 device_type = "serial";
249 compatible = "fsl,ns16550", "ns16550";
250 reg = <0x4600 0x100>;
251 clock-frequency = <0>;
252 interrupts = <10 0x8>;
253 interrupt-parent = <&ipic>;
254 };
256 crypto@30000 {
257 compatible = "fsl,sec2.0";
258 reg = <0x30000 0x10000>;
259 interrupts = <11 0x8>;
260 interrupt-parent = <&ipic>;
261 fsl,num-channels = <4>;
262 fsl,channel-fifo-len = <24>;
263 fsl,exec-units-mask = <0x7e>;
264 fsl,descriptor-types-mask = <0x01010ebf>;
265 };
267 /* IPIC
268 * interrupts cell = <intr #, sense>
269 * sense values match linux IORESOURCE_IRQ_* defines:
270 * sense == 8: Level, low assertion
271 * sense == 2: Edge, high-to-low change
272 */
273 ipic: pic@700 {
274 interrupt-controller;
275 #address-cells = <0>;
276 #interrupt-cells = <2>;
277 reg = <0x700 0x100>;
278 device_type = "ipic";
279 };
280 };
282 pci0: pci@e0008500 {
283 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
284 interrupt-map = <
286 /* IDSEL 0x11 */
287 0x8800 0x0 0x0 0x1 &ipic 20 0x8
288 0x8800 0x0 0x0 0x2 &ipic 21 0x8
289 0x8800 0x0 0x0 0x3 &ipic 22 0x8
290 0x8800 0x0 0x0 0x4 &ipic 23 0x8
292 /* IDSEL 0x12 */
293 0x9000 0x0 0x0 0x1 &ipic 22 0x8
294 0x9000 0x0 0x0 0x2 &ipic 23 0x8
295 0x9000 0x0 0x0 0x3 &ipic 20 0x8
296 0x9000 0x0 0x0 0x4 &ipic 21 0x8
298 /* IDSEL 0x13 */
299 0x9800 0x0 0x0 0x1 &ipic 23 0x8
300 0x9800 0x0 0x0 0x2 &ipic 20 0x8
301 0x9800 0x0 0x0 0x3 &ipic 21 0x8
302 0x9800 0x0 0x0 0x4 &ipic 22 0x8
304 /* IDSEL 0x15 */
305 0xa800 0x0 0x0 0x1 &ipic 20 0x8
306 0xa800 0x0 0x0 0x2 &ipic 21 0x8
307 0xa800 0x0 0x0 0x3 &ipic 22 0x8
308 0xa800 0x0 0x0 0x4 &ipic 23 0x8
310 /* IDSEL 0x16 */
311 0xb000 0x0 0x0 0x1 &ipic 23 0x8
312 0xb000 0x0 0x0 0x2 &ipic 20 0x8
313 0xb000 0x0 0x0 0x3 &ipic 21 0x8
314 0xb000 0x0 0x0 0x4 &ipic 22 0x8
316 /* IDSEL 0x17 */
317 0xb800 0x0 0x0 0x1 &ipic 22 0x8
318 0xb800 0x0 0x0 0x2 &ipic 23 0x8
319 0xb800 0x0 0x0 0x3 &ipic 20 0x8
320 0xb800 0x0 0x0 0x4 &ipic 21 0x8
322 /* IDSEL 0x18 */
323 0xc000 0x0 0x0 0x1 &ipic 21 0x8
324 0xc000 0x0 0x0 0x2 &ipic 22 0x8
325 0xc000 0x0 0x0 0x3 &ipic 23 0x8
326 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
327 interrupt-parent = <&ipic>;
328 interrupts = <66 0x8>;
329 bus-range = <0 0>;
330 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
331 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
332 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
333 clock-frequency = <66666666>;
334 #interrupt-cells = <1>;
335 #size-cells = <2>;
336 #address-cells = <3>;
337 reg = <0xe0008500 0x100 /* internal registers */
338 0xe0008300 0x8>; /* config space access registers */
339 compatible = "fsl,mpc8349-pci";
340 device_type = "pci";
341 };
343 pci1: pci@e0008600 {
344 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
345 interrupt-map = <
347 /* IDSEL 0x11 */
348 0x8800 0x0 0x0 0x1 &ipic 20 0x8
349 0x8800 0x0 0x0 0x2 &ipic 21 0x8
350 0x8800 0x0 0x0 0x3 &ipic 22 0x8
351 0x8800 0x0 0x0 0x4 &ipic 23 0x8
353 /* IDSEL 0x12 */
354 0x9000 0x0 0x0 0x1 &ipic 22 0x8
355 0x9000 0x0 0x0 0x2 &ipic 23 0x8
356 0x9000 0x0 0x0 0x3 &ipic 20 0x8
357 0x9000 0x0 0x0 0x4 &ipic 21 0x8
359 /* IDSEL 0x13 */
360 0x9800 0x0 0x0 0x1 &ipic 23 0x8
361 0x9800 0x0 0x0 0x2 &ipic 20 0x8
362 0x9800 0x0 0x0 0x3 &ipic 21 0x8
363 0x9800 0x0 0x0 0x4 &ipic 22 0x8
365 /* IDSEL 0x15 */
366 0xa800 0x0 0x0 0x1 &ipic 20 0x8
367 0xa800 0x0 0x0 0x2 &ipic 21 0x8
368 0xa800 0x0 0x0 0x3 &ipic 22 0x8
369 0xa800 0x0 0x0 0x4 &ipic 23 0x8
371 /* IDSEL 0x16 */
372 0xb000 0x0 0x0 0x1 &ipic 23 0x8
373 0xb000 0x0 0x0 0x2 &ipic 20 0x8
374 0xb000 0x0 0x0 0x3 &ipic 21 0x8
375 0xb000 0x0 0x0 0x4 &ipic 22 0x8
377 /* IDSEL 0x17 */
378 0xb800 0x0 0x0 0x1 &ipic 22 0x8
379 0xb800 0x0 0x0 0x2 &ipic 23 0x8
380 0xb800 0x0 0x0 0x3 &ipic 20 0x8
381 0xb800 0x0 0x0 0x4 &ipic 21 0x8
383 /* IDSEL 0x18 */
384 0xc000 0x0 0x0 0x1 &ipic 21 0x8
385 0xc000 0x0 0x0 0x2 &ipic 22 0x8
386 0xc000 0x0 0x0 0x3 &ipic 23 0x8
387 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
388 interrupt-parent = <&ipic>;
389 interrupts = <67 0x8>;
390 bus-range = <0 0>;
391 ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
392 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
393 0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
394 clock-frequency = <66666666>;
395 #interrupt-cells = <1>;
396 #size-cells = <2>;
397 #address-cells = <3>;
398 reg = <0xe0008600 0x100 /* internal registers */
399 0xe0008380 0x8>; /* config space access registers */
400 compatible = "fsl,mpc8349-pci";
401 device_type = "pci";
402 };
403 };