| blob | d8e7d40aeae449e33ea1640a53ee4dfec7d746a4 |
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC8377E WLAN Device Tree Source
4 *
5 * Copyright 2007-2009 Freescale Semiconductor Inc.
6 * Copyright 2009 MontaVista Software, Inc.
7 */
9 /dts-v1/;
11 / {
12 compatible = "fsl,mpc8377wlan";
13 #address-cells = <1>;
14 #size-cells = <1>;
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 serial0 = &serial0;
20 serial1 = &serial1;
21 pci0 = &pci0;
22 pci1 = &pci1;
23 pci2 = &pci2;
24 };
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
30 PowerPC,8377@0 {
31 device_type = "cpu";
32 reg = <0x0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
35 d-cache-size = <32768>;
36 i-cache-size = <32768>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
40 };
41 };
43 memory {
44 device_type = "memory";
45 reg = <0x00000000 0x20000000>; // 512MB at 0
46 };
48 localbus@e0005000 {
49 #address-cells = <2>;
50 #size-cells = <1>;
51 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
54 interrupt-parent = <&ipic>;
55 ranges = <0x0 0x0 0xfc000000 0x04000000>;
57 flash@0,0 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "cfi-flash";
61 reg = <0x0 0x0 0x4000000>;
62 bank-width = <2>;
63 device-width = <1>;
65 partition@0 {
66 reg = <0 0x80000>;
67 label = "u-boot";
68 read-only;
69 };
71 partition@a0000 {
72 reg = <0xa0000 0x300000>;
73 label = "kernel";
74 };
76 partition@3a0000 {
77 reg = <0x3a0000 0x3c60000>;
78 label = "rootfs";
79 };
80 };
81 };
83 immr@e0000000 {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 device_type = "soc";
87 compatible = "simple-bus";
88 ranges = <0x0 0xe0000000 0x00100000>;
89 reg = <0xe0000000 0x00000200>;
90 bus-frequency = <0>;
92 wdt@200 {
93 device_type = "watchdog";
94 compatible = "mpc83xx_wdt";
95 reg = <0x200 0x100>;
96 };
98 gpio1: gpio-controller@c00 {
99 #gpio-cells = <2>;
100 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
101 reg = <0xc00 0x100>;
102 interrupts = <74 0x8>;
103 interrupt-parent = <&ipic>;
104 gpio-controller;
105 };
107 gpio2: gpio-controller@d00 {
108 #gpio-cells = <2>;
109 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
110 reg = <0xd00 0x100>;
111 interrupts = <75 0x8>;
112 interrupt-parent = <&ipic>;
113 gpio-controller;
114 };
116 sleep-nexus {
117 #address-cells = <1>;
118 #size-cells = <1>;
119 compatible = "simple-bus";
120 sleep = <&pmc 0x0c000000>;
121 ranges;
123 i2c@3000 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 cell-index = <0>;
127 compatible = "fsl-i2c";
128 reg = <0x3000 0x100>;
129 interrupts = <14 0x8>;
130 interrupt-parent = <&ipic>;
131 dfsrr;
133 at24@50 {
134 compatible = "atmel,24c256";
135 reg = <0x50>;
136 };
138 rtc@68 {
139 compatible = "dallas,ds1339";
140 reg = <0x68>;
141 };
142 };
144 sdhci@2e000 {
145 compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
146 reg = <0x2e000 0x1000>;
147 interrupts = <42 0x8>;
148 interrupt-parent = <&ipic>;
149 sdhci,wp-inverted;
150 clock-frequency = <133333333>;
151 };
152 };
154 i2c@3100 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 cell-index = <1>;
158 compatible = "fsl-i2c";
159 reg = <0x3100 0x100>;
160 interrupts = <15 0x8>;
161 interrupt-parent = <&ipic>;
162 dfsrr;
163 };
165 spi@7000 {
166 cell-index = <0>;
167 compatible = "fsl,spi";
168 reg = <0x7000 0x1000>;
169 interrupts = <16 0x8>;
170 interrupt-parent = <&ipic>;
171 mode = "cpu";
172 };
174 dma@82a8 {
175 #address-cells = <1>;
176 #size-cells = <1>;
177 compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
178 reg = <0x82a8 4>;
179 ranges = <0 0x8100 0x1a8>;
180 interrupt-parent = <&ipic>;
181 interrupts = <71 8>;
182 cell-index = <0>;
183 dma-channel@0 {
184 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
185 reg = <0 0x80>;
186 cell-index = <0>;
187 interrupt-parent = <&ipic>;
188 interrupts = <71 8>;
189 };
190 dma-channel@80 {
191 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
192 reg = <0x80 0x80>;
193 cell-index = <1>;
194 interrupt-parent = <&ipic>;
195 interrupts = <71 8>;
196 };
197 dma-channel@100 {
198 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
199 reg = <0x100 0x80>;
200 cell-index = <2>;
201 interrupt-parent = <&ipic>;
202 interrupts = <71 8>;
203 };
204 dma-channel@180 {
205 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
206 reg = <0x180 0x28>;
207 cell-index = <3>;
208 interrupt-parent = <&ipic>;
209 interrupts = <71 8>;
210 };
211 };
213 usb@23000 {
214 compatible = "fsl-usb2-dr";
215 reg = <0x23000 0x1000>;
216 #address-cells = <1>;
217 #size-cells = <0>;
218 interrupt-parent = <&ipic>;
219 interrupts = <38 0x8>;
220 phy_type = "ulpi";
221 sleep = <&pmc 0x00c00000>;
222 };
224 enet0: ethernet@24000 {
225 #address-cells = <1>;
226 #size-cells = <1>;
227 cell-index = <0>;
228 device_type = "network";
229 model = "eTSEC";
230 compatible = "gianfar";
231 reg = <0x24000 0x1000>;
232 ranges = <0x0 0x24000 0x1000>;
233 local-mac-address = [ 00 00 00 00 00 00 ];
234 interrupts = <32 0x8 33 0x8 34 0x8>;
235 phy-connection-type = "mii";
236 interrupt-parent = <&ipic>;
237 tbi-handle = <&tbi0>;
238 phy-handle = <&phy2>;
239 sleep = <&pmc 0xc0000000>;
240 fsl,magic-packet;
242 mdio@520 {
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "fsl,gianfar-mdio";
246 reg = <0x520 0x20>;
248 phy2: ethernet-phy@2 {
249 interrupt-parent = <&ipic>;
250 interrupts = <17 0x8>;
251 reg = <0x2>;
252 };
254 phy3: ethernet-phy@3 {
255 interrupt-parent = <&ipic>;
256 interrupts = <18 0x8>;
257 reg = <0x3>;
258 };
260 tbi0: tbi-phy@11 {
261 reg = <0x11>;
262 device_type = "tbi-phy";
263 };
264 };
265 };
267 enet1: ethernet@25000 {
268 #address-cells = <1>;
269 #size-cells = <1>;
270 cell-index = <1>;
271 device_type = "network";
272 model = "eTSEC";
273 compatible = "gianfar";
274 reg = <0x25000 0x1000>;
275 ranges = <0x0 0x25000 0x1000>;
276 local-mac-address = [ 00 00 00 00 00 00 ];
277 interrupts = <35 0x8 36 0x8 37 0x8>;
278 phy-connection-type = "mii";
279 interrupt-parent = <&ipic>;
280 phy-handle = <&phy3>;
281 tbi-handle = <&tbi1>;
282 sleep = <&pmc 0x30000000>;
283 fsl,magic-packet;
285 mdio@520 {
286 #address-cells = <1>;
287 #size-cells = <0>;
288 compatible = "fsl,gianfar-tbi";
289 reg = <0x520 0x20>;
291 tbi1: tbi-phy@11 {
292 reg = <0x11>;
293 device_type = "tbi-phy";
294 };
295 };
296 };
298 serial0: serial@4500 {
299 cell-index = <0>;
300 device_type = "serial";
301 compatible = "fsl,ns16550", "ns16550";
302 reg = <0x4500 0x100>;
303 clock-frequency = <0>;
304 interrupts = <9 0x8>;
305 interrupt-parent = <&ipic>;
306 };
308 serial1: serial@4600 {
309 cell-index = <1>;
310 device_type = "serial";
311 compatible = "fsl,ns16550", "ns16550";
312 reg = <0x4600 0x100>;
313 clock-frequency = <0>;
314 interrupts = <10 0x8>;
315 interrupt-parent = <&ipic>;
316 };
318 crypto@30000 {
319 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
320 "fsl,sec2.1", "fsl,sec2.0";
321 reg = <0x30000 0x10000>;
322 interrupts = <11 0x8>;
323 interrupt-parent = <&ipic>;
324 fsl,num-channels = <4>;
325 fsl,channel-fifo-len = <24>;
326 fsl,exec-units-mask = <0x9fe>;
327 fsl,descriptor-types-mask = <0x3ab0ebf>;
328 sleep = <&pmc 0x03000000>;
329 };
331 sata@18000 {
332 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
333 reg = <0x18000 0x1000>;
334 interrupts = <44 0x8>;
335 interrupt-parent = <&ipic>;
336 sleep = <&pmc 0x000000c0>;
337 };
339 sata@19000 {
340 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
341 reg = <0x19000 0x1000>;
342 interrupts = <45 0x8>;
343 interrupt-parent = <&ipic>;
344 sleep = <&pmc 0x00000030>;
345 };
347 /* IPIC
348 * interrupts cell = <intr #, sense>
349 * sense values match linux IORESOURCE_IRQ_* defines:
350 * sense == 8: Level, low assertion
351 * sense == 2: Edge, high-to-low change
352 */
353 ipic: interrupt-controller@700 {
354 compatible = "fsl,ipic";
355 interrupt-controller;
356 #address-cells = <0>;
357 #interrupt-cells = <2>;
358 reg = <0x700 0x100>;
359 };
361 pmc: power@b00 {
362 compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
363 reg = <0xb00 0x100 0xa00 0x100>;
364 interrupts = <80 0x8>;
365 interrupt-parent = <&ipic>;
366 };
367 };
369 pci0: pci@e0008500 {
370 interrupt-map-mask = <0xf800 0 0 7>;
371 interrupt-map = <
372 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
374 /* IDSEL AD14 IRQ6 inta */
375 0x7000 0x0 0x0 0x1 &ipic 22 0x8
377 /* IDSEL AD15 IRQ5 inta */
378 0x7800 0x0 0x0 0x1 &ipic 21 0x8>;
379 interrupt-parent = <&ipic>;
380 interrupts = <66 0x8>;
381 bus-range = <0 0>;
382 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
383 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
384 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
385 sleep = <&pmc 0x00010000>;
386 clock-frequency = <66666666>;
387 #interrupt-cells = <1>;
388 #size-cells = <2>;
389 #address-cells = <3>;
390 reg = <0xe0008500 0x100 /* internal registers */
391 0xe0008300 0x8>; /* config space access registers */
392 compatible = "fsl,mpc8349-pci";
393 device_type = "pci";
394 };
396 pci1: pcie@e0009000 {
397 #address-cells = <3>;
398 #size-cells = <2>;
399 #interrupt-cells = <1>;
400 device_type = "pci";
401 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
402 reg = <0xe0009000 0x00001000>;
403 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
404 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
405 bus-range = <0 255>;
406 interrupt-map-mask = <0xf800 0 0 7>;
407 interrupt-map = <0 0 0 1 &ipic 1 8
408 0 0 0 2 &ipic 1 8
409 0 0 0 3 &ipic 1 8
410 0 0 0 4 &ipic 1 8>;
411 sleep = <&pmc 0x00300000>;
412 clock-frequency = <0>;
414 pcie@0 {
415 #address-cells = <3>;
416 #size-cells = <2>;
417 device_type = "pci";
418 reg = <0 0 0 0 0>;
419 ranges = <0x02000000 0 0xa8000000
420 0x02000000 0 0xa8000000
421 0 0x10000000
422 0x01000000 0 0x00000000
423 0x01000000 0 0x00000000
424 0 0x00800000>;
425 };
426 };
428 pci2: pcie@e000a000 {
429 #address-cells = <3>;
430 #size-cells = <2>;
431 #interrupt-cells = <1>;
432 device_type = "pci";
433 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
434 reg = <0xe000a000 0x00001000>;
435 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
436 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
437 bus-range = <0 255>;
438 interrupt-map-mask = <0xf800 0 0 7>;
439 interrupt-map = <0 0 0 1 &ipic 2 8
440 0 0 0 2 &ipic 2 8
441 0 0 0 3 &ipic 2 8
442 0 0 0 4 &ipic 2 8>;
443 sleep = <&pmc 0x000c0000>;
444 clock-frequency = <0>;
446 pcie@0 {
447 #address-cells = <3>;
448 #size-cells = <2>;
449 device_type = "pci";
450 reg = <0 0 0 0 0>;
451 ranges = <0x02000000 0 0xc8000000
452 0x02000000 0 0xc8000000
453 0 0x10000000
454 0x01000000 0 0x00000000
455 0x01000000 0 0x00000000
456 0 0x00800000>;
457 };
458 };
459 };