| blob | f7379a1cbb6c79a15047bfa7218b6b2a301f25b1 |
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC8379E MDS Device Tree Source
4 *
5 * Copyright 2007 Freescale Semiconductor Inc.
6 */
8 /dts-v1/;
10 / {
11 model = "fsl,mpc8379emds";
12 compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
13 #address-cells = <1>;
14 #size-cells = <1>;
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 serial0 = &serial0;
20 serial1 = &serial1;
21 pci0 = &pci0;
22 };
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
28 PowerPC,8379@0 {
29 device_type = "cpu";
30 reg = <0x0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <32768>;
34 i-cache-size = <32768>;
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
38 };
39 };
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x20000000>; // 512MB at 0
44 };
46 localbus@e0005000 {
47 #address-cells = <2>;
48 #size-cells = <1>;
49 compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
52 interrupt-parent = <&ipic>;
54 // booting from NOR flash
55 ranges = <0 0x0 0xfe000000 0x02000000
56 1 0x0 0xf8000000 0x00008000
57 3 0x0 0xe0600000 0x00008000>;
59 flash@0,0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "cfi-flash";
63 reg = <0 0x0 0x2000000>;
64 bank-width = <2>;
65 device-width = <1>;
67 u-boot@0 {
68 reg = <0x0 0x100000>;
69 read-only;
70 };
72 fs@100000 {
73 reg = <0x100000 0x800000>;
74 };
76 kernel@1d00000 {
77 reg = <0x1d00000 0x200000>;
78 };
80 dtb@1f00000 {
81 reg = <0x1f00000 0x100000>;
82 };
83 };
85 bcsr@1,0 {
86 reg = <1 0x0 0x8000>;
87 compatible = "fsl,mpc837xmds-bcsr";
88 };
90 nand@3,0 {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "fsl,mpc8379-fcm-nand",
94 "fsl,elbc-fcm-nand";
95 reg = <3 0x0 0x8000>;
97 u-boot@0 {
98 reg = <0x0 0x100000>;
99 read-only;
100 };
102 kernel@100000 {
103 reg = <0x100000 0x300000>;
104 };
106 fs@400000 {
107 reg = <0x400000 0x1c00000>;
108 };
109 };
110 };
112 soc@e0000000 {
113 #address-cells = <1>;
114 #size-cells = <1>;
115 device_type = "soc";
116 compatible = "simple-bus";
117 ranges = <0x0 0xe0000000 0x00100000>;
118 reg = <0xe0000000 0x00000200>;
119 bus-frequency = <0>;
121 wdt@200 {
122 compatible = "mpc83xx_wdt";
123 reg = <0x200 0x100>;
124 };
126 sleep-nexus {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "simple-bus";
130 sleep = <&pmc 0x0c000000>;
131 ranges;
133 i2c@3000 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 cell-index = <0>;
137 compatible = "fsl-i2c";
138 reg = <0x3000 0x100>;
139 interrupts = <14 0x8>;
140 interrupt-parent = <&ipic>;
141 dfsrr;
143 rtc@68 {
144 compatible = "dallas,ds1374";
145 reg = <0x68>;
146 interrupts = <19 0x8>;
147 interrupt-parent = <&ipic>;
148 };
149 };
151 sdhci@2e000 {
152 compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
153 reg = <0x2e000 0x1000>;
154 interrupts = <42 0x8>;
155 interrupt-parent = <&ipic>;
156 sdhci,wp-inverted;
157 /* Filled in by U-Boot */
158 clock-frequency = <0>;
159 };
160 };
162 i2c@3100 {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 cell-index = <1>;
166 compatible = "fsl-i2c";
167 reg = <0x3100 0x100>;
168 interrupts = <15 0x8>;
169 interrupt-parent = <&ipic>;
170 dfsrr;
171 };
173 spi@7000 {
174 cell-index = <0>;
175 compatible = "fsl,spi";
176 reg = <0x7000 0x1000>;
177 interrupts = <16 0x8>;
178 interrupt-parent = <&ipic>;
179 mode = "cpu";
180 };
182 dma@82a8 {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
186 reg = <0x82a8 4>;
187 ranges = <0 0x8100 0x1a8>;
188 interrupt-parent = <&ipic>;
189 interrupts = <71 8>;
190 cell-index = <0>;
191 dma-channel@0 {
192 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
193 reg = <0 0x80>;
194 cell-index = <0>;
195 interrupt-parent = <&ipic>;
196 interrupts = <71 8>;
197 };
198 dma-channel@80 {
199 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
200 reg = <0x80 0x80>;
201 cell-index = <1>;
202 interrupt-parent = <&ipic>;
203 interrupts = <71 8>;
204 };
205 dma-channel@100 {
206 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
207 reg = <0x100 0x80>;
208 cell-index = <2>;
209 interrupt-parent = <&ipic>;
210 interrupts = <71 8>;
211 };
212 dma-channel@180 {
213 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
214 reg = <0x180 0x28>;
215 cell-index = <3>;
216 interrupt-parent = <&ipic>;
217 interrupts = <71 8>;
218 };
219 };
221 usb@23000 {
222 compatible = "fsl-usb2-dr";
223 reg = <0x23000 0x1000>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 interrupt-parent = <&ipic>;
227 interrupts = <38 0x8>;
228 dr_mode = "host";
229 phy_type = "ulpi";
230 sleep = <&pmc 0x00c00000>;
231 };
233 enet0: ethernet@24000 {
234 #address-cells = <1>;
235 #size-cells = <1>;
236 cell-index = <0>;
237 device_type = "network";
238 model = "eTSEC";
239 compatible = "gianfar";
240 reg = <0x24000 0x1000>;
241 ranges = <0x0 0x24000 0x1000>;
242 local-mac-address = [ 00 00 00 00 00 00 ];
243 interrupts = <32 0x8 33 0x8 34 0x8>;
244 phy-connection-type = "mii";
245 interrupt-parent = <&ipic>;
246 tbi-handle = <&tbi0>;
247 phy-handle = <&phy2>;
248 sleep = <&pmc 0xc0000000>;
249 fsl,magic-packet;
251 mdio@520 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "fsl,gianfar-mdio";
255 reg = <0x520 0x20>;
257 phy2: ethernet-phy@2 {
258 interrupt-parent = <&ipic>;
259 interrupts = <17 0x8>;
260 reg = <0x2>;
261 };
263 phy3: ethernet-phy@3 {
264 interrupt-parent = <&ipic>;
265 interrupts = <18 0x8>;
266 reg = <0x3>;
267 };
269 tbi0: tbi-phy@11 {
270 reg = <0x11>;
271 device_type = "tbi-phy";
272 };
273 };
274 };
276 enet1: ethernet@25000 {
277 #address-cells = <1>;
278 #size-cells = <1>;
279 cell-index = <1>;
280 device_type = "network";
281 model = "eTSEC";
282 compatible = "gianfar";
283 reg = <0x25000 0x1000>;
284 ranges = <0x0 0x25000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <35 0x8 36 0x8 37 0x8>;
287 phy-connection-type = "mii";
288 interrupt-parent = <&ipic>;
289 tbi-handle = <&tbi1>;
290 phy-handle = <&phy3>;
291 sleep = <&pmc 0x30000000>;
292 fsl,magic-packet;
294 mdio@520 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 compatible = "fsl,gianfar-tbi";
298 reg = <0x520 0x20>;
300 tbi1: tbi-phy@11 {
301 reg = <0x11>;
302 device_type = "tbi-phy";
303 };
304 };
305 };
307 serial0: serial@4500 {
308 cell-index = <0>;
309 device_type = "serial";
310 compatible = "fsl,ns16550", "ns16550";
311 reg = <0x4500 0x100>;
312 clock-frequency = <0>;
313 interrupts = <9 0x8>;
314 interrupt-parent = <&ipic>;
315 };
317 serial1: serial@4600 {
318 cell-index = <1>;
319 device_type = "serial";
320 compatible = "fsl,ns16550", "ns16550";
321 reg = <0x4600 0x100>;
322 clock-frequency = <0>;
323 interrupts = <10 0x8>;
324 interrupt-parent = <&ipic>;
325 };
327 crypto@30000 {
328 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
329 "fsl,sec2.1", "fsl,sec2.0";
330 reg = <0x30000 0x10000>;
331 interrupts = <11 0x8>;
332 interrupt-parent = <&ipic>;
333 fsl,num-channels = <4>;
334 fsl,channel-fifo-len = <24>;
335 fsl,exec-units-mask = <0x9fe>;
336 fsl,descriptor-types-mask = <0x3ab0ebf>;
337 sleep = <&pmc 0x03000000>;
338 };
340 sata@18000 {
341 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
342 reg = <0x18000 0x1000>;
343 interrupts = <44 0x8>;
344 interrupt-parent = <&ipic>;
345 sleep = <&pmc 0x000000c0>;
346 };
348 sata@19000 {
349 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
350 reg = <0x19000 0x1000>;
351 interrupts = <45 0x8>;
352 interrupt-parent = <&ipic>;
353 sleep = <&pmc 0x00000030>;
354 };
356 sata@1a000 {
357 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
358 reg = <0x1a000 0x1000>;
359 interrupts = <46 0x8>;
360 interrupt-parent = <&ipic>;
361 sleep = <&pmc 0x0000000c>;
362 };
364 sata@1b000 {
365 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
366 reg = <0x1b000 0x1000>;
367 interrupts = <47 0x8>;
368 interrupt-parent = <&ipic>;
369 sleep = <&pmc 0x00000003>;
370 };
372 /* IPIC
373 * interrupts cell = <intr #, sense>
374 * sense values match linux IORESOURCE_IRQ_* defines:
375 * sense == 8: Level, low assertion
376 * sense == 2: Edge, high-to-low change
377 */
378 ipic: pic@700 {
379 compatible = "fsl,ipic";
380 interrupt-controller;
381 #address-cells = <0>;
382 #interrupt-cells = <2>;
383 reg = <0x700 0x100>;
384 };
386 pmc: power@b00 {
387 compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
388 reg = <0xb00 0x100 0xa00 0x100>;
389 interrupts = <80 0x8>;
390 interrupt-parent = <&ipic>;
391 };
392 };
394 pci0: pci@e0008500 {
395 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
396 interrupt-map = <
398 /* IDSEL 0x11 */
399 0x8800 0x0 0x0 0x1 &ipic 20 0x8
400 0x8800 0x0 0x0 0x2 &ipic 21 0x8
401 0x8800 0x0 0x0 0x3 &ipic 22 0x8
402 0x8800 0x0 0x0 0x4 &ipic 23 0x8
404 /* IDSEL 0x12 */
405 0x9000 0x0 0x0 0x1 &ipic 22 0x8
406 0x9000 0x0 0x0 0x2 &ipic 23 0x8
407 0x9000 0x0 0x0 0x3 &ipic 20 0x8
408 0x9000 0x0 0x0 0x4 &ipic 21 0x8
410 /* IDSEL 0x13 */
411 0x9800 0x0 0x0 0x1 &ipic 23 0x8
412 0x9800 0x0 0x0 0x2 &ipic 20 0x8
413 0x9800 0x0 0x0 0x3 &ipic 21 0x8
414 0x9800 0x0 0x0 0x4 &ipic 22 0x8
416 /* IDSEL 0x15 */
417 0xa800 0x0 0x0 0x1 &ipic 20 0x8
418 0xa800 0x0 0x0 0x2 &ipic 21 0x8
419 0xa800 0x0 0x0 0x3 &ipic 22 0x8
420 0xa800 0x0 0x0 0x4 &ipic 23 0x8
422 /* IDSEL 0x16 */
423 0xb000 0x0 0x0 0x1 &ipic 23 0x8
424 0xb000 0x0 0x0 0x2 &ipic 20 0x8
425 0xb000 0x0 0x0 0x3 &ipic 21 0x8
426 0xb000 0x0 0x0 0x4 &ipic 22 0x8
428 /* IDSEL 0x17 */
429 0xb800 0x0 0x0 0x1 &ipic 22 0x8
430 0xb800 0x0 0x0 0x2 &ipic 23 0x8
431 0xb800 0x0 0x0 0x3 &ipic 20 0x8
432 0xb800 0x0 0x0 0x4 &ipic 21 0x8
434 /* IDSEL 0x18 */
435 0xc000 0x0 0x0 0x1 &ipic 21 0x8
436 0xc000 0x0 0x0 0x2 &ipic 22 0x8
437 0xc000 0x0 0x0 0x3 &ipic 23 0x8
438 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
439 interrupt-parent = <&ipic>;
440 interrupts = <66 0x8>;
441 bus-range = <0x0 0x0>;
442 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
443 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
444 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
445 sleep = <&pmc 0x00010000>;
446 clock-frequency = <0>;
447 #interrupt-cells = <1>;
448 #size-cells = <2>;
449 #address-cells = <3>;
450 reg = <0xe0008500 0x100 /* internal registers */
451 0xe0008300 0x8>; /* config space access registers */
452 compatible = "fsl,mpc8349-pci";
453 device_type = "pci";
454 };
455 };