| blob | 9c1eb9779108c1edee8122d47e76b8fe2d5dc634 |
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TQM 8540 Device Tree Source
4 *
5 * Copyright 2008 Freescale Semiconductor Inc.
6 */
8 /dts-v1/;
10 / {
11 model = "tqc,tqm8540";
12 compatible = "tqc,tqm8540";
13 #address-cells = <1>;
14 #size-cells = <1>;
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 ethernet2 = &enet2;
20 serial0 = &serial0;
21 serial1 = &serial1;
22 pci0 = &pci0;
23 };
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
29 PowerPC,8540@0 {
30 device_type = "cpu";
31 reg = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <32768>;
35 i-cache-size = <32768>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
39 next-level-cache = <&L2>;
40 };
41 };
43 memory {
44 device_type = "memory";
45 reg = <0x00000000 0x10000000>;
46 };
48 soc@e0000000 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 device_type = "soc";
52 ranges = <0x0 0xe0000000 0x100000>;
53 bus-frequency = <0>;
54 compatible = "fsl,mpc8540-immr", "simple-bus";
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>;
59 fsl,num-laws = <8>;
60 };
62 ecm@1000 {
63 compatible = "fsl,mpc8540-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>;
65 interrupts = <17 2>;
66 interrupt-parent = <&mpic>;
67 };
69 memory-controller@2000 {
70 compatible = "fsl,mpc8540-memory-controller";
71 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>;
73 interrupts = <18 2>;
74 };
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8540-l2-cache-controller";
78 reg = <0x20000 0x1000>;
79 cache-line-size = <32>;
80 cache-size = <0x40000>; // L2, 256K
81 interrupt-parent = <&mpic>;
82 interrupts = <16 2>;
83 };
85 i2c@3000 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 cell-index = <0>;
89 compatible = "fsl-i2c";
90 reg = <0x3000 0x100>;
91 interrupts = <43 2>;
92 interrupt-parent = <&mpic>;
93 dfsrr;
95 dtt@48 {
96 compatible = "national,lm75";
97 reg = <0x48>;
98 };
100 rtc@68 {
101 compatible = "dallas,ds1337";
102 reg = <0x68>;
103 };
104 };
106 dma@21300 {
107 #address-cells = <1>;
108 #size-cells = <1>;
109 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
110 reg = <0x21300 0x4>;
111 ranges = <0x0 0x21100 0x200>;
112 cell-index = <0>;
113 dma-channel@0 {
114 compatible = "fsl,mpc8540-dma-channel",
115 "fsl,eloplus-dma-channel";
116 reg = <0x0 0x80>;
117 cell-index = <0>;
118 interrupt-parent = <&mpic>;
119 interrupts = <20 2>;
120 };
121 dma-channel@80 {
122 compatible = "fsl,mpc8540-dma-channel",
123 "fsl,eloplus-dma-channel";
124 reg = <0x80 0x80>;
125 cell-index = <1>;
126 interrupt-parent = <&mpic>;
127 interrupts = <21 2>;
128 };
129 dma-channel@100 {
130 compatible = "fsl,mpc8540-dma-channel",
131 "fsl,eloplus-dma-channel";
132 reg = <0x100 0x80>;
133 cell-index = <2>;
134 interrupt-parent = <&mpic>;
135 interrupts = <22 2>;
136 };
137 dma-channel@180 {
138 compatible = "fsl,mpc8540-dma-channel",
139 "fsl,eloplus-dma-channel";
140 reg = <0x180 0x80>;
141 cell-index = <3>;
142 interrupt-parent = <&mpic>;
143 interrupts = <23 2>;
144 };
145 };
147 enet0: ethernet@24000 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 cell-index = <0>;
151 device_type = "network";
152 model = "TSEC";
153 compatible = "gianfar";
154 reg = <0x24000 0x1000>;
155 ranges = <0x0 0x24000 0x1000>;
156 local-mac-address = [ 00 00 00 00 00 00 ];
157 interrupts = <29 2 30 2 34 2>;
158 interrupt-parent = <&mpic>;
159 phy-handle = <&phy2>;
161 mdio@520 {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "fsl,gianfar-mdio";
165 reg = <0x520 0x20>;
167 phy1: ethernet-phy@1 {
168 interrupt-parent = <&mpic>;
169 interrupts = <8 1>;
170 reg = <1>;
171 };
172 phy2: ethernet-phy@2 {
173 interrupt-parent = <&mpic>;
174 interrupts = <8 1>;
175 reg = <2>;
176 };
177 phy3: ethernet-phy@3 {
178 interrupt-parent = <&mpic>;
179 interrupts = <8 1>;
180 reg = <3>;
181 };
182 tbi0: tbi-phy@11 {
183 reg = <0x11>;
184 device_type = "tbi-phy";
185 };
186 };
187 };
189 enet1: ethernet@25000 {
190 #address-cells = <1>;
191 #size-cells = <1>;
192 cell-index = <1>;
193 device_type = "network";
194 model = "TSEC";
195 compatible = "gianfar";
196 reg = <0x25000 0x1000>;
197 ranges = <0x0 0x25000 0x1000>;
198 local-mac-address = [ 00 00 00 00 00 00 ];
199 interrupts = <35 2 36 2 40 2>;
200 interrupt-parent = <&mpic>;
201 phy-handle = <&phy1>;
203 mdio@520 {
204 #address-cells = <1>;
205 #size-cells = <0>;
206 compatible = "fsl,gianfar-tbi";
207 reg = <0x520 0x20>;
209 tbi1: tbi-phy@11 {
210 reg = <0x11>;
211 device_type = "tbi-phy";
212 };
213 };
214 };
216 enet2: ethernet@26000 {
217 #address-cells = <1>;
218 #size-cells = <1>;
219 cell-index = <2>;
220 device_type = "network";
221 model = "FEC";
222 compatible = "gianfar";
223 reg = <0x26000 0x1000>;
224 ranges = <0x0 0x26000 0x1000>;
225 local-mac-address = [ 00 00 00 00 00 00 ];
226 interrupts = <41 2>;
227 interrupt-parent = <&mpic>;
228 phy-handle = <&phy3>;
230 mdio@520 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "fsl,gianfar-tbi";
234 reg = <0x520 0x20>;
236 tbi2: tbi-phy@11 {
237 reg = <0x11>;
238 device_type = "tbi-phy";
239 };
240 };
241 };
243 serial0: serial@4500 {
244 cell-index = <0>;
245 device_type = "serial";
246 compatible = "fsl,ns16550", "ns16550";
247 reg = <0x4500 0x100>; // reg base, size
248 clock-frequency = <0>; // should we fill in in uboot?
249 interrupts = <42 2>;
250 interrupt-parent = <&mpic>;
251 };
253 serial1: serial@4600 {
254 cell-index = <1>;
255 device_type = "serial";
256 compatible = "fsl,ns16550", "ns16550";
257 reg = <0x4600 0x100>; // reg base, size
258 clock-frequency = <0>; // should we fill in in uboot?
259 interrupts = <42 2>;
260 interrupt-parent = <&mpic>;
261 };
263 mpic: pic@40000 {
264 interrupt-controller;
265 #address-cells = <0>;
266 #interrupt-cells = <2>;
267 reg = <0x40000 0x40000>;
268 device_type = "open-pic";
269 compatible = "chrp,open-pic";
270 };
271 };
273 localbus@e0005000 {
274 #address-cells = <2>;
275 #size-cells = <1>;
276 compatible = "fsl,mpc8540-localbus", "fsl,pq3-localbus",
277 "simple-bus";
278 reg = <0xe0005000 0x1000>;
279 interrupt-parent = <&mpic>;
280 interrupts = <19 2>;
282 ranges = <0x0 0x0 0xfe000000 0x02000000>;
284 nor@0,0 {
285 #address-cells = <1>;
286 #size-cells = <1>;
287 compatible = "cfi-flash";
288 reg = <0x0 0x0 0x02000000>;
289 bank-width = <4>;
290 device-width = <2>;
291 partition@0 {
292 label = "kernel";
293 reg = <0x00000000 0x00180000>;
294 };
295 partition@180000 {
296 label = "root";
297 reg = <0x00180000 0x01dc0000>;
298 };
299 partition@1f40000 {
300 label = "env1";
301 reg = <0x01f40000 0x00040000>;
302 };
303 partition@1f80000 {
304 label = "env2";
305 reg = <0x01f80000 0x00040000>;
306 };
307 partition@1fc0000 {
308 label = "u-boot";
309 reg = <0x01fc0000 0x00040000>;
310 read-only;
311 };
312 };
313 };
315 pci0: pci@e0008000 {
316 #interrupt-cells = <1>;
317 #size-cells = <2>;
318 #address-cells = <3>;
319 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
320 device_type = "pci";
321 reg = <0xe0008000 0x1000>;
322 clock-frequency = <66666666>;
323 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
324 interrupt-map = <
325 /* IDSEL 28 */
326 0xe000 0 0 1 &mpic 2 1
327 0xe000 0 0 2 &mpic 3 1
328 0xe000 0 0 3 &mpic 6 1
329 0xe000 0 0 4 &mpic 5 1
331 /* IDSEL 11 */
332 0x5800 0 0 1 &mpic 6 1
333 0x5800 0 0 2 &mpic 5 1
334 >;
336 interrupt-parent = <&mpic>;
337 interrupts = <24 2>;
338 bus-range = <0 0>;
339 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
340 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
341 };
342 };