arch/powerpc/include/asm/book3s/32/mmu-hash.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
   3 #define _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
   4
   5 /*
   6  * 32-bit hash table MMU support
   7  */
   8
   9 /*
  10  * BATs
  11  */
  12
  13 /* Block size masks */
  14 #define BL_128K 0x000
  15 #define BL_256K 0x001
  16 #define BL_512K 0x003
  17 #define BL_1M   0x007
  18 #define BL_2M   0x00F
  19 #define BL_4M   0x01F
  20 #define BL_8M   0x03F
  21 #define BL_16M  0x07F
  22 #define BL_32M  0x0FF
  23 #define BL_64M  0x1FF
  24 #define BL_128M 0x3FF
  25 #define BL_256M 0x7FF
  26
  27 /* BAT Access Protection */
  28 #define BPP_XX  0x00            /* No access */
  29 #define BPP_RX  0x01            /* Read only */
  30 #define BPP_RW  0x02            /* Read/write */
  31
  32 #ifndef __ASSEMBLY__
  33 /* Contort a phys_addr_t into the right format/bits for a BAT */
  34 #ifdef CONFIG_PHYS_64BIT
  35 #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
  36                                 ((x & 0x0000000e00000000ULL) >> 24) | \
  37                                 ((x & 0x0000000100000000ULL) >> 30)))
  38 #define PHYS_BAT_ADDR(x) (((u64)(x) & 0x00000000fffe0000ULL) | \
  39                           (((u64)(x) << 24) & 0x0000000e00000000ULL) | \
  40                           (((u64)(x) << 30) & 0x0000000100000000ULL))
  41 #else
  42 #define BAT_PHYS_ADDR(x) (x)
  43 #define PHYS_BAT_ADDR(x) ((x) & 0xfffe0000)
  44 #endif
  45
  46 struct ppc_bat {
  47         u32 batu;
  48         u32 batl;
  49 };
  50 #endif /* !__ASSEMBLY__ */
  51
  52 /*
  53  * Hash table
  54  */
  55
  56 /* Values for PP (assumes Ks=0, Kp=1) */
  57 #define PP_RWXX 0       /* Supervisor read/write, User none */
  58 #define PP_RWRX 1       /* Supervisor read/write, User read */
  59 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
  60 #define PP_RXRX 3       /* Supervisor read,       User read */
  61
  62 /* Values for Segment Registers */
  63 #define SR_NX   0x10000000      /* No Execute */
  64 #define SR_KP   0x20000000      /* User key */
  65 #define SR_KS   0x40000000      /* Supervisor key */
  66
  67 #ifndef __ASSEMBLY__
  68
  69 /*
  70  * Hardware Page Table Entry
  71  * Note that the xpn and x bitfields are used only by processors that
  72  * support extended addressing; otherwise, those bits are reserved.
  73  */
  74 struct hash_pte {
  75         unsigned long v:1;      /* Entry is valid */
  76         unsigned long vsid:24;  /* Virtual segment identifier */
  77         unsigned long h:1;      /* Hash algorithm indicator */
  78         unsigned long api:6;    /* Abbreviated page index */
  79         unsigned long rpn:20;   /* Real (physical) page number */
  80         unsigned long xpn:3;    /* Real page number bits 0-2, optional */
  81         unsigned long r:1;      /* Referenced */
  82         unsigned long c:1;      /* Changed */
  83         unsigned long w:1;      /* Write-thru cache mode */
  84         unsigned long i:1;      /* Cache inhibited */
  85         unsigned long m:1;      /* Memory coherence */
  86         unsigned long g:1;      /* Guarded */
  87         unsigned long x:1;      /* Real page number bit 3, optional */
  88         unsigned long pp:2;     /* Page protection */
  89 };
  90
  91 typedef struct {
  92         unsigned long id;
  93         void __user *vdso;
  94 } mm_context_t;
  95
  96 void update_bats(void);
  97 static inline void cleanup_cpu_mmu_context(void) { };
  98
  99 /* patch sites */
 100 extern s32 patch__hash_page_A0, patch__hash_page_A1, patch__hash_page_A2;
 101 extern s32 patch__hash_page_B, patch__hash_page_C;
 102 extern s32 patch__flush_hash_A0, patch__flush_hash_A1, patch__flush_hash_A2;
 103 extern s32 patch__flush_hash_B;
 104
 105 #endif /* !__ASSEMBLY__ */
 106
 107 /* We happily ignore the smaller BATs on 601, we don't actually use
 108  * those definitions on hash32 at the moment anyway
 109  */
 110 #define mmu_virtual_psize       MMU_PAGE_4K
 111 #define mmu_linear_psize        MMU_PAGE_256M
 112
 113 #endif /* _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_ */