arch/powerpc/include/asm/page_32.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_PAGE_32_H
   3 #define _ASM_POWERPC_PAGE_32_H
   4
   5 #include <asm/cache.h>
   6
   7 #if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
   8 #if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
   9 #error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
  10 #endif
  11 #endif
  12
  13 #define VM_DATA_DEFAULT_FLAGS   VM_DATA_DEFAULT_FLAGS32
  14
  15 #ifdef CONFIG_NOT_COHERENT_CACHE
  16 #define ARCH_DMA_MINALIGN       L1_CACHE_BYTES
  17 #endif
  18
  19 #if defined(CONFIG_PPC_256K_PAGES) || \
  20     (defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES))
  21 #define PTE_SHIFT       (PAGE_SHIFT - PTE_T_LOG2 - 2)   /* 1/4 of a page */
  22 #else
  23 #define PTE_SHIFT       (PAGE_SHIFT - PTE_T_LOG2)       /* full page */
  24 #endif
  25
  26 #ifndef __ASSEMBLY__
  27 /*
  28  * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
  29  * physical addressing.
  30  */
  31 #ifdef CONFIG_PTE_64BIT
  32 typedef unsigned long long pte_basic_t;
  33 #else
  34 typedef unsigned long pte_basic_t;
  35 #endif
  36
  37 #include <asm/bug.h>
  38
  39 /*
  40  * Clear page using the dcbz instruction, which doesn't cause any
  41  * memory traffic (except to write out any cache lines which get
  42  * displaced).  This only works on cacheable memory.
  43  */
  44 static inline void clear_page(void *addr)
  45 {
  46         unsigned int i;
  47
  48         WARN_ON((unsigned long)addr & (L1_CACHE_BYTES - 1));
  49
  50         for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
  51                 dcbz(addr);
  52 }
  53 extern void copy_page(void *to, void *from);
  54
  55 #include <asm-generic/getorder.h>
  56
  57 #define PGD_T_LOG2      (__builtin_ffs(sizeof(pgd_t)) - 1)
  58 #define PTE_T_LOG2      (__builtin_ffs(sizeof(pte_t)) - 1)
  59
  60 #endif /* __ASSEMBLY__ */
  61
  62 #endif /* _ASM_POWERPC_PAGE_32_H */