arch/powerpc/include/asm/ppc_asm.h

   1 /*
   2  * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
   3  */
   4 #ifndef _ASM_POWERPC_PPC_ASM_H
   5 #define _ASM_POWERPC_PPC_ASM_H
   6
   7 #include <linux/stringify.h>
   8 #include <asm/asm-compat.h>
   9 #include <asm/processor.h>
  10 #include <asm/ppc-opcode.h>
  11 #include <asm/firmware.h>
  12 #include <asm/feature-fixups.h>
  13
  14 #ifdef __ASSEMBLY__
  15
  16 #define SZL                     (BITS_PER_LONG/8)
  17
  18 /*
  19  * Stuff for accurate CPU time accounting.
  20  * These macros handle transitions between user and system state
  21  * in exception entry and exit and accumulate time to the
  22  * user_time and system_time fields in the paca.
  23  */
  24
  25 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
  26 #define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb)
  27 #define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb)
  28 #define ACCOUNT_STOLEN_TIME
  29 #else
  30 #define ACCOUNT_CPU_USER_ENTRY(ptr, ra, rb)                             \
  31         MFTB(ra);                       /* get timebase */              \
  32         PPC_LL  rb, ACCOUNT_STARTTIME_USER(ptr);                        \
  33         PPC_STL ra, ACCOUNT_STARTTIME(ptr);                             \
  34         subf    rb,rb,ra;               /* subtract start value */      \
  35         PPC_LL  ra, ACCOUNT_USER_TIME(ptr);                             \
  36         add     ra,ra,rb;               /* add on to user time */       \
  37         PPC_STL ra, ACCOUNT_USER_TIME(ptr);                             \
  38
  39 #define ACCOUNT_CPU_USER_EXIT(ptr, ra, rb)                              \
  40         MFTB(ra);                       /* get timebase */              \
  41         PPC_LL  rb, ACCOUNT_STARTTIME(ptr);                             \
  42         PPC_STL ra, ACCOUNT_STARTTIME_USER(ptr);                        \
  43         subf    rb,rb,ra;               /* subtract start value */      \
  44         PPC_LL  ra, ACCOUNT_SYSTEM_TIME(ptr);                           \
  45         add     ra,ra,rb;               /* add on to system time */     \
  46         PPC_STL ra, ACCOUNT_SYSTEM_TIME(ptr)
  47
  48 #ifdef CONFIG_PPC_SPLPAR
  49 #define ACCOUNT_STOLEN_TIME                                             \
  50 BEGIN_FW_FTR_SECTION;                                                   \
  51         beq     33f;                                                    \
  52         /* from user - see if there are any DTL entries to process */   \
  53         ld      r10,PACALPPACAPTR(r13); /* get ptr to VPA */            \
  54         ld      r11,PACA_DTL_RIDX(r13); /* get log read index */        \
  55         addi    r10,r10,LPPACA_DTLIDX;                                  \
  56         LDX_BE  r10,0,r10;              /* get log write index */       \
  57         cmpd    cr1,r11,r10;                                            \
  58         beq+    cr1,33f;                                                \
  59         bl      accumulate_stolen_time;                         \
  60         ld      r12,_MSR(r1);                                           \
  61         andi.   r10,r12,MSR_PR;         /* Restore cr0 (coming from user) */ \
  62 33:                                                                     \
  63 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
  64
  65 #else  /* CONFIG_PPC_SPLPAR */
  66 #define ACCOUNT_STOLEN_TIME
  67
  68 #endif /* CONFIG_PPC_SPLPAR */
  69
  70 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
  71
  72 /*
  73  * Macros for storing registers into and loading registers from
  74  * exception frames.
  75  */
  76 #ifdef __powerpc64__
  77 #define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
  78 #define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
  79 #define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
  80 #define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
  81 #else
  82 #define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
  83 #define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
  84 #define SAVE_NVGPRS(base)       stmw    13, GPR0+4*13(base)
  85 #define REST_NVGPRS(base)       lmw     13, GPR0+4*13(base)
  86 #endif
  87
  88 #define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
  89 #define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
  90 #define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
  91 #define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
  92 #define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
  93 #define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
  94 #define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
  95 #define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
  96
  97 #define SAVE_FPR(n, base)       stfd    n,8*TS_FPRWIDTH*(n)(base)
  98 #define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
  99 #define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
 100 #define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
 101 #define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
 102 #define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
 103 #define REST_FPR(n, base)       lfd     n,8*TS_FPRWIDTH*(n)(base)
 104 #define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
 105 #define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
 106 #define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
 107 #define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
 108 #define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
 109
 110 #define SAVE_VR(n,b,base)       li b,16*(n);  stvx n,base,b
 111 #define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
 112 #define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
 113 #define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
 114 #define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
 115 #define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
 116 #define REST_VR(n,b,base)       li b,16*(n); lvx n,base,b
 117 #define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
 118 #define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
 119 #define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
 120 #define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
 121 #define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
 122
 123 #ifdef __BIG_ENDIAN__
 124 #define STXVD2X_ROT(n,b,base)           STXVD2X(n,b,base)
 125 #define LXVD2X_ROT(n,b,base)            LXVD2X(n,b,base)
 126 #else
 127 #define STXVD2X_ROT(n,b,base)           XXSWAPD(n,n);           \
 128                                         STXVD2X(n,b,base);      \
 129                                         XXSWAPD(n,n)
 130
 131 #define LXVD2X_ROT(n,b,base)            LXVD2X(n,b,base);       \
 132                                         XXSWAPD(n,n)
 133 #endif
 134 /* Save the lower 32 VSRs in the thread VSR region */
 135 #define SAVE_VSR(n,b,base)      li b,16*(n);  STXVD2X_ROT(n,R##base,R##b)
 136 #define SAVE_2VSRS(n,b,base)    SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
 137 #define SAVE_4VSRS(n,b,base)    SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
 138 #define SAVE_8VSRS(n,b,base)    SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
 139 #define SAVE_16VSRS(n,b,base)   SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
 140 #define SAVE_32VSRS(n,b,base)   SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
 141 #define REST_VSR(n,b,base)      li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
 142 #define REST_2VSRS(n,b,base)    REST_VSR(n,b,base); REST_VSR(n+1,b,base)
 143 #define REST_4VSRS(n,b,base)    REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
 144 #define REST_8VSRS(n,b,base)    REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
 145 #define REST_16VSRS(n,b,base)   REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
 146 #define REST_32VSRS(n,b,base)   REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
 147
 148 /*
 149  * b = base register for addressing, o = base offset from register of 1st EVR
 150  * n = first EVR, s = scratch
 151  */
 152 #define SAVE_EVR(n,s,b,o)       evmergehi s,s,n; stw s,o+4*(n)(b)
 153 #define SAVE_2EVRS(n,s,b,o)     SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
 154 #define SAVE_4EVRS(n,s,b,o)     SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
 155 #define SAVE_8EVRS(n,s,b,o)     SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
 156 #define SAVE_16EVRS(n,s,b,o)    SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
 157 #define SAVE_32EVRS(n,s,b,o)    SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
 158 #define REST_EVR(n,s,b,o)       lwz s,o+4*(n)(b); evmergelo n,s,n
 159 #define REST_2EVRS(n,s,b,o)     REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
 160 #define REST_4EVRS(n,s,b,o)     REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
 161 #define REST_8EVRS(n,s,b,o)     REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
 162 #define REST_16EVRS(n,s,b,o)    REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
 163 #define REST_32EVRS(n,s,b,o)    REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
 164
 165 /* Macros to adjust thread priority for hardware multithreading */
 166 #define HMT_VERY_LOW    or      31,31,31        # very low priority
 167 #define HMT_LOW         or      1,1,1
 168 #define HMT_MEDIUM_LOW  or      6,6,6           # medium low priority
 169 #define HMT_MEDIUM      or      2,2,2
 170 #define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
 171 #define HMT_HIGH        or      3,3,3
 172 #define HMT_EXTRA_HIGH  or      7,7,7           # power7 only
 173
 174 #ifdef CONFIG_PPC64
 175 #define ULONG_SIZE      8
 176 #else
 177 #define ULONG_SIZE      4
 178 #endif
 179 #define __VCPU_GPR(n)   (VCPU_GPRS + (n * ULONG_SIZE))
 180 #define VCPU_GPR(n)     __VCPU_GPR(__REG_##n)
 181
 182 #ifdef __KERNEL__
 183
 184 /*
 185  * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit
 186  * version below in the else case of the ifdef.
 187  */
 188 #ifdef __powerpc64__
 189
 190 #define STACKFRAMESIZE 256
 191 #define __STK_REG(i)   (112 + ((i)-14)*8)
 192 #define STK_REG(i)     __STK_REG(__REG_##i)
 193
 194 #ifdef PPC64_ELF_ABI_v2
 195 #define STK_GOT         24
 196 #define __STK_PARAM(i)  (32 + ((i)-3)*8)
 197 #else
 198 #define STK_GOT         40
 199 #define __STK_PARAM(i)  (48 + ((i)-3)*8)
 200 #endif
 201 #define STK_PARAM(i)    __STK_PARAM(__REG_##i)
 202
 203 #ifdef PPC64_ELF_ABI_v2
 204
 205 #define _GLOBAL(name) \
 206         .align 2 ; \
 207         .type name,@function; \
 208         .globl name; \
 209 name:
 210
 211 #define _GLOBAL_TOC(name) \
 212         .align 2 ; \
 213         .type name,@function; \
 214         .globl name; \
 215 name: \
 216 0:      addis r2,r12,(.TOC.-0b)@ha; \
 217         addi r2,r2,(.TOC.-0b)@l; \
 218         .localentry name,.-name
 219
 220 #define DOTSYM(a)       a
 221
 222 #else
 223
 224 #define XGLUE(a,b) a##b
 225 #define GLUE(a,b) XGLUE(a,b)
 226
 227 #define _GLOBAL(name) \
 228         .align 2 ; \
 229         .globl name; \
 230         .globl GLUE(.,name); \
 231         .pushsection ".opd","aw"; \
 232 name: \
 233         .quad GLUE(.,name); \
 234         .quad .TOC.@tocbase; \
 235         .quad 0; \
 236         .popsection; \
 237         .type GLUE(.,name),@function; \
 238 GLUE(.,name):
 239
 240 #define _GLOBAL_TOC(name) _GLOBAL(name)
 241
 242 #define DOTSYM(a)       GLUE(.,a)
 243
 244 #endif
 245
 246 #else /* 32-bit */
 247
 248 #define _ENTRY(n)       \
 249         .globl n;       \
 250 n:
 251
 252 #define _GLOBAL(n)      \
 253         .stabs __stringify(n:F-1),N_FUN,0,0,n;\
 254         .globl n;       \
 255 n:
 256
 257 #define _GLOBAL_TOC(name) _GLOBAL(name)
 258
 259 #define DOTSYM(a)       a
 260
 261 #endif
 262
 263 /*
 264  * __kprobes (the C annotation) puts the symbol into the .kprobes.text
 265  * section, which gets emitted at the end of regular text.
 266  *
 267  * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
 268  * a blacklist. The former is for core kprobe functions/data, the
 269  * latter is for those that incdentially must be excluded from probing
 270  * and allows them to be linked at more optimal location within text.
 271  */
 272 #ifdef CONFIG_KPROBES
 273 #define _ASM_NOKPROBE_SYMBOL(entry)                     \
 274         .pushsection "_kprobe_blacklist","aw";          \
 275         PPC_LONG (entry) ;                              \
 276         .popsection
 277 #else
 278 #define _ASM_NOKPROBE_SYMBOL(entry)
 279 #endif
 280
 281 #define FUNC_START(name)        _GLOBAL(name)
 282 #define FUNC_END(name)
 283
 284 /*
 285  * LOAD_REG_IMMEDIATE(rn, expr)
 286  *   Loads the value of the constant expression 'expr' into register 'rn'
 287  *   using immediate instructions only.  Use this when it's important not
 288  *   to reference other data (i.e. on ppc64 when the TOC pointer is not
 289  *   valid) and when 'expr' is a constant or absolute address.
 290  *
 291  * LOAD_REG_ADDR(rn, name)
 292  *   Loads the address of label 'name' into register 'rn'.  Use this when
 293  *   you don't particularly need immediate instructions only, but you need
 294  *   the whole address in one register (e.g. it's a structure address and
 295  *   you want to access various offsets within it).  On ppc32 this is
 296  *   identical to LOAD_REG_IMMEDIATE.
 297  *
 298  * LOAD_REG_ADDR_PIC(rn, name)
 299  *   Loads the address of label 'name' into register 'run'. Use this when
 300  *   the kernel doesn't run at the linked or relocated address. Please
 301  *   note that this macro will clobber the lr register.
 302  *
 303  * LOAD_REG_ADDRBASE(rn, name)
 304  * ADDROFF(name)
 305  *   LOAD_REG_ADDRBASE loads part of the address of label 'name' into
 306  *   register 'rn'.  ADDROFF(name) returns the remainder of the address as
 307  *   a constant expression.  ADDROFF(name) is a signed expression < 16 bits
 308  *   in size, so is suitable for use directly as an offset in load and store
 309  *   instructions.  Use this when loading/storing a single word or less as:
 310  *      LOAD_REG_ADDRBASE(rX, name)
 311  *      ld      rY,ADDROFF(name)(rX)
 312  */
 313
 314 /* Be careful, this will clobber the lr register. */
 315 #define LOAD_REG_ADDR_PIC(reg, name)            \
 316         bl      0f;                             \
 317 0:      mflr    reg;                            \
 318         addis   reg,reg,(name - 0b)@ha;         \
 319         addi    reg,reg,(name - 0b)@l;
 320
 321 #if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH)
 322 #define __AS_ATHIGH high
 323 #else
 324 #define __AS_ATHIGH h
 325 #endif
 326
 327 .macro __LOAD_REG_IMMEDIATE_32 r, x
 328         .if (\x) >= 0x8000 || (\x) < -0x8000
 329                 lis \r, (\x)@__AS_ATHIGH
 330                 .if (\x) & 0xffff != 0
 331                         ori \r, \r, (\x)@l
 332                 .endif
 333         .else
 334                 li \r, (\x)@l
 335         .endif
 336 .endm
 337
 338 .macro __LOAD_REG_IMMEDIATE r, x
 339         .if (\x) >= 0x80000000 || (\x) < -0x80000000
 340                 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32
 341                 sldi    \r, \r, 32
 342                 .if (\x) & 0xffff0000 != 0
 343                         oris \r, \r, (\x)@__AS_ATHIGH
 344                 .endif
 345                 .if (\x) & 0xffff != 0
 346                         ori \r, \r, (\x)@l
 347                 .endif
 348         .else
 349                 __LOAD_REG_IMMEDIATE_32 \r, \x
 350         .endif
 351 .endm
 352
 353 #ifdef __powerpc64__
 354
 355 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr
 356
 357 #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr)  \
 358         lis     tmp, (expr)@highest;            \
 359         lis     reg, (expr)@__AS_ATHIGH;        \
 360         ori     tmp, tmp, (expr)@higher;        \
 361         ori     reg, reg, (expr)@l;             \
 362         rldimi  reg, tmp, 32, 0
 363
 364 #define LOAD_REG_ADDR(reg,name)                 \
 365         ld      reg,name@got(r2)
 366
 367 #define LOAD_REG_ADDRBASE(reg,name)     LOAD_REG_ADDR(reg,name)
 368 #define ADDROFF(name)                   0
 369
 370 /* offsets for stack frame layout */
 371 #define LRSAVE  16
 372
 373 #else /* 32-bit */
 374
 375 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr
 376
 377 #define LOAD_REG_IMMEDIATE_SYM(reg,expr)                \
 378         lis     reg,(expr)@ha;          \
 379         addi    reg,reg,(expr)@l;
 380
 381 #define LOAD_REG_ADDR(reg,name)         LOAD_REG_IMMEDIATE_SYM(reg, name)
 382
 383 #define LOAD_REG_ADDRBASE(reg, name)    lis     reg,name@ha
 384 #define ADDROFF(name)                   name@l
 385
 386 /* offsets for stack frame layout */
 387 #define LRSAVE  4
 388
 389 #endif
 390
 391 /* various errata or part fixups */
 392 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
 393 #define MFTB(dest)                      \
 394 90:     mfspr dest, SPRN_TBRL;          \
 395 BEGIN_FTR_SECTION_NESTED(96);           \
 396         cmpwi dest,0;                   \
 397         beq-  90b;                      \
 398 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
 399 #else
 400 #define MFTB(dest)                      MFTBL(dest)
 401 #endif
 402
 403 #ifdef CONFIG_PPC_8xx
 404 #define MFTBL(dest)                     mftb dest
 405 #define MFTBU(dest)                     mftbu dest
 406 #else
 407 #define MFTBL(dest)                     mfspr dest, SPRN_TBRL
 408 #define MFTBU(dest)                     mfspr dest, SPRN_TBRU
 409 #endif
 410
 411 #ifndef CONFIG_SMP
 412 #define TLBSYNC
 413 #else
 414 #define TLBSYNC         tlbsync; sync
 415 #endif
 416
 417 #ifdef CONFIG_PPC64
 418 #define MTOCRF(FXM, RS)                 \
 419         BEGIN_FTR_SECTION_NESTED(848);  \
 420         mtcrf   (FXM), RS;              \
 421         FTR_SECTION_ELSE_NESTED(848);   \
 422         mtocrf (FXM), RS;               \
 423         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
 424 #endif
 425
 426 /*
 427  * This instruction is not implemented on the PPC 603 or 601; however, on
 428  * the 403GCX and 405GP tlbia IS defined and tlbie is not.
 429  * All of these instructions exist in the 8xx, they have magical powers,
 430  * and they must be used.
 431  */
 432
 433 #if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx)
 434 #define tlbia                                   \
 435         li      r4,1024;                        \
 436         mtctr   r4;                             \
 437         lis     r4,KERNELBASE@h;                \
 438         .machine push;                          \
 439         .machine "power4";                      \
 440 0:      tlbie   r4;                             \
 441         .machine pop;                           \
 442         addi    r4,r4,0x1000;                   \
 443         bdnz    0b
 444 #endif
 445
 446
 447 #ifdef CONFIG_IBM440EP_ERR42
 448 #define PPC440EP_ERR42 isync
 449 #else
 450 #define PPC440EP_ERR42
 451 #endif
 452
 453 /* The following stops all load and store data streams associated with stream
 454  * ID (ie. streams created explicitly).  The embedded and server mnemonics for
 455  * dcbt are different so this must only be used for server.
 456  */
 457 #define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch)        \
 458        lis     scratch,0x60000000@h;                    \
 459        dcbt    0,scratch,0b01010
 460
 461 /*
 462  * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
 463  * keep the address intact to be compatible with code shared with
 464  * 32-bit classic.
 465  *
 466  * On the other hand, I find it useful to have them behave as expected
 467  * by their name (ie always do the addition) on 64-bit BookE
 468  */
 469 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
 470 #define toreal(rd)
 471 #define fromreal(rd)
 472
 473 /*
 474  * We use addis to ensure compatibility with the "classic" ppc versions of
 475  * these macros, which use rs = 0 to get the tophys offset in rd, rather than
 476  * converting the address in r0, and so this version has to do that too
 477  * (i.e. set register rd to 0 when rs == 0).
 478  */
 479 #define tophys(rd,rs)                           \
 480         addis   rd,rs,0
 481
 482 #define tovirt(rd,rs)                           \
 483         addis   rd,rs,0
 484
 485 #elif defined(CONFIG_PPC64)
 486 #define toreal(rd)              /* we can access c000... in real mode */
 487 #define fromreal(rd)
 488
 489 #define tophys(rd,rs)                           \
 490         clrldi  rd,rs,2
 491
 492 #define tovirt(rd,rs)                           \
 493         rotldi  rd,rs,16;                       \
 494         ori     rd,rd,((KERNELBASE>>48)&0xFFFF);\
 495         rotldi  rd,rd,48
 496 #else
 497 #define toreal(rd)      tophys(rd,rd)
 498 #define fromreal(rd)    tovirt(rd,rd)
 499
 500 #define tophys(rd, rs)  addis   rd, rs, -PAGE_OFFSET@h
 501 #define tovirt(rd, rs)  addis   rd, rs, PAGE_OFFSET@h
 502 #endif
 503
 504 #ifdef CONFIG_PPC_BOOK3S_64
 505 #define MTMSRD(r)       mtmsrd  r
 506 #define MTMSR_EERI(reg) mtmsrd  reg,1
 507 #else
 508 #define MTMSRD(r)       mtmsr   r
 509 #define MTMSR_EERI(reg) mtmsr   reg
 510 #endif
 511
 512 #endif /* __KERNEL__ */
 513
 514 /* The boring bits... */
 515
 516 /* Condition Register Bit Fields */
 517
 518 #define cr0     0
 519 #define cr1     1
 520 #define cr2     2
 521 #define cr3     3
 522 #define cr4     4
 523 #define cr5     5
 524 #define cr6     6
 525 #define cr7     7
 526
 527
 528 /*
 529  * General Purpose Registers (GPRs)
 530  *
 531  * The lower case r0-r31 should be used in preference to the upper
 532  * case R0-R31 as they provide more error checking in the assembler.
 533  * Use R0-31 only when really nessesary.
 534  */
 535
 536 #define r0      %r0
 537 #define r1      %r1
 538 #define r2      %r2
 539 #define r3      %r3
 540 #define r4      %r4
 541 #define r5      %r5
 542 #define r6      %r6
 543 #define r7      %r7
 544 #define r8      %r8
 545 #define r9      %r9
 546 #define r10     %r10
 547 #define r11     %r11
 548 #define r12     %r12
 549 #define r13     %r13
 550 #define r14     %r14
 551 #define r15     %r15
 552 #define r16     %r16
 553 #define r17     %r17
 554 #define r18     %r18
 555 #define r19     %r19
 556 #define r20     %r20
 557 #define r21     %r21
 558 #define r22     %r22
 559 #define r23     %r23
 560 #define r24     %r24
 561 #define r25     %r25
 562 #define r26     %r26
 563 #define r27     %r27
 564 #define r28     %r28
 565 #define r29     %r29
 566 #define r30     %r30
 567 #define r31     %r31
 568
 569
 570 /* Floating Point Registers (FPRs) */
 571
 572 #define fr0     0
 573 #define fr1     1
 574 #define fr2     2
 575 #define fr3     3
 576 #define fr4     4
 577 #define fr5     5
 578 #define fr6     6
 579 #define fr7     7
 580 #define fr8     8
 581 #define fr9     9
 582 #define fr10    10
 583 #define fr11    11
 584 #define fr12    12
 585 #define fr13    13
 586 #define fr14    14
 587 #define fr15    15
 588 #define fr16    16
 589 #define fr17    17
 590 #define fr18    18
 591 #define fr19    19
 592 #define fr20    20
 593 #define fr21    21
 594 #define fr22    22
 595 #define fr23    23
 596 #define fr24    24
 597 #define fr25    25
 598 #define fr26    26
 599 #define fr27    27
 600 #define fr28    28
 601 #define fr29    29
 602 #define fr30    30
 603 #define fr31    31
 604
 605 /* AltiVec Registers (VPRs) */
 606
 607 #define v0      0
 608 #define v1      1
 609 #define v2      2
 610 #define v3      3
 611 #define v4      4
 612 #define v5      5
 613 #define v6      6
 614 #define v7      7
 615 #define v8      8
 616 #define v9      9
 617 #define v10     10
 618 #define v11     11
 619 #define v12     12
 620 #define v13     13
 621 #define v14     14
 622 #define v15     15
 623 #define v16     16
 624 #define v17     17
 625 #define v18     18
 626 #define v19     19
 627 #define v20     20
 628 #define v21     21
 629 #define v22     22
 630 #define v23     23
 631 #define v24     24
 632 #define v25     25
 633 #define v26     26
 634 #define v27     27
 635 #define v28     28
 636 #define v29     29
 637 #define v30     30
 638 #define v31     31
 639
 640 /* VSX Registers (VSRs) */
 641
 642 #define vs0     0
 643 #define vs1     1
 644 #define vs2     2
 645 #define vs3     3
 646 #define vs4     4
 647 #define vs5     5
 648 #define vs6     6
 649 #define vs7     7
 650 #define vs8     8
 651 #define vs9     9
 652 #define vs10    10
 653 #define vs11    11
 654 #define vs12    12
 655 #define vs13    13
 656 #define vs14    14
 657 #define vs15    15
 658 #define vs16    16
 659 #define vs17    17
 660 #define vs18    18
 661 #define vs19    19
 662 #define vs20    20
 663 #define vs21    21
 664 #define vs22    22
 665 #define vs23    23
 666 #define vs24    24
 667 #define vs25    25
 668 #define vs26    26
 669 #define vs27    27
 670 #define vs28    28
 671 #define vs29    29
 672 #define vs30    30
 673 #define vs31    31
 674 #define vs32    32
 675 #define vs33    33
 676 #define vs34    34
 677 #define vs35    35
 678 #define vs36    36
 679 #define vs37    37
 680 #define vs38    38
 681 #define vs39    39
 682 #define vs40    40
 683 #define vs41    41
 684 #define vs42    42
 685 #define vs43    43
 686 #define vs44    44
 687 #define vs45    45
 688 #define vs46    46
 689 #define vs47    47
 690 #define vs48    48
 691 #define vs49    49
 692 #define vs50    50
 693 #define vs51    51
 694 #define vs52    52
 695 #define vs53    53
 696 #define vs54    54
 697 #define vs55    55
 698 #define vs56    56
 699 #define vs57    57
 700 #define vs58    58
 701 #define vs59    59
 702 #define vs60    60
 703 #define vs61    61
 704 #define vs62    62
 705 #define vs63    63
 706
 707 /* SPE Registers (EVPRs) */
 708
 709 #define evr0    0
 710 #define evr1    1
 711 #define evr2    2
 712 #define evr3    3
 713 #define evr4    4
 714 #define evr5    5
 715 #define evr6    6
 716 #define evr7    7
 717 #define evr8    8
 718 #define evr9    9
 719 #define evr10   10
 720 #define evr11   11
 721 #define evr12   12
 722 #define evr13   13
 723 #define evr14   14
 724 #define evr15   15
 725 #define evr16   16
 726 #define evr17   17
 727 #define evr18   18
 728 #define evr19   19
 729 #define evr20   20
 730 #define evr21   21
 731 #define evr22   22
 732 #define evr23   23
 733 #define evr24   24
 734 #define evr25   25
 735 #define evr26   26
 736 #define evr27   27
 737 #define evr28   28
 738 #define evr29   29
 739 #define evr30   30
 740 #define evr31   31
 741
 742 /* some stab codes */
 743 #define N_FUN   36
 744 #define N_RSYM  64
 745 #define N_SLINE 68
 746 #define N_SO    100
 747
 748 #define RFSCV   .long 0x4c0000a4
 749
 750 /*
 751  * Create an endian fixup trampoline
 752  *
 753  * This starts with a "tdi 0,0,0x48" instruction which is
 754  * essentially a "trap never", and thus akin to a nop.
 755  *
 756  * The opcode for this instruction read with the wrong endian
 757  * however results in a b . + 8
 758  *
 759  * So essentially we use that trick to execute the following
 760  * trampoline in "reverse endian" if we are running with the
 761  * MSR_LE bit set the "wrong" way for whatever endianness the
 762  * kernel is built for.
 763  */
 764
 765 #ifdef CONFIG_PPC_BOOK3E
 766 #define FIXUP_ENDIAN
 767 #else
 768 /*
 769  * This version may be used in HV or non-HV context.
 770  * MSR[EE] must be disabled.
 771  */
 772 #define FIXUP_ENDIAN                                               \
 773         tdi   0,0,0x48;   /* Reverse endian of b . + 8          */ \
 774         b     191f;       /* Skip trampoline if endian is good  */ \
 775         .long 0xa600607d; /* mfmsr r11                          */ \
 776         .long 0x01006b69; /* xori r11,r11,1                     */ \
 777         .long 0x00004039; /* li r10,0                           */ \
 778         .long 0x6401417d; /* mtmsrd r10,1                       */ \
 779         .long 0x05009f42; /* bcl 20,31,$+4                      */ \
 780         .long 0xa602487d; /* mflr r10                           */ \
 781         .long 0x14004a39; /* addi r10,r10,20                    */ \
 782         .long 0xa6035a7d; /* mtsrr0 r10                         */ \
 783         .long 0xa6037b7d; /* mtsrr1 r11                         */ \
 784         .long 0x2400004c; /* rfid                               */ \
 785 191:
 786
 787 /*
 788  * This version that may only be used with MSR[HV]=1
 789  * - Does not clear MSR[RI], so more robust.
 790  * - Slightly smaller and faster.
 791  */
 792 #define FIXUP_ENDIAN_HV                                            \
 793         tdi   0,0,0x48;   /* Reverse endian of b . + 8          */ \
 794         b     191f;       /* Skip trampoline if endian is good  */ \
 795         .long 0xa600607d; /* mfmsr r11                          */ \
 796         .long 0x01006b69; /* xori r11,r11,1                     */ \
 797         .long 0x05009f42; /* bcl 20,31,$+4                      */ \
 798         .long 0xa602487d; /* mflr r10                           */ \
 799         .long 0x14004a39; /* addi r10,r10,20                    */ \
 800         .long 0xa64b5a7d; /* mthsrr0 r10                        */ \
 801         .long 0xa64b7b7d; /* mthsrr1 r11                        */ \
 802         .long 0x2402004c; /* hrfid                              */ \
 803 191:
 804
 805 #endif /* !CONFIG_PPC_BOOK3E */
 806
 807 #endif /*  __ASSEMBLY__ */
 808
 809 /*
 810  * Helper macro for exception table entries
 811  */
 812 #define EX_TABLE(_fault, _target)               \
 813         stringify_in_c(.section __ex_table,"a";)\
 814         stringify_in_c(.balign 4;)              \
 815         stringify_in_c(.long (_fault) - . ;)    \
 816         stringify_in_c(.long (_target) - . ;)   \
 817         stringify_in_c(.previous)
 818
 819 #ifdef CONFIG_PPC_FSL_BOOK3E
 820 #define BTB_FLUSH(reg)                  \
 821         lis reg,BUCSR_INIT@h;           \
 822         ori reg,reg,BUCSR_INIT@l;       \
 823         mtspr SPRN_BUCSR,reg;           \
 824         isync;
 825 #else
 826 #define BTB_FLUSH(reg)
 827 #endif /* CONFIG_PPC_FSL_BOOK3E */
 828
 829 #endif /* _ASM_POWERPC_PPC_ASM_H */