arch/powerpc/include/uapi/asm/sigcontext.h

   1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
   2 #ifndef _ASM_POWERPC_SIGCONTEXT_H
   3 #define _ASM_POWERPC_SIGCONTEXT_H
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/compiler.h>
  12 #include <asm/ptrace.h>
  13 #ifdef __powerpc64__
  14 #include <asm/elf.h>
  15 #endif
  16
  17 struct sigcontext {
  18         unsigned long   _unused[4];
  19         int             signal;
  20 #ifdef __powerpc64__
  21         int             _pad0;
  22 #endif
  23         unsigned long   handler;
  24         unsigned long   oldmask;
  25 #ifdef __KERNEL__
  26         struct user_pt_regs __user *regs;
  27 #else
  28         struct pt_regs  *regs;
  29 #endif
  30 #ifdef __powerpc64__
  31         elf_gregset_t   gp_regs;
  32         elf_fpregset_t  fp_regs;
  33 /*
  34  * To maintain compatibility with current implementations the sigcontext is
  35  * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
  36  * followed by an unstructured (vmx_reserve) field of 101 doublewords. This
  37  * allows the array of vector registers to be quadword aligned independent of
  38  * the alignment of the containing sigcontext or ucontext. It is the
  39  * responsibility of the code setting the sigcontext to set this pointer to
  40  * either NULL (if this processor does not support the VMX feature) or the
  41  * address of the first quadword within the allocated (vmx_reserve) area.
  42  *
  43  * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
  44  * an array of 34 quadword entries (elf_vrregset_t).  The entries with
  45  * indexes 0-31 contain the corresponding vector registers.  The entry with
  46  * index 32 contains the vscr as the last word (offset 12) within the
  47  * quadword.  This allows the vscr to be stored as either a quadword (since
  48  * it must be copied via a vector register to/from storage) or as a word.
  49  * The entry with index 33 contains the vrsave as the first word (offset 0)
  50  * within the quadword.
  51  *
  52  * Part of the VSX data is stored here also by extending vmx_restore
  53  * by an additional 32 double words.  Architecturally the layout of
  54  * the VSR registers and how they overlap on top of the legacy FPR and
  55  * VR registers is shown below:
  56  *
  57  *                    VSR doubleword 0               VSR doubleword 1
  58  *           ----------------------------------------------------------------
  59  *   VSR[0]  |             FPR[0]            |                              |
  60  *           ----------------------------------------------------------------
  61  *   VSR[1]  |             FPR[1]            |                              |
  62  *           ----------------------------------------------------------------
  63  *           |              ...              |                              |
  64  *           |              ...              |                              |
  65  *           ----------------------------------------------------------------
  66  *   VSR[30] |             FPR[30]           |                              |
  67  *           ----------------------------------------------------------------
  68  *   VSR[31] |             FPR[31]           |                              |
  69  *           ----------------------------------------------------------------
  70  *   VSR[32] |                             VR[0]                            |
  71  *           ----------------------------------------------------------------
  72  *   VSR[33] |                             VR[1]                            |
  73  *           ----------------------------------------------------------------
  74  *           |                              ...                             |
  75  *           |                              ...                             |
  76  *           ----------------------------------------------------------------
  77  *   VSR[62] |                             VR[30]                           |
  78  *           ----------------------------------------------------------------
  79  *   VSR[63] |                             VR[31]                           |
  80  *           ----------------------------------------------------------------
  81  *
  82  * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63
  83  * is stored at the start of vmx_reserve.  vmx_reserve is extended for
  84  * backwards compatility to store VSR 0-31 doubleword 1 after the VMX
  85  * registers and vscr/vrsave.
  86  */
  87         elf_vrreg_t     __user *v_regs;
  88         long            vmx_reserve[ELF_NVRREG + ELF_NVRREG + 1 + 32];
  89 #endif
  90 };
  91
  92 #endif /* _ASM_POWERPC_SIGCONTEXT_H */