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WIP FPC-III support
[linux/fpc-iii.git] / arch / powerpc / kernel / head_booke.h
blob74e230c200fbf40bab4443f781c673cfe35b01fa
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __HEAD_BOOKE_H__
3 #define __HEAD_BOOKE_H__
4
5 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
6 #include <asm/kvm_asm.h>
7 #include <asm/kvm_booke_hv_asm.h>
8
9 #ifdef __ASSEMBLY__
10
11 /*
12 * Macros used for common Book-e exception handling
13 */
14
15 #define SET_IVOR(vector_number, vector_label) \
16 li r26,vector_label@l; \
17 mtspr SPRN_IVOR##vector_number,r26; \
18 sync
19
20 #if (THREAD_SHIFT < 15)
21 #define ALLOC_STACK_FRAME(reg, val) \
22 addi reg,reg,val
23 #else
24 #define ALLOC_STACK_FRAME(reg, val) \
25 addis reg,reg,val@ha; \
26 addi reg,reg,val@l
27 #endif
28
29 /*
30 * Macro used to get to thread save registers.
31 * Note that entries 0-3 are used for the prolog code, and the remaining
32 * entries are available for specific exception use in the event a handler
33 * requires more than 4 scratch registers.
34 */
35 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
36
37 #ifdef CONFIG_PPC_FSL_BOOK3E
38 #define BOOKE_CLEAR_BTB(reg) \
39 START_BTB_FLUSH_SECTION \
40 BTB_FLUSH(reg) \
41 END_BTB_FLUSH_SECTION
42 #else
43 #define BOOKE_CLEAR_BTB(reg)
44 #endif
45
46
47 #define NORMAL_EXCEPTION_PROLOG(intno) \
48 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
49 mfspr r10, SPRN_SPRG_THREAD; \
50 stw r11, THREAD_NORMSAVE(0)(r10); \
51 stw r13, THREAD_NORMSAVE(2)(r10); \
52 mfcr r13; /* save CR in r13 for now */\
53 mfspr r11, SPRN_SRR1; \
54 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \
55 andi. r11, r11, MSR_PR; /* check whether user or kernel */\
56 mr r11, r1; \
57 beq 1f; \
58 BOOKE_CLEAR_BTB(r11) \
59 /* if from user, start at top of this thread's kernel stack */ \
60 lwz r11, TASK_STACK - THREAD(r10); \
61 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
62 1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
63 stw r13, _CCR(r11); /* save various registers */ \
64 stw r12,GPR12(r11); \
65 stw r9,GPR9(r11); \
66 mfspr r13, SPRN_SPRG_RSCRATCH0; \
67 stw r13, GPR10(r11); \
68 lwz r12, THREAD_NORMSAVE(0)(r10); \
69 stw r12,GPR11(r11); \
70 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
71 mflr r10; \
72 stw r10,_LINK(r11); \
73 mfspr r12,SPRN_SRR0; \
74 stw r1, GPR1(r11); \
75 mfspr r9,SPRN_SRR1; \
76 stw r1, 0(r11); \
77 mr r1, r11; \
78 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
79 stw r0,GPR0(r11); \
80 lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
81 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
82 stw r10, 8(r11); \
83 SAVE_4GPRS(3, r11); \
84 SAVE_2GPRS(7, r11)
85
86 .macro SYSCALL_ENTRY trapno intno srr1
87 mfspr r10, SPRN_SPRG_THREAD
88 #ifdef CONFIG_KVM_BOOKE_HV
89 BEGIN_FTR_SECTION
90 mtspr SPRN_SPRG_WSCRATCH0, r10
91 stw r11, THREAD_NORMSAVE(0)(r10)
92 stw r13, THREAD_NORMSAVE(2)(r10)
93 mfcr r13 /* save CR in r13 for now */
94 mfspr r11, SPRN_SRR1
95 mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */
96 bf 3, 1975f
97 b kvmppc_handler_\intno\()_\srr1
98 1975:
99 mr r12, r13
100 lwz r13, THREAD_NORMSAVE(2)(r10)
101 FTR_SECTION_ELSE
102 #endif
103 mfcr r12
104 #ifdef CONFIG_KVM_BOOKE_HV
105 ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
106 #endif
107 mfspr r9, SPRN_SRR1
108 BOOKE_CLEAR_BTB(r11)
109 andi. r11, r9, MSR_PR
110 lwz r11, TASK_STACK - THREAD(r10)
111 rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */
112 beq- 99f
113 ALLOC_STACK_FRAME(r11, THREAD_SIZE - INT_FRAME_SIZE)
114 stw r12, _CCR(r11) /* save various registers */
115 mflr r12
116 stw r12,_LINK(r11)
117 mfspr r12,SPRN_SRR0
118 stw r1, GPR1(r11)
119 stw r1, 0(r11)
120 mr r1, r11
121 stw r12,_NIP(r11)
122 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
123 lis r12, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
124 stw r2,GPR2(r11)
125 addi r12, r12, STACK_FRAME_REGS_MARKER@l
126 stw r9,_MSR(r11)
127 li r2, \trapno + 1
128 stw r12, 8(r11)
129 stw r2,_TRAP(r11)
130 SAVE_GPR(0, r11)
131 SAVE_4GPRS(3, r11)
132 SAVE_2GPRS(7, r11)
133
134 addi r11,r1,STACK_FRAME_OVERHEAD
135 addi r2,r10,-THREAD
136 stw r11,PT_REGS(r10)
137 /* Check to see if the dbcr0 register is set up to debug. Use the
138 internal debug mode bit to do this. */
139 lwz r12,THREAD_DBCR0(r10)
140 andis. r12,r12,DBCR0_IDM@h
141 ACCOUNT_CPU_USER_ENTRY(r2, r11, r12)
142 beq+ 3f
143 /* From user and task is ptraced - load up global dbcr0 */
144 li r12,-1 /* clear all pending debug events */
145 mtspr SPRN_DBSR,r12
146 lis r11,global_dbcr0@ha
147 tophys(r11,r11)
148 addi r11,r11,global_dbcr0@l
149 #ifdef CONFIG_SMP
150 lwz r10, TASK_CPU(r2)
151 slwi r10, r10, 3
152 add r11, r11, r10
153 #endif
154 lwz r12,0(r11)
155 mtspr SPRN_DBCR0,r12
156 lwz r12,4(r11)
157 addi r12,r12,-1
158 stw r12,4(r11)
159
160 3:
161 tovirt(r2, r2) /* set r2 to current */
162 lis r11, transfer_to_syscall@h
163 ori r11, r11, transfer_to_syscall@l
164 #ifdef CONFIG_TRACE_IRQFLAGS
165 /*
166 * If MSR is changing we need to keep interrupts disabled at this point
167 * otherwise we might risk taking an interrupt before we tell lockdep
168 * they are enabled.
169 */
170 lis r10, MSR_KERNEL@h
171 ori r10, r10, MSR_KERNEL@l
172 rlwimi r10, r9, 0, MSR_EE
173 #else
174 lis r10, (MSR_KERNEL | MSR_EE)@h
175 ori r10, r10, (MSR_KERNEL | MSR_EE)@l
176 #endif
177 mtspr SPRN_SRR1,r10
178 mtspr SPRN_SRR0,r11
179 rfi /* jump to handler, enable MMU */
180 99: b ret_from_kernel_syscall
181 .endm
182
183 /* To handle the additional exception priority levels on 40x and Book-E
184 * processors we allocate a stack per additional priority level.
185 *
186 * On 40x critical is the only additional level
187 * On 44x/e500 we have critical and machine check
188 *
189 * Additionally we reserve a SPRG for each priority level so we can free up a
190 * GPR to use as the base for indirect access to the exception stacks. This
191 * is necessary since the MMU is always on, for Book-E parts, and the stacks
192 * are offset from KERNELBASE.
193 *
194 * There is some space optimization to be had here if desired. However
195 * to allow for a common kernel with support for debug exceptions either
196 * going to critical or their own debug level we aren't currently
197 * providing configurations that micro-optimize space usage.
198 */
199
200 #define MC_STACK_BASE mcheckirq_ctx
201 #define CRIT_STACK_BASE critirq_ctx
202
203 /* only on e500mc */
204 #define DBG_STACK_BASE dbgirq_ctx
205
206 #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
207
208 #ifdef CONFIG_SMP
209 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
210 mfspr r8,SPRN_PIR; \
211 slwi r8,r8,2; \
212 addis r8,r8,level##_STACK_BASE@ha; \
213 lwz r8,level##_STACK_BASE@l(r8); \
214 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
215 #else
216 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
217 lis r8,level##_STACK_BASE@ha; \
218 lwz r8,level##_STACK_BASE@l(r8); \
219 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
220 #endif
221
222 /*
223 * Exception prolog for critical/machine check exceptions. This is a
224 * little different from the normal exception prolog above since a
225 * critical/machine check exception can potentially occur at any point
226 * during normal exception processing. Thus we cannot use the same SPRG
227 * registers as the normal prolog above. Instead we use a portion of the
228 * critical/machine check exception stack at low physical addresses.
229 */
230 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \
231 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \
232 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
233 stw r9,GPR9(r8); /* save various registers */\
234 mfcr r9; /* save CR in r9 for now */\
235 stw r10,GPR10(r8); \
236 stw r11,GPR11(r8); \
237 stw r9,_CCR(r8); /* save CR on stack */\
238 mfspr r11,exc_level_srr1; /* check whether user or kernel */\
239 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \
240 BOOKE_CLEAR_BTB(r10) \
241 andi. r11,r11,MSR_PR; \
242 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
243 lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\
244 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\
245 beq 1f; \
246 /* COMING FROM USER MODE */ \
247 stw r9,_CCR(r11); /* save CR */\
248 lwz r10,GPR10(r8); /* copy regs from exception stack */\
249 lwz r9,GPR9(r8); \
250 stw r10,GPR10(r11); \
251 lwz r10,GPR11(r8); \
252 stw r9,GPR9(r11); \
253 stw r10,GPR11(r11); \
254 b 2f; \
255 /* COMING FROM PRIV MODE */ \
256 1: mr r11, r8; \
257 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \
258 stw r12,GPR12(r11); /* save various registers */\
259 mflr r10; \
260 stw r10,_LINK(r11); \
261 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
262 stw r12,_DEAR(r11); /* since they may have had stuff */\
263 mfspr r9,SPRN_ESR; /* in them at the point where the */\
264 stw r9,_ESR(r11); /* exception was taken */\
265 mfspr r12,exc_level_srr0; \
266 stw r1,GPR1(r11); \
267 mfspr r9,exc_level_srr1; \
268 stw r1,0(r11); \
269 mr r1,r11; \
270 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
271 stw r0,GPR0(r11); \
272 SAVE_4GPRS(3, r11); \
273 SAVE_2GPRS(7, r11)
274
275 #define CRITICAL_EXCEPTION_PROLOG(intno) \
276 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1)
277 #define DEBUG_EXCEPTION_PROLOG \
278 EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
279 #define MCHECK_EXCEPTION_PROLOG \
280 EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \
281 SPRN_MCSRR0, SPRN_MCSRR1)
282
283 /*
284 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
285 * being delivered to the host. This exception can only happen
286 * inside a KVM guest -- so we just handle up to the DO_KVM rather
287 * than try to fit this into one of the existing prolog macros.
288 */
289 #define GUEST_DOORBELL_EXCEPTION \
290 START_EXCEPTION(GuestDoorbell); \
291 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
292 mfspr r10, SPRN_SPRG_THREAD; \
293 stw r11, THREAD_NORMSAVE(0)(r10); \
294 mfspr r11, SPRN_SRR1; \
295 stw r13, THREAD_NORMSAVE(2)(r10); \
296 mfcr r13; /* save CR in r13 for now */\
297 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \
298 trap
299
300 /*
301 * Exception vectors.
302 */
303 #define START_EXCEPTION(label) \
304 .align 5; \
305 label:
306
307 #define EXCEPTION(n, intno, label, hdlr, xfer) \
308 START_EXCEPTION(label); \
309 NORMAL_EXCEPTION_PROLOG(intno); \
310 addi r3,r1,STACK_FRAME_OVERHEAD; \
311 xfer(n, hdlr)
312
313 #define CRITICAL_EXCEPTION(n, intno, label, hdlr) \
314 START_EXCEPTION(label); \
315 CRITICAL_EXCEPTION_PROLOG(intno); \
316 addi r3,r1,STACK_FRAME_OVERHEAD; \
317 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
318 crit_transfer_to_handler, ret_from_crit_exc)
319
320 #define MCHECK_EXCEPTION(n, label, hdlr) \
321 START_EXCEPTION(label); \
322 MCHECK_EXCEPTION_PROLOG; \
323 mfspr r5,SPRN_ESR; \
324 stw r5,_ESR(r11); \
325 addi r3,r1,STACK_FRAME_OVERHEAD; \
326 EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
327 mcheck_transfer_to_handler, ret_from_mcheck_exc)
328
329 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret) \
330 li r10,trap; \
331 stw r10,_TRAP(r11); \
332 lis r10,msr@h; \
333 ori r10,r10,msr@l; \
334 bl tfer; \
335 .long hdlr; \
336 .long ret
337
338 #define EXC_XFER_STD(n, hdlr) \
339 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, transfer_to_handler_full, \
340 ret_from_except_full)
341
342 #define EXC_XFER_LITE(n, hdlr) \
343 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, transfer_to_handler, \
344 ret_from_except)
345
346 /* Check for a single step debug exception while in an exception
347 * handler before state has been saved. This is to catch the case
348 * where an instruction that we are trying to single step causes
349 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
350 * the exception handler generates a single step debug exception.
351 *
352 * If we get a debug trap on the first instruction of an exception handler,
353 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
354 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
355 * The exception handler was handling a non-critical interrupt, so it will
356 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
357 * the MSR_DE bit set.
358 */
359 #define DEBUG_DEBUG_EXCEPTION \
360 START_EXCEPTION(DebugDebug); \
361 DEBUG_EXCEPTION_PROLOG; \
362 \
363 /* \
364 * If there is a single step or branch-taken exception in an \
365 * exception entry sequence, it was probably meant to apply to \
366 * the code where the exception occurred (since exception entry \
367 * doesn't turn off DE automatically). We simulate the effect \
368 * of turning off DE on entry to an exception handler by turning \
369 * off DE in the DSRR1 value and clearing the debug status. \
370 */ \
371 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
372 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
373 beq+ 2f; \
374 \
375 lis r10,interrupt_base@h; /* check if exception in vectors */ \
376 ori r10,r10,interrupt_base@l; \
377 cmplw r12,r10; \
378 blt+ 2f; /* addr below exception vectors */ \
379 \
380 lis r10,interrupt_end@h; \
381 ori r10,r10,interrupt_end@l; \
382 cmplw r12,r10; \
383 bgt+ 2f; /* addr above exception vectors */ \
384 \
385 /* here it looks like we got an inappropriate debug exception. */ \
386 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
387 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
388 mtspr SPRN_DBSR,r10; \
389 /* restore state and get out */ \
390 lwz r10,_CCR(r11); \
391 lwz r0,GPR0(r11); \
392 lwz r1,GPR1(r11); \
393 mtcrf 0x80,r10; \
394 mtspr SPRN_DSRR0,r12; \
395 mtspr SPRN_DSRR1,r9; \
396 lwz r9,GPR9(r11); \
397 lwz r12,GPR12(r11); \
398 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \
399 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
400 lwz r10,GPR10(r8); \
401 lwz r11,GPR11(r8); \
402 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \
403 \
404 PPC_RFDI; \
405 b .; \
406 \
407 /* continue normal handling for a debug exception... */ \
408 2: mfspr r4,SPRN_DBSR; \
409 addi r3,r1,STACK_FRAME_OVERHEAD; \
410 EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), debug_transfer_to_handler, ret_from_debug_exc)
411
412 #define DEBUG_CRIT_EXCEPTION \
413 START_EXCEPTION(DebugCrit); \
414 CRITICAL_EXCEPTION_PROLOG(DEBUG); \
415 \
416 /* \
417 * If there is a single step or branch-taken exception in an \
418 * exception entry sequence, it was probably meant to apply to \
419 * the code where the exception occurred (since exception entry \
420 * doesn't turn off DE automatically). We simulate the effect \
421 * of turning off DE on entry to an exception handler by turning \
422 * off DE in the CSRR1 value and clearing the debug status. \
423 */ \
424 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
425 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
426 beq+ 2f; \
427 \
428 lis r10,interrupt_base@h; /* check if exception in vectors */ \
429 ori r10,r10,interrupt_base@l; \
430 cmplw r12,r10; \
431 blt+ 2f; /* addr below exception vectors */ \
432 \
433 lis r10,interrupt_end@h; \
434 ori r10,r10,interrupt_end@l; \
435 cmplw r12,r10; \
436 bgt+ 2f; /* addr above exception vectors */ \
437 \
438 /* here it looks like we got an inappropriate debug exception. */ \
439 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
440 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
441 mtspr SPRN_DBSR,r10; \
442 /* restore state and get out */ \
443 lwz r10,_CCR(r11); \
444 lwz r0,GPR0(r11); \
445 lwz r1,GPR1(r11); \
446 mtcrf 0x80,r10; \
447 mtspr SPRN_CSRR0,r12; \
448 mtspr SPRN_CSRR1,r9; \
449 lwz r9,GPR9(r11); \
450 lwz r12,GPR12(r11); \
451 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \
452 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
453 lwz r10,GPR10(r8); \
454 lwz r11,GPR11(r8); \
455 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \
456 \
457 rfci; \
458 b .; \
459 \
460 /* continue normal handling for a critical exception... */ \
461 2: mfspr r4,SPRN_DBSR; \
462 addi r3,r1,STACK_FRAME_OVERHEAD; \
463 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), crit_transfer_to_handler, ret_from_crit_exc)
464
465 #define DATA_STORAGE_EXCEPTION \
466 START_EXCEPTION(DataStorage) \
467 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE); \
468 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
469 stw r5,_ESR(r11); \
470 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
471 stw r4, _DEAR(r11); \
472 EXC_XFER_LITE(0x0300, handle_page_fault)
473
474 #define INSTRUCTION_STORAGE_EXCEPTION \
475 START_EXCEPTION(InstructionStorage) \
476 NORMAL_EXCEPTION_PROLOG(INST_STORAGE); \
477 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
478 stw r5,_ESR(r11); \
479 mr r4,r12; /* Pass SRR0 as arg2 */ \
480 stw r4, _DEAR(r11); \
481 li r5,0; /* Pass zero as arg3 */ \
482 EXC_XFER_LITE(0x0400, handle_page_fault)
483
484 #define ALIGNMENT_EXCEPTION \
485 START_EXCEPTION(Alignment) \
486 NORMAL_EXCEPTION_PROLOG(ALIGNMENT); \
487 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
488 stw r4,_DEAR(r11); \
489 addi r3,r1,STACK_FRAME_OVERHEAD; \
490 EXC_XFER_STD(0x0600, alignment_exception)
491
492 #define PROGRAM_EXCEPTION \
493 START_EXCEPTION(Program) \
494 NORMAL_EXCEPTION_PROLOG(PROGRAM); \
495 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
496 stw r4,_ESR(r11); \
497 addi r3,r1,STACK_FRAME_OVERHEAD; \
498 EXC_XFER_STD(0x0700, program_check_exception)
499
500 #define DECREMENTER_EXCEPTION \
501 START_EXCEPTION(Decrementer) \
502 NORMAL_EXCEPTION_PROLOG(DECREMENTER); \
503 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
504 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
505 addi r3,r1,STACK_FRAME_OVERHEAD; \
506 EXC_XFER_LITE(0x0900, timer_interrupt)
507
508 #define FP_UNAVAILABLE_EXCEPTION \
509 START_EXCEPTION(FloatingPointUnavailable) \
510 NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL); \
511 beq 1f; \
512 bl load_up_fpu; /* if from user, just load it up */ \
513 b fast_exception_return; \
514 1: addi r3,r1,STACK_FRAME_OVERHEAD; \
515 EXC_XFER_STD(0x800, kernel_fp_unavailable_exception)
516
517 #else /* __ASSEMBLY__ */
518 struct exception_regs {
519 unsigned long mas0;
520 unsigned long mas1;
521 unsigned long mas2;
522 unsigned long mas3;
523 unsigned long mas6;
524 unsigned long mas7;
525 unsigned long srr0;
526 unsigned long srr1;
527 unsigned long csrr0;
528 unsigned long csrr1;
529 unsigned long dsrr0;
530 unsigned long dsrr1;
531 unsigned long saved_ksp_limit;
532 };
533
534 /* ensure this structure is always sized to a multiple of the stack alignment */
535 #define STACK_EXC_LVL_FRAME_SIZE ALIGN(sizeof (struct exception_regs), 16)
536
537 #endif /* __ASSEMBLY__ */
538 #endif /* __HEAD_BOOKE_H__ */
Linux with added FPC-III support