1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2008-2011 DENX Software Engineering GmbH
4 * Author: Heiko Schocher <hs@denx.de>
7 * Keymile 83xx platform specific routines.
10 #include <linux/stddef.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/errno.h>
14 #include <linux/reboot.h>
15 #include <linux/pci.h>
16 #include <linux/kdev_t.h>
17 #include <linux/major.h>
18 #include <linux/console.h>
19 #include <linux/delay.h>
20 #include <linux/seq_file.h>
21 #include <linux/root_dev.h>
22 #include <linux/initrd.h>
23 #include <linux/of_platform.h>
24 #include <linux/of_device.h>
26 #include <linux/atomic.h>
27 #include <linux/time.h>
29 #include <asm/machdep.h>
34 #include <sysdev/fsl_soc.h>
35 #include <sysdev/fsl_pci.h>
36 #include <soc/fsl/qe/qe.h>
40 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
42 static void quirk_mpc8360e_qe_enet10(void)
45 * handle mpc8360E Erratum QE_ENET10:
46 * RGMII AC values do not meet the specification
48 uint svid
= mfspr(SPRN_SVR
);
49 struct device_node
*np_par
;
54 np_par
= of_find_node_by_name(NULL
, "par_io");
56 pr_warn("%s couldn't find par_io node\n", __func__
);
59 /* Map Parallel I/O ports registers */
60 ret
= of_address_to_resource(np_par
, 0, &res
);
62 pr_warn("%s couldn't map par_io registers\n", __func__
);
66 base
= ioremap(res
.start
, resource_size(&res
));
71 * set output delay adjustments to default values according
72 * table 5 in Errata Rev. 5, 9/2011:
74 * write 0b01 to UCC1 bits 18:19
75 * write 0b01 to UCC2 option 1 bits 4:5
76 * write 0b01 to UCC2 option 2 bits 16:17
78 clrsetbits_be32((base
+ 0xa8), 0x0c00f000, 0x04005000);
81 * set output delay adjustments to default values according
82 * table 3-13 in Reference Manual Rev.3 05/2010:
84 * write 0b01 to UCC2 option 2 bits 16:17
85 * write 0b0101 to UCC1 bits 20:23
86 * write 0b0101 to UCC2 option 1 bits 24:27
88 clrsetbits_be32((base
+ 0xac), 0x0000cff0, 0x00004550);
90 if (SVR_REV(svid
) == 0x0021) {
92 * UCC2 option 1: write 0b1010 to bits 24:27
93 * at address IMMRBAR+0x14AC
95 clrsetbits_be32((base
+ 0xac), 0x000000f0, 0x000000a0);
96 } else if (SVR_REV(svid
) == 0x0020) {
98 * UCC1: write 0b11 to bits 18:19
99 * at address IMMRBAR+0x14A8
101 setbits32((base
+ 0xa8), 0x00003000);
104 * UCC2 option 1: write 0b11 to bits 4:5
105 * at address IMMRBAR+0x14A8
107 setbits32((base
+ 0xa8), 0x0c000000);
110 * UCC2 option 2: write 0b11 to bits 16:17
111 * at address IMMRBAR+0x14AC
113 setbits32((base
+ 0xac), 0x0000c000);
120 /* ************************************************************************
122 * Setup the architecture
125 static void __init
mpc83xx_km_setup_arch(void)
127 #ifdef CONFIG_QUICC_ENGINE
128 struct device_node
*np
;
131 mpc83xx_setup_arch();
133 #ifdef CONFIG_QUICC_ENGINE
134 np
= of_find_node_by_name(NULL
, "par_io");
139 for_each_node_by_name(np
, "spi")
140 par_io_of_config(np
);
142 for_each_node_by_name(np
, "ucc")
143 par_io_of_config(np
);
145 /* Only apply this quirk when par_io is available */
146 np
= of_find_compatible_node(NULL
, "network", "ucc_geth");
148 quirk_mpc8360e_qe_enet10();
152 #endif /* CONFIG_QUICC_ENGINE */
155 machine_device_initcall(mpc83xx_km
, mpc83xx_declare_of_platform_devices
);
157 /* list of the supported boards */
158 static char *board
[] __initdata
= {
160 "Keymile,kmpbec8321",
165 * Called very early, MMU is off, device-tree isn't unflattened
167 static int __init
mpc83xx_km_probe(void)
172 if (of_machine_is_compatible(board
[i
]))
176 return (board
[i
] != NULL
);
179 define_machine(mpc83xx_km
) {
180 .name
= "mpc83xx-km-platform",
181 .probe
= mpc83xx_km_probe
,
182 .setup_arch
= mpc83xx_km_setup_arch
,
183 .init_IRQ
= mpc83xx_ipic_init_IRQ
,
184 .get_irq
= ipic_get_irq
,
185 .restart
= mpc83xx_restart
,
186 .time_init
= mpc83xx_time_init
,
187 .calibrate_decr
= generic_calibrate_decr
,
188 .progress
= udbg_progress
,