arch/powerpc/platforms/chrp/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * CHRP pci routines.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/pci.h>
   8 #include <linux/delay.h>
   9 #include <linux/string.h>
  10 #include <linux/init.h>
  11 #include <linux/pgtable.h>
  12
  13 #include <asm/io.h>
  14 #include <asm/irq.h>
  15 #include <asm/hydra.h>
  16 #include <asm/prom.h>
  17 #include <asm/machdep.h>
  18 #include <asm/sections.h>
  19 #include <asm/pci-bridge.h>
  20 #include <asm/grackle.h>
  21 #include <asm/rtas.h>
  22
  23 #include "chrp.h"
  24 #include "gg2.h"
  25
  26 /* LongTrail */
  27 void __iomem *gg2_pci_config_base;
  28
  29 /*
  30  * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
  31  * limit the bus number to 3 bits
  32  */
  33
  34 static int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
  35                            int len, u32 *val)
  36 {
  37         volatile void __iomem *cfg_data;
  38         struct pci_controller *hose = pci_bus_to_host(bus);
  39
  40         if (bus->number > 7)
  41                 return PCIBIOS_DEVICE_NOT_FOUND;
  42         /*
  43          * Note: the caller has already checked that off is
  44          * suitably aligned and that len is 1, 2 or 4.
  45          */
  46         cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
  47         switch (len) {
  48         case 1:
  49                 *val =  in_8(cfg_data);
  50                 break;
  51         case 2:
  52                 *val = in_le16(cfg_data);
  53                 break;
  54         default:
  55                 *val = in_le32(cfg_data);
  56                 break;
  57         }
  58         return PCIBIOS_SUCCESSFUL;
  59 }
  60
  61 static int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
  62                             int len, u32 val)
  63 {
  64         volatile void __iomem *cfg_data;
  65         struct pci_controller *hose = pci_bus_to_host(bus);
  66
  67         if (bus->number > 7)
  68                 return PCIBIOS_DEVICE_NOT_FOUND;
  69         /*
  70          * Note: the caller has already checked that off is
  71          * suitably aligned and that len is 1, 2 or 4.
  72          */
  73         cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
  74         switch (len) {
  75         case 1:
  76                 out_8(cfg_data, val);
  77                 break;
  78         case 2:
  79                 out_le16(cfg_data, val);
  80                 break;
  81         default:
  82                 out_le32(cfg_data, val);
  83                 break;
  84         }
  85         return PCIBIOS_SUCCESSFUL;
  86 }
  87
  88 static struct pci_ops gg2_pci_ops =
  89 {
  90         .read = gg2_read_config,
  91         .write = gg2_write_config,
  92 };
  93
  94 /*
  95  * Access functions for PCI config space using RTAS calls.
  96  */
  97 static int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
  98                             int len, u32 *val)
  99 {
 100         struct pci_controller *hose = pci_bus_to_host(bus);
 101         unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
 102                 | (((bus->number - hose->first_busno) & 0xff) << 16)
 103                 | (hose->global_number << 24);
 104         int ret = -1;
 105         int rval;
 106
 107         rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
 108         *val = ret;
 109         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
 110 }
 111
 112 static int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
 113                              int len, u32 val)
 114 {
 115         struct pci_controller *hose = pci_bus_to_host(bus);
 116         unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
 117                 | (((bus->number - hose->first_busno) & 0xff) << 16)
 118                 | (hose->global_number << 24);
 119         int rval;
 120
 121         rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
 122                          addr, len, val);
 123         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
 124 }
 125
 126 static struct pci_ops rtas_pci_ops =
 127 {
 128         .read = rtas_read_config,
 129         .write = rtas_write_config,
 130 };
 131
 132 volatile struct Hydra __iomem *Hydra = NULL;
 133
 134 int __init
 135 hydra_init(void)
 136 {
 137         struct device_node *np;
 138         struct resource r;
 139
 140         np = of_find_node_by_name(NULL, "mac-io");
 141         if (np == NULL || of_address_to_resource(np, 0, &r)) {
 142                 of_node_put(np);
 143                 return 0;
 144         }
 145         of_node_put(np);
 146         Hydra = ioremap(r.start, resource_size(&r));
 147         printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start);
 148         printk("Hydra Feature_Control was %x",
 149                in_le32(&Hydra->Feature_Control));
 150         out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
 151                                            HYDRA_FC_SCSI_CELL_EN |
 152                                            HYDRA_FC_SCCA_ENABLE |
 153                                            HYDRA_FC_SCCB_ENABLE |
 154                                            HYDRA_FC_ARB_BYPASS |
 155                                            HYDRA_FC_MPIC_ENABLE |
 156                                            HYDRA_FC_SLOW_SCC_PCLK |
 157                                            HYDRA_FC_MPIC_IS_MASTER));
 158         printk(", now %x\n", in_le32(&Hydra->Feature_Control));
 159         return 1;
 160 }
 161
 162 #define PRG_CL_RESET_VALID 0x00010000
 163
 164 static void __init
 165 setup_python(struct pci_controller *hose, struct device_node *dev)
 166 {
 167         u32 __iomem *reg;
 168         u32 val;
 169         struct resource r;
 170
 171         if (of_address_to_resource(dev, 0, &r)) {
 172                 printk(KERN_ERR "No address for Python PCI controller\n");
 173                 return;
 174         }
 175
 176         /* Clear the magic go-slow bit */
 177         reg = ioremap(r.start + 0xf6000, 0x40);
 178         BUG_ON(!reg);
 179         val = in_be32(&reg[12]);
 180         if (val & PRG_CL_RESET_VALID) {
 181                 out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
 182                 in_be32(&reg[12]);
 183         }
 184         iounmap(reg);
 185
 186         setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0);
 187 }
 188
 189 /* Marvell Discovery II based Pegasos 2 */
 190 static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
 191 {
 192         struct device_node *root = of_find_node_by_path("/");
 193         struct device_node *rtas;
 194
 195         rtas = of_find_node_by_name (root, "rtas");
 196         if (rtas) {
 197                 hose->ops = &rtas_pci_ops;
 198                 of_node_put(rtas);
 199         } else {
 200                 printk ("RTAS supporting Pegasos OF not found, please upgrade"
 201                         " your firmware\n");
 202         }
 203         pci_add_flags(PCI_REASSIGN_ALL_BUS);
 204         /* keep the reference to the root node */
 205 }
 206
 207 void __init
 208 chrp_find_bridges(void)
 209 {
 210         struct device_node *dev;
 211         const int *bus_range;
 212         int len, index = -1;
 213         struct pci_controller *hose;
 214         const unsigned int *dma;
 215         const char *model, *machine;
 216         int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
 217         struct device_node *root = of_find_node_by_path("/");
 218         struct resource r;
 219         /*
 220          * The PCI host bridge nodes on some machines don't have
 221          * properties to adequately identify them, so we have to
 222          * look at what sort of machine this is as well.
 223          */
 224         machine = of_get_property(root, "model", NULL);
 225         if (machine != NULL) {
 226                 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
 227                 is_mot = strncmp(machine, "MOT", 3) == 0;
 228                 if (strncmp(machine, "Pegasos2", 8) == 0)
 229                         is_pegasos = 2;
 230                 else if (strncmp(machine, "Pegasos", 7) == 0)
 231                         is_pegasos = 1;
 232         }
 233         for_each_child_of_node(root, dev) {
 234                 if (!of_node_is_type(dev, "pci"))
 235                         continue;
 236                 ++index;
 237                 /* The GG2 bridge on the LongTrail doesn't have an address */
 238                 if (of_address_to_resource(dev, 0, &r) && !is_longtrail) {
 239                         printk(KERN_WARNING "Can't use %pOF: no address\n",
 240                                dev);
 241                         continue;
 242                 }
 243                 bus_range = of_get_property(dev, "bus-range", &len);
 244                 if (bus_range == NULL || len < 2 * sizeof(int)) {
 245                         printk(KERN_WARNING "Can't get bus-range for %pOF\n",
 246                                 dev);
 247                         continue;
 248                 }
 249                 if (bus_range[1] == bus_range[0])
 250                         printk(KERN_INFO "PCI bus %d", bus_range[0]);
 251                 else
 252                         printk(KERN_INFO "PCI buses %d..%d",
 253                                bus_range[0], bus_range[1]);
 254                 printk(" controlled by %pOF", dev);
 255                 if (!is_longtrail)
 256                         printk(" at %llx", (unsigned long long)r.start);
 257                 printk("\n");
 258
 259                 hose = pcibios_alloc_controller(dev);
 260                 if (!hose) {
 261                         printk("Can't allocate PCI controller structure for %pOF\n",
 262                                 dev);
 263                         continue;
 264                 }
 265                 hose->first_busno = hose->self_busno = bus_range[0];
 266                 hose->last_busno = bus_range[1];
 267
 268                 model = of_get_property(dev, "model", NULL);
 269                 if (model == NULL)
 270                         model = "<none>";
 271                 if (strncmp(model, "IBM, Python", 11) == 0) {
 272                         setup_python(hose, dev);
 273                 } else if (is_mot
 274                            || strncmp(model, "Motorola, Grackle", 17) == 0) {
 275                         setup_grackle(hose);
 276                 } else if (is_longtrail) {
 277                         void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
 278                         hose->ops = &gg2_pci_ops;
 279                         hose->cfg_data = p;
 280                         gg2_pci_config_base = p;
 281                 } else if (is_pegasos == 1) {
 282                         setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0);
 283                 } else if (is_pegasos == 2) {
 284                         setup_peg2(hose, dev);
 285                 } else if (!strncmp(model, "IBM,CPC710", 10)) {
 286                         setup_indirect_pci(hose,
 287                                            r.start + 0x000f8000,
 288                                            r.start + 0x000f8010,
 289                                            0);
 290                         if (index == 0) {
 291                                 dma = of_get_property(dev, "system-dma-base",
 292                                                         &len);
 293                                 if (dma && len >= sizeof(*dma)) {
 294                                         dma = (unsigned int *)
 295                                                 (((unsigned long)dma) +
 296                                                 len - sizeof(*dma));
 297                                                 pci_dram_offset = *dma;
 298                                 }
 299                         }
 300                 } else {
 301                         printk("No methods for %pOF (model %s), using RTAS\n",
 302                                dev, model);
 303                         hose->ops = &rtas_pci_ops;
 304                 }
 305
 306                 pci_process_bridge_OF_ranges(hose, dev, index == 0);
 307
 308                 /* check the first bridge for a property that we can
 309                    use to set pci_dram_offset */
 310                 dma = of_get_property(dev, "ibm,dma-ranges", &len);
 311                 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
 312                         pci_dram_offset = dma[2] - dma[3];
 313                         printk("pci_dram_offset = %lx\n", pci_dram_offset);
 314                 }
 315         }
 316         of_node_put(root);
 317 }
 318
 319 /* SL82C105 IDE Control/Status Register */
 320 #define SL82C105_IDECSR                0x40
 321
 322 /* Fixup for Winbond ATA quirk, required for briq mostly because the
 323  * 8259 is configured for level sensitive IRQ 14 and so wants the
 324  * ATA controller to be set to fully native mode or bad things
 325  * will happen.
 326  */
 327 static void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105)
 328 {
 329         u8 progif;
 330
 331         /* If non-briq machines need that fixup too, please speak up */
 332         if (!machine_is(chrp) || _chrp_type != _CHRP_briq)
 333                 return;
 334
 335         if ((sl82c105->class & 5) != 5) {
 336                 printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
 337                 /* Enable SL82C105 PCI native IDE mode */
 338                 pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif);
 339                 pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05);
 340                 sl82c105->class |= 0x05;
 341                 /* Disable SL82C105 second port */
 342                 pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003);
 343                 /* Clear IO BARs, they will be reassigned */
 344                 pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_0, 0);
 345                 pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_1, 0);
 346                 pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_2, 0);
 347                 pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_3, 0);
 348         }
 349 }
 350 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
 351                         chrp_pci_fixup_winbond_ata);
 352
 353 /* Pegasos2 firmware version 20040810 configures the built-in IDE controller
 354  * in legacy mode, but sets the PCI registers to PCI native mode.
 355  * The chip can only operate in legacy mode, so force the PCI class into legacy
 356  * mode as well. The same fixup must be done to the class-code property in
 357  * the IDE node /pci@80000000/ide@C,1
 358  */
 359 static void chrp_pci_fixup_vt8231_ata(struct pci_dev *viaide)
 360 {
 361         u8 progif;
 362         struct pci_dev *viaisa;
 363
 364         if (!machine_is(chrp) || _chrp_type != _CHRP_Pegasos)
 365                 return;
 366         if (viaide->irq != 14)
 367                 return;
 368
 369         viaisa = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
 370         if (!viaisa)
 371                 return;
 372         dev_info(&viaide->dev, "Fixing VIA IDE, force legacy mode on\n");
 373
 374         pci_read_config_byte(viaide, PCI_CLASS_PROG, &progif);
 375         pci_write_config_byte(viaide, PCI_CLASS_PROG, progif & ~0x5);
 376         viaide->class &= ~0x5;
 377
 378         pci_dev_put(viaisa);
 379 }
 380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, chrp_pci_fixup_vt8231_ata);