?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
WIP FPC-III support
[linux/fpc-iii.git] / arch / powerpc / sysdev / xive / native.c
blob05a800a3104edda4591f3e49309122f4ece4737f
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2016,2017 IBM Corporation.
4 */
5
6 #define pr_fmt(fmt) "xive: " fmt
7
8 #include <linux/types.h>
9 #include <linux/irq.h>
10 #include <linux/debugfs.h>
11 #include <linux/smp.h>
12 #include <linux/interrupt.h>
13 #include <linux/seq_file.h>
14 #include <linux/init.h>
15 #include <linux/of.h>
16 #include <linux/slab.h>
17 #include <linux/spinlock.h>
18 #include <linux/delay.h>
19 #include <linux/cpumask.h>
20 #include <linux/mm.h>
21 #include <linux/kmemleak.h>
22
23 #include <asm/machdep.h>
24 #include <asm/prom.h>
25 #include <asm/io.h>
26 #include <asm/smp.h>
27 #include <asm/irq.h>
28 #include <asm/errno.h>
29 #include <asm/xive.h>
30 #include <asm/xive-regs.h>
31 #include <asm/opal.h>
32 #include <asm/kvm_ppc.h>
33
34 #include "xive-internal.h"
35
36
37 static u32 xive_provision_size;
38 static u32 *xive_provision_chips;
39 static u32 xive_provision_chip_count;
40 static u32 xive_queue_shift;
41 static u32 xive_pool_vps = XIVE_INVALID_VP;
42 static struct kmem_cache *xive_provision_cache;
43 static bool xive_has_single_esc;
44
45 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
46 {
47 __be64 flags, eoi_page, trig_page;
48 __be32 esb_shift, src_chip;
49 u64 opal_flags;
50 s64 rc;
51
52 memset(data, 0, sizeof(*data));
53
54 rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page,
55 &esb_shift, &src_chip);
56 if (rc) {
57 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n",
58 hw_irq, rc);
59 return -EINVAL;
60 }
61
62 opal_flags = be64_to_cpu(flags);
63 if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI)
64 data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
65 if (opal_flags & OPAL_XIVE_IRQ_LSI)
66 data->flags |= XIVE_IRQ_FLAG_LSI;
67 data->eoi_page = be64_to_cpu(eoi_page);
68 data->trig_page = be64_to_cpu(trig_page);
69 data->esb_shift = be32_to_cpu(esb_shift);
70 data->src_chip = be32_to_cpu(src_chip);
71
72 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
73 if (!data->eoi_mmio) {
74 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
75 return -ENOMEM;
76 }
77
78 data->hw_irq = hw_irq;
79
80 if (!data->trig_page)
81 return 0;
82 if (data->trig_page == data->eoi_page) {
83 data->trig_mmio = data->eoi_mmio;
84 return 0;
85 }
86
87 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
88 if (!data->trig_mmio) {
89 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
90 return -ENOMEM;
91 }
92 return 0;
93 }
94 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data);
95
96 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
97 {
98 s64 rc;
99
100 for (;;) {
101 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq);
102 if (rc != OPAL_BUSY)
103 break;
104 msleep(OPAL_BUSY_DELAY_MS);
105 }
106 return rc == 0 ? 0 : -ENXIO;
107 }
108 EXPORT_SYMBOL_GPL(xive_native_configure_irq);
109
110 static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
111 u32 *sw_irq)
112 {
113 s64 rc;
114 __be64 vp;
115 __be32 lirq;
116
117 rc = opal_xive_get_irq_config(hw_irq, &vp, prio, &lirq);
118
119 *target = be64_to_cpu(vp);
120 *sw_irq = be32_to_cpu(lirq);
121
122 return rc == 0 ? 0 : -ENXIO;
123 }
124
125 #define vp_err(vp, fmt, ...) pr_err("VP[0x%x]: " fmt, vp, ##__VA_ARGS__)
126
127 /* This can be called multiple time to change a queue configuration */
128 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
129 __be32 *qpage, u32 order, bool can_escalate)
130 {
131 s64 rc = 0;
132 __be64 qeoi_page_be;
133 __be32 esc_irq_be;
134 u64 flags, qpage_phys;
135
136 /* If there's an actual queue page, clean it */
137 if (order) {
138 if (WARN_ON(!qpage))
139 return -EINVAL;
140 qpage_phys = __pa(qpage);
141 } else
142 qpage_phys = 0;
143
144 /* Initialize the rest of the fields */
145 q->msk = order ? ((1u << (order - 2)) - 1) : 0;
146 q->idx = 0;
147 q->toggle = 0;
148
149 rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL,
150 &qeoi_page_be,
151 &esc_irq_be,
152 NULL);
153 if (rc) {
154 vp_err(vp_id, "Failed to get queue %d info : %lld\n", prio, rc);
155 rc = -EIO;
156 goto fail;
157 }
158 q->eoi_phys = be64_to_cpu(qeoi_page_be);
159
160 /* Default flags */
161 flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED;
162
163 /* Escalation needed ? */
164 if (can_escalate) {
165 q->esc_irq = be32_to_cpu(esc_irq_be);
166 flags |= OPAL_XIVE_EQ_ESCALATE;
167 }
168
169 /* Configure and enable the queue in HW */
170 for (;;) {
171 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags);
172 if (rc != OPAL_BUSY)
173 break;
174 msleep(OPAL_BUSY_DELAY_MS);
175 }
176 if (rc) {
177 vp_err(vp_id, "Failed to set queue %d info: %lld\n", prio, rc);
178 rc = -EIO;
179 } else {
180 /*
181 * KVM code requires all of the above to be visible before
182 * q->qpage is set due to how it manages IPI EOIs
183 */
184 wmb();
185 q->qpage = qpage;
186 }
187 fail:
188 return rc;
189 }
190 EXPORT_SYMBOL_GPL(xive_native_configure_queue);
191
192 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
193 {
194 s64 rc;
195
196 /* Disable the queue in HW */
197 for (;;) {
198 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0);
199 if (rc != OPAL_BUSY)
200 break;
201 msleep(OPAL_BUSY_DELAY_MS);
202 }
203 if (rc)
204 vp_err(vp_id, "Failed to disable queue %d : %lld\n", prio, rc);
205 }
206
207 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
208 {
209 __xive_native_disable_queue(vp_id, q, prio);
210 }
211 EXPORT_SYMBOL_GPL(xive_native_disable_queue);
212
213 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
214 {
215 struct xive_q *q = &xc->queue[prio];
216 __be32 *qpage;
217
218 qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
219 if (IS_ERR(qpage))
220 return PTR_ERR(qpage);
221
222 return xive_native_configure_queue(get_hard_smp_processor_id(cpu),
223 q, prio, qpage, xive_queue_shift, false);
224 }
225
226 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
227 {
228 struct xive_q *q = &xc->queue[prio];
229 unsigned int alloc_order;
230
231 /*
232 * We use the variant with no iounmap as this is called on exec
233 * from an IPI and iounmap isn't safe
234 */
235 __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio);
236 alloc_order = xive_alloc_order(xive_queue_shift);
237 free_pages((unsigned long)q->qpage, alloc_order);
238 q->qpage = NULL;
239 }
240
241 static bool xive_native_match(struct device_node *node)
242 {
243 return of_device_is_compatible(node, "ibm,opal-xive-vc");
244 }
245
246 static s64 opal_xive_allocate_irq(u32 chip_id)
247 {
248 s64 irq = opal_xive_allocate_irq_raw(chip_id);
249
250 /*
251 * Old versions of skiboot can incorrectly return 0xffffffff to
252 * indicate no space, fix it up here.
253 */
254 return irq == 0xffffffff ? OPAL_RESOURCE : irq;
255 }
256
257 #ifdef CONFIG_SMP
258 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
259 {
260 s64 irq;
261
262 /* Allocate an IPI and populate info about it */
263 for (;;) {
264 irq = opal_xive_allocate_irq(xc->chip_id);
265 if (irq == OPAL_BUSY) {
266 msleep(OPAL_BUSY_DELAY_MS);
267 continue;
268 }
269 if (irq < 0) {
270 pr_err("Failed to allocate IPI on CPU %d\n", cpu);
271 return -ENXIO;
272 }
273 xc->hw_ipi = irq;
274 break;
275 }
276 return 0;
277 }
278 #endif /* CONFIG_SMP */
279
280 u32 xive_native_alloc_irq_on_chip(u32 chip_id)
281 {
282 s64 rc;
283
284 for (;;) {
285 rc = opal_xive_allocate_irq(chip_id);
286 if (rc != OPAL_BUSY)
287 break;
288 msleep(OPAL_BUSY_DELAY_MS);
289 }
290 if (rc < 0)
291 return 0;
292 return rc;
293 }
294 EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip);
295
296 void xive_native_free_irq(u32 irq)
297 {
298 for (;;) {
299 s64 rc = opal_xive_free_irq(irq);
300 if (rc != OPAL_BUSY)
301 break;
302 msleep(OPAL_BUSY_DELAY_MS);
303 }
304 }
305 EXPORT_SYMBOL_GPL(xive_native_free_irq);
306
307 #ifdef CONFIG_SMP
308 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
309 {
310 s64 rc;
311
312 /* Free the IPI */
313 if (xc->hw_ipi == XIVE_BAD_IRQ)
314 return;
315 for (;;) {
316 rc = opal_xive_free_irq(xc->hw_ipi);
317 if (rc == OPAL_BUSY) {
318 msleep(OPAL_BUSY_DELAY_MS);
319 continue;
320 }
321 xc->hw_ipi = XIVE_BAD_IRQ;
322 break;
323 }
324 }
325 #endif /* CONFIG_SMP */
326
327 static void xive_native_shutdown(void)
328 {
329 /* Switch the XIVE to emulation mode */
330 opal_xive_reset(OPAL_XIVE_MODE_EMU);
331 }
332
333 /*
334 * Perform an "ack" cycle on the current thread, thus
335 * grabbing the pending active priorities and updating
336 * the CPPR to the most favored one.
337 */
338 static void xive_native_update_pending(struct xive_cpu *xc)
339 {
340 u8 he, cppr;
341 u16 ack;
342
343 /* Perform the acknowledge hypervisor to register cycle */
344 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG));
345
346 /* Synchronize subsequent queue accesses */
347 mb();
348
349 /*
350 * Grab the CPPR and the "HE" field which indicates the source
351 * of the hypervisor interrupt (if any)
352 */
353 cppr = ack & 0xff;
354 he = (ack >> 8) >> 6;
355 switch(he) {
356 case TM_QW3_NSR_HE_NONE: /* Nothing to see here */
357 break;
358 case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */
359 if (cppr == 0xff)
360 return;
361 /* Mark the priority pending */
362 xc->pending_prio |= 1 << cppr;
363
364 /*
365 * A new interrupt should never have a CPPR less favored
366 * than our current one.
367 */
368 if (cppr >= xc->cppr)
369 pr_err("CPU %d odd ack CPPR, got %d at %d\n",
370 smp_processor_id(), cppr, xc->cppr);
371
372 /* Update our idea of what the CPPR is */
373 xc->cppr = cppr;
374 break;
375 case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */
376 case TM_QW3_NSR_HE_LSI: /* Legacy FW LSI (unused) */
377 pr_err("CPU %d got unexpected interrupt type HE=%d\n",
378 smp_processor_id(), he);
379 return;
380 }
381 }
382
383 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
384 {
385 s64 rc;
386 u32 vp;
387 __be64 vp_cam_be;
388 u64 vp_cam;
389
390 if (xive_pool_vps == XIVE_INVALID_VP)
391 return;
392
393 /* Check if pool VP already active, if it is, pull it */
394 if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP)
395 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
396
397 /* Enable the pool VP */
398 vp = xive_pool_vps + cpu;
399 for (;;) {
400 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
401 if (rc != OPAL_BUSY)
402 break;
403 msleep(OPAL_BUSY_DELAY_MS);
404 }
405 if (rc) {
406 pr_err("Failed to enable pool VP on CPU %d\n", cpu);
407 return;
408 }
409
410 /* Grab it's CAM value */
411 rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
412 if (rc) {
413 pr_err("Failed to get pool VP info CPU %d\n", cpu);
414 return;
415 }
416 vp_cam = be64_to_cpu(vp_cam_be);
417
418 /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
419 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
420 out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam);
421 }
422
423 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
424 {
425 s64 rc;
426 u32 vp;
427
428 if (xive_pool_vps == XIVE_INVALID_VP)
429 return;
430
431 /* Pull the pool VP from the CPU */
432 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
433
434 /* Disable it */
435 vp = xive_pool_vps + cpu;
436 for (;;) {
437 rc = opal_xive_set_vp_info(vp, 0, 0);
438 if (rc != OPAL_BUSY)
439 break;
440 msleep(OPAL_BUSY_DELAY_MS);
441 }
442 }
443
444 void xive_native_sync_source(u32 hw_irq)
445 {
446 opal_xive_sync(XIVE_SYNC_EAS, hw_irq);
447 }
448 EXPORT_SYMBOL_GPL(xive_native_sync_source);
449
450 void xive_native_sync_queue(u32 hw_irq)
451 {
452 opal_xive_sync(XIVE_SYNC_QUEUE, hw_irq);
453 }
454 EXPORT_SYMBOL_GPL(xive_native_sync_queue);
455
456 static const struct xive_ops xive_native_ops = {
457 .populate_irq_data = xive_native_populate_irq_data,
458 .configure_irq = xive_native_configure_irq,
459 .get_irq_config = xive_native_get_irq_config,
460 .setup_queue = xive_native_setup_queue,
461 .cleanup_queue = xive_native_cleanup_queue,
462 .match = xive_native_match,
463 .shutdown = xive_native_shutdown,
464 .update_pending = xive_native_update_pending,
465 .setup_cpu = xive_native_setup_cpu,
466 .teardown_cpu = xive_native_teardown_cpu,
467 .sync_source = xive_native_sync_source,
468 #ifdef CONFIG_SMP
469 .get_ipi = xive_native_get_ipi,
470 .put_ipi = xive_native_put_ipi,
471 #endif /* CONFIG_SMP */
472 .name = "native",
473 };
474
475 static bool xive_parse_provisioning(struct device_node *np)
476 {
477 int rc;
478
479 if (of_property_read_u32(np, "ibm,xive-provision-page-size",
480 &xive_provision_size) < 0)
481 return true;
482 rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4);
483 if (rc < 0) {
484 pr_err("Error %d getting provision chips array\n", rc);
485 return false;
486 }
487 xive_provision_chip_count = rc;
488 if (rc == 0)
489 return true;
490
491 xive_provision_chips = kcalloc(4, xive_provision_chip_count,
492 GFP_KERNEL);
493 if (WARN_ON(!xive_provision_chips))
494 return false;
495
496 rc = of_property_read_u32_array(np, "ibm,xive-provision-chips",
497 xive_provision_chips,
498 xive_provision_chip_count);
499 if (rc < 0) {
500 pr_err("Error %d reading provision chips array\n", rc);
501 return false;
502 }
503
504 xive_provision_cache = kmem_cache_create("xive-provision",
505 xive_provision_size,
506 xive_provision_size,
507 0, NULL);
508 if (!xive_provision_cache) {
509 pr_err("Failed to allocate provision cache\n");
510 return false;
511 }
512 return true;
513 }
514
515 static void xive_native_setup_pools(void)
516 {
517 /* Allocate a pool big enough */
518 pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids);
519
520 xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids);
521 if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP))
522 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n");
523
524 pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n",
525 xive_pool_vps, nr_cpu_ids);
526 }
527
528 u32 xive_native_default_eq_shift(void)
529 {
530 return xive_queue_shift;
531 }
532 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift);
533
534 unsigned long xive_tima_os;
535 EXPORT_SYMBOL_GPL(xive_tima_os);
536
537 bool __init xive_native_init(void)
538 {
539 struct device_node *np;
540 struct resource r;
541 void __iomem *tima;
542 struct property *prop;
543 u8 max_prio = 7;
544 const __be32 *p;
545 u32 val, cpu;
546 s64 rc;
547
548 if (xive_cmdline_disabled)
549 return false;
550
551 pr_devel("xive_native_init()\n");
552 np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe");
553 if (!np) {
554 pr_devel("not found !\n");
555 return false;
556 }
557 pr_devel("Found %pOF\n", np);
558
559 /* Resource 1 is HV window */
560 if (of_address_to_resource(np, 1, &r)) {
561 pr_err("Failed to get thread mgmnt area resource\n");
562 return false;
563 }
564 tima = ioremap(r.start, resource_size(&r));
565 if (!tima) {
566 pr_err("Failed to map thread mgmnt area\n");
567 return false;
568 }
569
570 /* Read number of priorities */
571 if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0)
572 max_prio = val - 1;
573
574 /* Iterate the EQ sizes and pick one */
575 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
576 xive_queue_shift = val;
577 if (val == PAGE_SHIFT)
578 break;
579 }
580
581 /* Do we support single escalation */
582 if (of_get_property(np, "single-escalation-support", NULL) != NULL)
583 xive_has_single_esc = true;
584
585 /* Configure Thread Management areas for KVM */
586 for_each_possible_cpu(cpu)
587 kvmppc_set_xive_tima(cpu, r.start, tima);
588
589 /* Resource 2 is OS window */
590 if (of_address_to_resource(np, 2, &r)) {
591 pr_err("Failed to get thread mgmnt area resource\n");
592 return false;
593 }
594
595 xive_tima_os = r.start;
596
597 /* Grab size of provisionning pages */
598 xive_parse_provisioning(np);
599
600 /* Switch the XIVE to exploitation mode */
601 rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL);
602 if (rc) {
603 pr_err("Switch to exploitation mode failed with error %lld\n", rc);
604 return false;
605 }
606
607 /* Setup some dummy HV pool VPs */
608 xive_native_setup_pools();
609
610 /* Initialize XIVE core with our backend */
611 if (!xive_core_init(np, &xive_native_ops, tima, TM_QW3_HV_PHYS,
612 max_prio)) {
613 opal_xive_reset(OPAL_XIVE_MODE_EMU);
614 return false;
615 }
616 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
617 return true;
618 }
619
620 static bool xive_native_provision_pages(void)
621 {
622 u32 i;
623 void *p;
624
625 for (i = 0; i < xive_provision_chip_count; i++) {
626 u32 chip = xive_provision_chips[i];
627
628 /*
629 * XXX TODO: Try to make the allocation local to the node where
630 * the chip resides.
631 */
632 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL);
633 if (!p) {
634 pr_err("Failed to allocate provisioning page\n");
635 return false;
636 }
637 kmemleak_ignore(p);
638 opal_xive_donate_page(chip, __pa(p));
639 }
640 return true;
641 }
642
643 u32 xive_native_alloc_vp_block(u32 max_vcpus)
644 {
645 s64 rc;
646 u32 order;
647
648 order = fls(max_vcpus) - 1;
649 if (max_vcpus > (1 << order))
650 order++;
651
652 pr_debug("VP block alloc, for max VCPUs %d use order %d\n",
653 max_vcpus, order);
654
655 for (;;) {
656 rc = opal_xive_alloc_vp_block(order);
657 switch (rc) {
658 case OPAL_BUSY:
659 msleep(OPAL_BUSY_DELAY_MS);
660 break;
661 case OPAL_XIVE_PROVISIONING:
662 if (!xive_native_provision_pages())
663 return XIVE_INVALID_VP;
664 break;
665 default:
666 if (rc < 0) {
667 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n",
668 order, rc);
669 return XIVE_INVALID_VP;
670 }
671 return rc;
672 }
673 }
674 }
675 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block);
676
677 void xive_native_free_vp_block(u32 vp_base)
678 {
679 s64 rc;
680
681 if (vp_base == XIVE_INVALID_VP)
682 return;
683
684 rc = opal_xive_free_vp_block(vp_base);
685 if (rc < 0)
686 pr_warn("OPAL error %lld freeing VP block\n", rc);
687 }
688 EXPORT_SYMBOL_GPL(xive_native_free_vp_block);
689
690 int xive_native_enable_vp(u32 vp_id, bool single_escalation)
691 {
692 s64 rc;
693 u64 flags = OPAL_XIVE_VP_ENABLED;
694
695 if (single_escalation)
696 flags |= OPAL_XIVE_VP_SINGLE_ESCALATION;
697 for (;;) {
698 rc = opal_xive_set_vp_info(vp_id, flags, 0);
699 if (rc != OPAL_BUSY)
700 break;
701 msleep(OPAL_BUSY_DELAY_MS);
702 }
703 if (rc)
704 vp_err(vp_id, "Failed to enable VP : %lld\n", rc);
705 return rc ? -EIO : 0;
706 }
707 EXPORT_SYMBOL_GPL(xive_native_enable_vp);
708
709 int xive_native_disable_vp(u32 vp_id)
710 {
711 s64 rc;
712
713 for (;;) {
714 rc = opal_xive_set_vp_info(vp_id, 0, 0);
715 if (rc != OPAL_BUSY)
716 break;
717 msleep(OPAL_BUSY_DELAY_MS);
718 }
719 if (rc)
720 vp_err(vp_id, "Failed to disable VP : %lld\n", rc);
721 return rc ? -EIO : 0;
722 }
723 EXPORT_SYMBOL_GPL(xive_native_disable_vp);
724
725 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id)
726 {
727 __be64 vp_cam_be;
728 __be32 vp_chip_id_be;
729 s64 rc;
730
731 rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
732 if (rc) {
733 vp_err(vp_id, "Failed to get VP info : %lld\n", rc);
734 return -EIO;
735 }
736 *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
737 *out_chip_id = be32_to_cpu(vp_chip_id_be);
738
739 return 0;
740 }
741 EXPORT_SYMBOL_GPL(xive_native_get_vp_info);
742
743 bool xive_native_has_single_escalation(void)
744 {
745 return xive_has_single_esc;
746 }
747 EXPORT_SYMBOL_GPL(xive_native_has_single_escalation);
748
749 int xive_native_get_queue_info(u32 vp_id, u32 prio,
750 u64 *out_qpage,
751 u64 *out_qsize,
752 u64 *out_qeoi_page,
753 u32 *out_escalate_irq,
754 u64 *out_qflags)
755 {
756 __be64 qpage;
757 __be64 qsize;
758 __be64 qeoi_page;
759 __be32 escalate_irq;
760 __be64 qflags;
761 s64 rc;
762
763 rc = opal_xive_get_queue_info(vp_id, prio, &qpage, &qsize,
764 &qeoi_page, &escalate_irq, &qflags);
765 if (rc) {
766 vp_err(vp_id, "failed to get queue %d info : %lld\n", prio, rc);
767 return -EIO;
768 }
769
770 if (out_qpage)
771 *out_qpage = be64_to_cpu(qpage);
772 if (out_qsize)
773 *out_qsize = be32_to_cpu(qsize);
774 if (out_qeoi_page)
775 *out_qeoi_page = be64_to_cpu(qeoi_page);
776 if (out_escalate_irq)
777 *out_escalate_irq = be32_to_cpu(escalate_irq);
778 if (out_qflags)
779 *out_qflags = be64_to_cpu(qflags);
780
781 return 0;
782 }
783 EXPORT_SYMBOL_GPL(xive_native_get_queue_info);
784
785 int xive_native_get_queue_state(u32 vp_id, u32 prio, u32 *qtoggle, u32 *qindex)
786 {
787 __be32 opal_qtoggle;
788 __be32 opal_qindex;
789 s64 rc;
790
791 rc = opal_xive_get_queue_state(vp_id, prio, &opal_qtoggle,
792 &opal_qindex);
793 if (rc) {
794 vp_err(vp_id, "failed to get queue %d state : %lld\n", prio, rc);
795 return -EIO;
796 }
797
798 if (qtoggle)
799 *qtoggle = be32_to_cpu(opal_qtoggle);
800 if (qindex)
801 *qindex = be32_to_cpu(opal_qindex);
802
803 return 0;
804 }
805 EXPORT_SYMBOL_GPL(xive_native_get_queue_state);
806
807 int xive_native_set_queue_state(u32 vp_id, u32 prio, u32 qtoggle, u32 qindex)
808 {
809 s64 rc;
810
811 rc = opal_xive_set_queue_state(vp_id, prio, qtoggle, qindex);
812 if (rc) {
813 vp_err(vp_id, "failed to set queue %d state : %lld\n", prio, rc);
814 return -EIO;
815 }
816
817 return 0;
818 }
819 EXPORT_SYMBOL_GPL(xive_native_set_queue_state);
820
821 bool xive_native_has_queue_state_support(void)
822 {
823 return opal_check_token(OPAL_XIVE_GET_QUEUE_STATE) &&
824 opal_check_token(OPAL_XIVE_SET_QUEUE_STATE);
825 }
826 EXPORT_SYMBOL_GPL(xive_native_has_queue_state_support);
827
828 int xive_native_get_vp_state(u32 vp_id, u64 *out_state)
829 {
830 __be64 state;
831 s64 rc;
832
833 rc = opal_xive_get_vp_state(vp_id, &state);
834 if (rc) {
835 vp_err(vp_id, "failed to get vp state : %lld\n", rc);
836 return -EIO;
837 }
838
839 if (out_state)
840 *out_state = be64_to_cpu(state);
841 return 0;
842 }
843 EXPORT_SYMBOL_GPL(xive_native_get_vp_state);
844
845 machine_arch_initcall(powernv, xive_core_debug_init);
Linux with added FPC-III support