arch/sh/include/cpu-sh4/cpu/cache.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * include/asm-sh/cpu-sh4/cache.h
   4  *
   5  * Copyright (C) 1999 Niibe Yutaka
   6  */
   7 #ifndef __ASM_CPU_SH4_CACHE_H
   8 #define __ASM_CPU_SH4_CACHE_H
   9
  10 #define L1_CACHE_SHIFT  5
  11
  12 #define SH_CACHE_VALID          1
  13 #define SH_CACHE_UPDATED        2
  14 #define SH_CACHE_COMBINED       4
  15 #define SH_CACHE_ASSOC          8
  16
  17 #define SH_CCR          0xff00001c      /* Address of Cache Control Register */
  18 #define CCR_CACHE_OCE   0x0001  /* Operand Cache Enable */
  19 #define CCR_CACHE_WT    0x0002  /* Write-Through (for P0,U0,P3) (else writeback)*/
  20 #define CCR_CACHE_CB    0x0004  /* Copy-Back (for P1) (else writethrough) */
  21 #define CCR_CACHE_OCI   0x0008  /* OC Invalidate */
  22 #define CCR_CACHE_ORA   0x0020  /* OC RAM Mode */
  23 #define CCR_CACHE_OIX   0x0080  /* OC Index Enable */
  24 #define CCR_CACHE_ICE   0x0100  /* Instruction Cache Enable */
  25 #define CCR_CACHE_ICI   0x0800  /* IC Invalidate */
  26 #define CCR_CACHE_IIX   0x8000  /* IC Index Enable */
  27 #ifndef CONFIG_CPU_SH4A
  28 #define CCR_CACHE_EMODE 0x80000000      /* EMODE Enable */
  29 #endif
  30
  31 /* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
  32 #define CCR_CACHE_ENABLE        (CCR_CACHE_OCE|CCR_CACHE_ICE)
  33 #define CCR_CACHE_INVALIDATE    (CCR_CACHE_OCI|CCR_CACHE_ICI)
  34
  35 #define CACHE_IC_ADDRESS_ARRAY  0xf0000000
  36 #define CACHE_OC_ADDRESS_ARRAY  0xf4000000
  37
  38 #define RAMCR                   0xFF000074
  39
  40 #endif /* __ASM_CPU_SH4_CACHE_H */
  41