arch/sparc/include/asm/dcr.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _SPARC64_DCR_H
   3 #define _SPARC64_DCR_H
   4
   5 /* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */
   6 #define DCR_DPE         0x0000000000001000 /* III+: D$ Parity Error Enable      */
   7 #define DCR_OBS         0x0000000000000fc0 /* Observability Bus Controls        */
   8 #define DCR_BPE         0x0000000000000020 /* Branch Predict Enable             */
   9 #define DCR_RPE         0x0000000000000010 /* Return Address Prediction Enable  */
  10 #define DCR_SI          0x0000000000000008 /* Single Instruction Disable        */
  11 #define DCR_IPE         0x0000000000000004 /* III+: I$ Parity Error Enable      */
  12 #define DCR_IFPOE       0x0000000000000002 /* IRQ FP Operation Enable           */
  13 #define DCR_MS          0x0000000000000001 /* Multi-Scalar dispatch             */
  14
  15 #endif /* _SPARC64_DCR_H */