1 /* SPDX-License-Identifier: GPL-2.0 */
3 * hypersparc.S: High speed Hypersparc mmu/cache operations.
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
8 #include <asm/ptrace.h>
10 #include <asm/asm-offsets.h>
13 #include <asm/pgtable.h>
14 #include <asm/pgtsrmmu.h>
15 #include <linux/init.h>
20 .globl hypersparc_flush_cache_all, hypersparc_flush_cache_mm
21 .globl hypersparc_flush_cache_range, hypersparc_flush_cache_page
22 .globl hypersparc_flush_page_to_ram
23 .globl hypersparc_flush_page_for_dma, hypersparc_flush_sig_insns
24 .globl hypersparc_flush_tlb_all, hypersparc_flush_tlb_mm
25 .globl hypersparc_flush_tlb_range, hypersparc_flush_tlb_page
27 hypersparc_flush_cache_all:
28 WINDOW_FLUSH(%g4, %g5)
29 sethi %hi(vac_cache_size), %g4
30 ld [%g4 + %lo(vac_cache_size)], %g5
31 sethi %hi(vac_line_size), %g1
32 ld [%g1 + %lo(vac_line_size)], %g2
34 subcc %g5, %g2, %g5 ! hyper_flush_unconditional_combined
36 sta %g0, [%g5] ASI_M_FLUSH_CTX
38 sta %g0, [%g0] ASI_M_FLUSH_IWHOLE ! hyper_flush_whole_icache
40 /* We expand the window flush to get maximum performance. */
41 hypersparc_flush_cache_mm:
43 ld [%o0 + AOFF_mm_context], %g1
45 be hypersparc_flush_cache_mm_out
47 WINDOW_FLUSH(%g4, %g5)
49 sethi %hi(vac_line_size), %g1
50 ld [%g1 + %lo(vac_line_size)], %o1
51 sethi %hi(vac_cache_size), %g2
52 ld [%g2 + %lo(vac_cache_size)], %o0
63 subcc %o0, %o5, %o0 ! hyper_flush_cache_user
64 sta %g0, [%o0 + %g0] ASI_M_FLUSH_USER
65 sta %g0, [%o0 + %o1] ASI_M_FLUSH_USER
66 sta %g0, [%o0 + %g1] ASI_M_FLUSH_USER
67 sta %g0, [%o0 + %g2] ASI_M_FLUSH_USER
68 sta %g0, [%o0 + %g3] ASI_M_FLUSH_USER
69 sta %g0, [%o0 + %g4] ASI_M_FLUSH_USER
70 sta %g0, [%o0 + %g5] ASI_M_FLUSH_USER
72 sta %g0, [%o0 + %o4] ASI_M_FLUSH_USER
73 hypersparc_flush_cache_mm_out:
77 /* The things we do for performance... */
78 hypersparc_flush_cache_range:
79 ld [%o0 + VMA_VM_MM], %o0
81 ld [%o0 + AOFF_mm_context], %g1
83 be hypersparc_flush_cache_range_out
85 WINDOW_FLUSH(%g4, %g5)
87 sethi %hi(vac_line_size), %g1
88 ld [%g1 + %lo(vac_line_size)], %o4
89 sethi %hi(vac_cache_size), %g2
90 ld [%g2 + %lo(vac_cache_size)], %o3
92 /* Here comes the fun part... */
93 add %o2, (PAGE_SIZE - 1), %o2
94 andn %o1, (PAGE_SIZE - 1), %o1
96 andn %o2, (PAGE_SIZE - 1), %o2
108 /* Flush entire user space, believe it or not this is quicker
109 * than page at a time flushings for range > (cache_size<<2).
113 sta %g0, [%o3 + %g0] ASI_M_FLUSH_USER
114 sta %g0, [%o3 + %o4] ASI_M_FLUSH_USER
115 sta %g0, [%o3 + %o5] ASI_M_FLUSH_USER
116 sta %g0, [%o3 + %g1] ASI_M_FLUSH_USER
117 sta %g0, [%o3 + %g2] ASI_M_FLUSH_USER
118 sta %g0, [%o3 + %g3] ASI_M_FLUSH_USER
119 sta %g0, [%o3 + %g4] ASI_M_FLUSH_USER
121 sta %g0, [%o3 + %g5] ASI_M_FLUSH_USER
125 /* Below our threshold, flush one page at a time. */
127 ld [%o0 + AOFF_mm_context], %o0
128 mov SRMMU_CTX_REG, %g7
129 lda [%g7] ASI_M_MMUREGS, %o3
130 sta %o0, [%g7] ASI_M_MMUREGS
131 add %o2, -PAGE_SIZE, %o0
134 lda [%g7] ASI_M_FLUSH_PROBE, %g7
141 sta %g0, [%o2 + %g0] ASI_M_FLUSH_PAGE
142 sta %g0, [%o2 + %o4] ASI_M_FLUSH_PAGE
143 sta %g0, [%o2 + %o5] ASI_M_FLUSH_PAGE
144 sta %g0, [%o2 + %g1] ASI_M_FLUSH_PAGE
145 sta %g0, [%o2 + %g2] ASI_M_FLUSH_PAGE
146 sta %g0, [%o2 + %g3] ASI_M_FLUSH_PAGE
147 andcc %o2, 0xffc, %g0
148 sta %g0, [%o2 + %g4] ASI_M_FLUSH_PAGE
150 sta %g0, [%o2 + %g5] ASI_M_FLUSH_PAGE
154 add %o2, -PAGE_SIZE, %o0
155 mov SRMMU_FAULT_STATUS, %g5
156 lda [%g5] ASI_M_MMUREGS, %g0
157 mov SRMMU_CTX_REG, %g7
158 sta %o3, [%g7] ASI_M_MMUREGS
159 hypersparc_flush_cache_range_out:
163 /* HyperSparc requires a valid mapping where we are about to flush
164 * in order to check for a physical tag match during the flush.
166 /* Verified, my ass... */
167 hypersparc_flush_cache_page:
168 ld [%o0 + VMA_VM_MM], %o0
169 ld [%o0 + AOFF_mm_context], %g2
172 be hypersparc_flush_cache_page_out
174 WINDOW_FLUSH(%g4, %g5)
176 sethi %hi(vac_line_size), %g1
177 ld [%g1 + %lo(vac_line_size)], %o4
178 mov SRMMU_CTX_REG, %o3
179 andn %o1, (PAGE_SIZE - 1), %o1
180 lda [%o3] ASI_M_MMUREGS, %o2
181 sta %g2, [%o3] ASI_M_MMUREGS
183 lda [%o5] ASI_M_FLUSH_PROBE, %g1
187 sub %o1, -PAGE_SIZE, %o1
198 sta %g0, [%o1 + %g0] ASI_M_FLUSH_PAGE
199 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
200 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
201 sta %g0, [%o1 + %g1] ASI_M_FLUSH_PAGE
202 sta %g0, [%o1 + %g2] ASI_M_FLUSH_PAGE
203 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
204 andcc %o1, 0xffc, %g0
205 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
207 sta %g0, [%o1 + %g5] ASI_M_FLUSH_PAGE
209 mov SRMMU_FAULT_STATUS, %g7
210 mov SRMMU_CTX_REG, %g4
211 lda [%g7] ASI_M_MMUREGS, %g0
212 sta %o2, [%g4] ASI_M_MMUREGS
213 hypersparc_flush_cache_page_out:
217 hypersparc_flush_sig_insns:
222 /* HyperSparc is copy-back. */
223 hypersparc_flush_page_to_ram:
224 sethi %hi(vac_line_size), %g1
225 ld [%g1 + %lo(vac_line_size)], %o4
226 andn %o0, (PAGE_SIZE - 1), %o0
229 lda [%g7] ASI_M_FLUSH_PROBE, %g5
235 sub %o0, -PAGE_SIZE, %o0
243 sta %g0, [%o0 + %g0] ASI_M_FLUSH_PAGE
244 sta %g0, [%o0 + %o4] ASI_M_FLUSH_PAGE
245 sta %g0, [%o0 + %o5] ASI_M_FLUSH_PAGE
246 sta %g0, [%o0 + %g1] ASI_M_FLUSH_PAGE
247 sta %g0, [%o0 + %g2] ASI_M_FLUSH_PAGE
248 sta %g0, [%o0 + %g3] ASI_M_FLUSH_PAGE
249 andcc %o0, 0xffc, %g0
250 sta %g0, [%o0 + %g4] ASI_M_FLUSH_PAGE
252 sta %g0, [%o0 + %g5] ASI_M_FLUSH_PAGE
254 mov SRMMU_FAULT_STATUS, %g1
256 lda [%g1] ASI_M_MMUREGS, %g0
258 /* HyperSparc is IO cache coherent. */
259 hypersparc_flush_page_for_dma:
263 /* It was noted that at boot time a TLB flush all in a delay slot
264 * can deliver an illegal instruction to the processor if the timing
267 hypersparc_flush_tlb_all:
269 sta %g0, [%g1] ASI_M_FLUSH_PROBE
273 hypersparc_flush_tlb_mm:
274 mov SRMMU_CTX_REG, %g1
275 ld [%o0 + AOFF_mm_context], %o1
276 lda [%g1] ASI_M_MMUREGS, %g5
279 be hypersparc_flush_tlb_mm_out
282 sta %o1, [%g1] ASI_M_MMUREGS
283 sta %g0, [%g2] ASI_M_FLUSH_PROBE
284 hypersparc_flush_tlb_mm_out:
286 sta %g5, [%g1] ASI_M_MMUREGS
288 hypersparc_flush_tlb_range:
289 ld [%o0 + VMA_VM_MM], %o0
290 mov SRMMU_CTX_REG, %g1
291 ld [%o0 + AOFF_mm_context], %o3
292 lda [%g1] ASI_M_MMUREGS, %g5
295 be hypersparc_flush_tlb_range_out
297 sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
298 sta %o3, [%g1] ASI_M_MMUREGS
301 sta %g0, [%o1] ASI_M_FLUSH_PROBE
306 sta %g0, [%o1] ASI_M_FLUSH_PROBE
307 hypersparc_flush_tlb_range_out:
309 sta %g5, [%g1] ASI_M_MMUREGS
311 hypersparc_flush_tlb_page:
312 ld [%o0 + VMA_VM_MM], %o0
313 mov SRMMU_CTX_REG, %g1
314 ld [%o0 + AOFF_mm_context], %o3
315 andn %o1, (PAGE_SIZE - 1), %o1
318 be hypersparc_flush_tlb_page_out
320 lda [%g1] ASI_M_MMUREGS, %g5
321 sta %o3, [%g1] ASI_M_MMUREGS
322 sta %g0, [%o1] ASI_M_FLUSH_PROBE
323 hypersparc_flush_tlb_page_out:
325 sta %g5, [%g1] ASI_M_MMUREGS
329 /* High speed page clear/copy. */
330 hypersparc_bzero_1page:
331 /* NOTE: This routine has to be shorter than 40insns --jj */
342 stda %g0, [%o0 + %g0] ASI_M_BFILL
343 stda %g0, [%o0 + %g2] ASI_M_BFILL
344 stda %g0, [%o0 + %g3] ASI_M_BFILL
345 stda %g0, [%o0 + %g4] ASI_M_BFILL
346 stda %g0, [%o0 + %g5] ASI_M_BFILL
347 stda %g0, [%o0 + %g7] ASI_M_BFILL
348 stda %g0, [%o0 + %o2] ASI_M_BFILL
349 stda %g0, [%o0 + %o3] ASI_M_BFILL
357 hypersparc_copy_1page:
358 /* NOTE: This routine has to be shorter than 70insns --jj */
359 sub %o1, %o0, %o2 ! difference
362 sta %o0, [%o0 + %o2] ASI_M_BCOPY
364 sta %o0, [%o0 + %o2] ASI_M_BCOPY
366 sta %o0, [%o0 + %o2] ASI_M_BCOPY
368 sta %o0, [%o0 + %o2] ASI_M_BCOPY
370 sta %o0, [%o0 + %o2] ASI_M_BCOPY
372 sta %o0, [%o0 + %o2] ASI_M_BCOPY
374 sta %o0, [%o0 + %o2] ASI_M_BCOPY
376 sta %o0, [%o0 + %o2] ASI_M_BCOPY
384 .globl hypersparc_setup_blockops
385 hypersparc_setup_blockops:
386 sethi %hi(bzero_1page), %o0
387 or %o0, %lo(bzero_1page), %o0
388 sethi %hi(hypersparc_bzero_1page), %o1
389 or %o1, %lo(hypersparc_bzero_1page), %o1
390 sethi %hi(hypersparc_copy_1page), %o2
391 or %o2, %lo(hypersparc_copy_1page), %o2
400 sethi %hi(__copy_1page), %o0
401 or %o0, %lo(__copy_1page), %o0
402 sethi %hi(hypersparc_setup_blockops), %o2
403 or %o2, %lo(hypersparc_setup_blockops), %o2
412 sta %g0, [%g0] ASI_M_FLUSH_IWHOLE