arch/x86/include/asm/fpu/api.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 1994 Linus Torvalds
   4  *
   5  * Pentium III FXSR, SSE support
   6  * General FPU state handling cleanups
   7  *      Gareth Hughes <gareth@valinux.com>, May 2000
   8  * x86-64 work by Andi Kleen 2002
   9  */
  10
  11 #ifndef _ASM_X86_FPU_API_H
  12 #define _ASM_X86_FPU_API_H
  13 #include <linux/bottom_half.h>
  14
  15 /*
  16  * Use kernel_fpu_begin/end() if you intend to use FPU in kernel context. It
  17  * disables preemption so be careful if you intend to use it for long periods
  18  * of time.
  19  * If you intend to use the FPU in softirq you need to check first with
  20  * irq_fpu_usable() if it is possible.
  21  */
  22 extern void kernel_fpu_begin(void);
  23 extern void kernel_fpu_end(void);
  24 extern bool irq_fpu_usable(void);
  25 extern void fpregs_mark_activate(void);
  26
  27 /*
  28  * Use fpregs_lock() while editing CPU's FPU registers or fpu->state.
  29  * A context switch will (and softirq might) save CPU's FPU registers to
  30  * fpu->state and set TIF_NEED_FPU_LOAD leaving CPU's FPU registers in
  31  * a random state.
  32  *
  33  * local_bh_disable() protects against both preemption and soft interrupts
  34  * on !RT kernels.
  35  *
  36  * On RT kernels local_bh_disable() is not sufficient because it only
  37  * serializes soft interrupt related sections via a local lock, but stays
  38  * preemptible. Disabling preemption is the right choice here as bottom
  39  * half processing is always in thread context on RT kernels so it
  40  * implicitly prevents bottom half processing as well.
  41  *
  42  * Disabling preemption also serializes against kernel_fpu_begin().
  43  */
  44 static inline void fpregs_lock(void)
  45 {
  46         if (!IS_ENABLED(CONFIG_PREEMPT_RT))
  47                 local_bh_disable();
  48         else
  49                 preempt_disable();
  50 }
  51
  52 static inline void fpregs_unlock(void)
  53 {
  54         if (!IS_ENABLED(CONFIG_PREEMPT_RT))
  55                 local_bh_enable();
  56         else
  57                 preempt_enable();
  58 }
  59
  60 #ifdef CONFIG_X86_DEBUG_FPU
  61 extern void fpregs_assert_state_consistent(void);
  62 #else
  63 static inline void fpregs_assert_state_consistent(void) { }
  64 #endif
  65
  66 /*
  67  * Load the task FPU state before returning to userspace.
  68  */
  69 extern void switch_fpu_return(void);
  70
  71 /*
  72  * Query the presence of one or more xfeatures. Works on any legacy CPU as well.
  73  *
  74  * If 'feature_name' is set then put a human-readable description of
  75  * the feature there as well - this can be used to print error (or success)
  76  * messages.
  77  */
  78 extern int cpu_has_xfeatures(u64 xfeatures_mask, const char **feature_name);
  79
  80 /*
  81  * Tasks that are not using SVA have mm->pasid set to zero to note that they
  82  * will not have the valid bit set in MSR_IA32_PASID while they are running.
  83  */
  84 #define PASID_DISABLED  0
  85
  86 #ifdef CONFIG_IOMMU_SUPPORT
  87 /* Update current's PASID MSR/state by mm's PASID. */
  88 void update_pasid(void);
  89 #else
  90 static inline void update_pasid(void) { }
  91 #endif
  92 #endif /* _ASM_X86_FPU_API_H */