1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <asm/errno.h>
11 #include <asm/cpumask.h>
12 #include <uapi/asm/msr.h>
31 struct msr_regs_info
{
43 struct saved_msr
*array
;
47 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
48 * constraint has different meanings. For i386, "A" means exactly
49 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
50 * it means rax *or* rdx.
53 /* Using 64-bit values saves one instruction clearing the high half of low */
54 #define DECLARE_ARGS(val, low, high) unsigned long low, high
55 #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32)
56 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
58 #define DECLARE_ARGS(val, low, high) unsigned long long val
59 #define EAX_EDX_VAL(val, low, high) (val)
60 #define EAX_EDX_RET(val, low, high) "=A" (val)
64 * Be very careful with includes. This header is prone to include loops.
66 #include <asm/atomic.h>
67 #include <linux/tracepoint-defs.h>
69 #ifdef CONFIG_TRACEPOINTS
70 DECLARE_TRACEPOINT(read_msr
);
71 DECLARE_TRACEPOINT(write_msr
);
72 DECLARE_TRACEPOINT(rdpmc
);
73 extern void do_trace_write_msr(unsigned int msr
, u64 val
, int failed
);
74 extern void do_trace_read_msr(unsigned int msr
, u64 val
, int failed
);
75 extern void do_trace_rdpmc(unsigned int msr
, u64 val
, int failed
);
77 static inline void do_trace_write_msr(unsigned int msr
, u64 val
, int failed
) {}
78 static inline void do_trace_read_msr(unsigned int msr
, u64 val
, int failed
) {}
79 static inline void do_trace_rdpmc(unsigned int msr
, u64 val
, int failed
) {}
83 * __rdmsr() and __wrmsr() are the two primitives which are the bare minimum MSR
84 * accessors and should not have any tracing or other functionality piggybacking
85 * on them - those are *purely* for accessing MSRs and nothing more. So don't even
86 * think of extending them - you will be slapped with a stinking trout or a frozen
87 * shark will reach you, wherever you are! You've been warned.
89 static inline unsigned long long notrace
__rdmsr(unsigned int msr
)
91 DECLARE_ARGS(val
, low
, high
);
93 asm volatile("1: rdmsr\n"
95 _ASM_EXTABLE_HANDLE(1b
, 2b
, ex_handler_rdmsr_unsafe
)
96 : EAX_EDX_RET(val
, low
, high
) : "c" (msr
));
98 return EAX_EDX_VAL(val
, low
, high
);
101 static inline void notrace
__wrmsr(unsigned int msr
, u32 low
, u32 high
)
103 asm volatile("1: wrmsr\n"
105 _ASM_EXTABLE_HANDLE(1b
, 2b
, ex_handler_wrmsr_unsafe
)
106 : : "c" (msr
), "a"(low
), "d" (high
) : "memory");
109 #define native_rdmsr(msr, val1, val2) \
111 u64 __val = __rdmsr((msr)); \
112 (void)((val1) = (u32)__val); \
113 (void)((val2) = (u32)(__val >> 32)); \
116 #define native_wrmsr(msr, low, high) \
117 __wrmsr(msr, low, high)
119 #define native_wrmsrl(msr, val) \
120 __wrmsr((msr), (u32)((u64)(val)), \
121 (u32)((u64)(val) >> 32))
123 static inline unsigned long long native_read_msr(unsigned int msr
)
125 unsigned long long val
;
129 if (tracepoint_enabled(read_msr
))
130 do_trace_read_msr(msr
, val
, 0);
135 static inline unsigned long long native_read_msr_safe(unsigned int msr
,
138 DECLARE_ARGS(val
, low
, high
);
140 asm volatile("2: rdmsr ; xor %[err],%[err]\n"
142 ".section .fixup,\"ax\"\n\t"
143 "3: mov %[fault],%[err]\n\t"
144 "xorl %%eax, %%eax\n\t"
145 "xorl %%edx, %%edx\n\t"
149 : [err
] "=r" (*err
), EAX_EDX_RET(val
, low
, high
)
150 : "c" (msr
), [fault
] "i" (-EIO
));
151 if (tracepoint_enabled(read_msr
))
152 do_trace_read_msr(msr
, EAX_EDX_VAL(val
, low
, high
), *err
);
153 return EAX_EDX_VAL(val
, low
, high
);
156 /* Can be uninlined because referenced by paravirt */
157 static inline void notrace
158 native_write_msr(unsigned int msr
, u32 low
, u32 high
)
160 __wrmsr(msr
, low
, high
);
162 if (tracepoint_enabled(write_msr
))
163 do_trace_write_msr(msr
, ((u64
)high
<< 32 | low
), 0);
166 /* Can be uninlined because referenced by paravirt */
167 static inline int notrace
168 native_write_msr_safe(unsigned int msr
, u32 low
, u32 high
)
172 asm volatile("2: wrmsr ; xor %[err],%[err]\n"
174 ".section .fixup,\"ax\"\n\t"
175 "3: mov %[fault],%[err] ; jmp 1b\n\t"
179 : "c" (msr
), "0" (low
), "d" (high
),
182 if (tracepoint_enabled(write_msr
))
183 do_trace_write_msr(msr
, ((u64
)high
<< 32 | low
), err
);
187 extern int rdmsr_safe_regs(u32 regs
[8]);
188 extern int wrmsr_safe_regs(u32 regs
[8]);
191 * rdtsc() - returns the current TSC without ordering constraints
193 * rdtsc() returns the result of RDTSC as a 64-bit integer. The
194 * only ordering constraint it supplies is the ordering implied by
195 * "asm volatile": it will put the RDTSC in the place you expect. The
196 * CPU can and will speculatively execute that RDTSC, though, so the
197 * results can be non-monotonic if compared on different CPUs.
199 static __always_inline
unsigned long long rdtsc(void)
201 DECLARE_ARGS(val
, low
, high
);
203 asm volatile("rdtsc" : EAX_EDX_RET(val
, low
, high
));
205 return EAX_EDX_VAL(val
, low
, high
);
209 * rdtsc_ordered() - read the current TSC in program order
211 * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer.
212 * It is ordered like a load to a global in-memory counter. It should
213 * be impossible to observe non-monotonic rdtsc_unordered() behavior
214 * across multiple CPUs as long as the TSC is synced.
216 static __always_inline
unsigned long long rdtsc_ordered(void)
218 DECLARE_ARGS(val
, low
, high
);
221 * The RDTSC instruction is not ordered relative to memory
222 * access. The Intel SDM and the AMD APM are both vague on this
223 * point, but empirically an RDTSC instruction can be
224 * speculatively executed before prior loads. An RDTSC
225 * immediately after an appropriate barrier appears to be
226 * ordered as a normal load, that is, it provides the same
227 * ordering guarantees as reading from a global memory location
228 * that some other imaginary CPU is updating continuously with a
231 * Thus, use the preferred barrier on the respective CPU, aiming for
232 * RDTSCP as the default.
234 asm volatile(ALTERNATIVE_2("rdtsc",
235 "lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC
,
236 "rdtscp", X86_FEATURE_RDTSCP
)
237 : EAX_EDX_RET(val
, low
, high
)
238 /* RDTSCP clobbers ECX with MSR_TSC_AUX. */
241 return EAX_EDX_VAL(val
, low
, high
);
244 static inline unsigned long long native_read_pmc(int counter
)
246 DECLARE_ARGS(val
, low
, high
);
248 asm volatile("rdpmc" : EAX_EDX_RET(val
, low
, high
) : "c" (counter
));
249 if (tracepoint_enabled(rdpmc
))
250 do_trace_rdpmc(counter
, EAX_EDX_VAL(val
, low
, high
), 0);
251 return EAX_EDX_VAL(val
, low
, high
);
254 #ifdef CONFIG_PARAVIRT_XXL
255 #include <asm/paravirt.h>
257 #include <linux/errno.h>
259 * Access to machine-specific registers (available on 586 and better only)
260 * Note: the rd* operations modify the parameters directly (without using
261 * pointer indirection), this allows gcc to optimize better
264 #define rdmsr(msr, low, high) \
266 u64 __val = native_read_msr((msr)); \
267 (void)((low) = (u32)__val); \
268 (void)((high) = (u32)(__val >> 32)); \
271 static inline void wrmsr(unsigned int msr
, u32 low
, u32 high
)
273 native_write_msr(msr
, low
, high
);
276 #define rdmsrl(msr, val) \
277 ((val) = native_read_msr((msr)))
279 static inline void wrmsrl(unsigned int msr
, u64 val
)
281 native_write_msr(msr
, (u32
)(val
& 0xffffffffULL
), (u32
)(val
>> 32));
284 /* wrmsr with exception handling */
285 static inline int wrmsr_safe(unsigned int msr
, u32 low
, u32 high
)
287 return native_write_msr_safe(msr
, low
, high
);
290 /* rdmsr with exception handling */
291 #define rdmsr_safe(msr, low, high) \
294 u64 __val = native_read_msr_safe((msr), &__err); \
295 (*low) = (u32)__val; \
296 (*high) = (u32)(__val >> 32); \
300 static inline int rdmsrl_safe(unsigned int msr
, unsigned long long *p
)
304 *p
= native_read_msr_safe(msr
, &err
);
308 #define rdpmc(counter, low, high) \
310 u64 _l = native_read_pmc((counter)); \
312 (high) = (u32)(_l >> 32); \
315 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
317 #endif /* !CONFIG_PARAVIRT_XXL */
320 * 64-bit version of wrmsr_safe():
322 static inline int wrmsrl_safe(u32 msr
, u64 val
)
324 return wrmsr_safe(msr
, (u32
)val
, (u32
)(val
>> 32));
327 #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high))
329 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
331 struct msr
*msrs_alloc(void);
332 void msrs_free(struct msr
*msrs
);
333 int msr_set_bit(u32 msr
, u8 bit
);
334 int msr_clear_bit(u32 msr
, u8 bit
);
337 int rdmsr_on_cpu(unsigned int cpu
, u32 msr_no
, u32
*l
, u32
*h
);
338 int wrmsr_on_cpu(unsigned int cpu
, u32 msr_no
, u32 l
, u32 h
);
339 int rdmsrl_on_cpu(unsigned int cpu
, u32 msr_no
, u64
*q
);
340 int wrmsrl_on_cpu(unsigned int cpu
, u32 msr_no
, u64 q
);
341 void rdmsr_on_cpus(const struct cpumask
*mask
, u32 msr_no
, struct msr
*msrs
);
342 void wrmsr_on_cpus(const struct cpumask
*mask
, u32 msr_no
, struct msr
*msrs
);
343 int rdmsr_safe_on_cpu(unsigned int cpu
, u32 msr_no
, u32
*l
, u32
*h
);
344 int wrmsr_safe_on_cpu(unsigned int cpu
, u32 msr_no
, u32 l
, u32 h
);
345 int rdmsrl_safe_on_cpu(unsigned int cpu
, u32 msr_no
, u64
*q
);
346 int wrmsrl_safe_on_cpu(unsigned int cpu
, u32 msr_no
, u64 q
);
347 int rdmsr_safe_regs_on_cpu(unsigned int cpu
, u32 regs
[8]);
348 int wrmsr_safe_regs_on_cpu(unsigned int cpu
, u32 regs
[8]);
349 #else /* CONFIG_SMP */
350 static inline int rdmsr_on_cpu(unsigned int cpu
, u32 msr_no
, u32
*l
, u32
*h
)
352 rdmsr(msr_no
, *l
, *h
);
355 static inline int wrmsr_on_cpu(unsigned int cpu
, u32 msr_no
, u32 l
, u32 h
)
360 static inline int rdmsrl_on_cpu(unsigned int cpu
, u32 msr_no
, u64
*q
)
365 static inline int wrmsrl_on_cpu(unsigned int cpu
, u32 msr_no
, u64 q
)
370 static inline void rdmsr_on_cpus(const struct cpumask
*m
, u32 msr_no
,
373 rdmsr_on_cpu(0, msr_no
, &(msrs
[0].l
), &(msrs
[0].h
));
375 static inline void wrmsr_on_cpus(const struct cpumask
*m
, u32 msr_no
,
378 wrmsr_on_cpu(0, msr_no
, msrs
[0].l
, msrs
[0].h
);
380 static inline int rdmsr_safe_on_cpu(unsigned int cpu
, u32 msr_no
,
383 return rdmsr_safe(msr_no
, l
, h
);
385 static inline int wrmsr_safe_on_cpu(unsigned int cpu
, u32 msr_no
, u32 l
, u32 h
)
387 return wrmsr_safe(msr_no
, l
, h
);
389 static inline int rdmsrl_safe_on_cpu(unsigned int cpu
, u32 msr_no
, u64
*q
)
391 return rdmsrl_safe(msr_no
, q
);
393 static inline int wrmsrl_safe_on_cpu(unsigned int cpu
, u32 msr_no
, u64 q
)
395 return wrmsrl_safe(msr_no
, q
);
397 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu
, u32 regs
[8])
399 return rdmsr_safe_regs(regs
);
401 static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu
, u32 regs
[8])
403 return wrmsr_safe_regs(regs
);
405 #endif /* CONFIG_SMP */
406 #endif /* __ASSEMBLY__ */
407 #endif /* _ASM_X86_MSR_H */