arch/x86/include/asm/msr.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_MSR_H
   3 #define _ASM_X86_MSR_H
   4
   5 #include "msr-index.h"
   6
   7 #ifndef __ASSEMBLY__
   8
   9 #include <asm/asm.h>
  10 #include <asm/errno.h>
  11 #include <asm/cpumask.h>
  12 #include <uapi/asm/msr.h>
  13
  14 struct msr {
  15         union {
  16                 struct {
  17                         u32 l;
  18                         u32 h;
  19                 };
  20                 u64 q;
  21         };
  22 };
  23
  24 struct msr_info {
  25         u32 msr_no;
  26         struct msr reg;
  27         struct msr *msrs;
  28         int err;
  29 };
  30
  31 struct msr_regs_info {
  32         u32 *regs;
  33         int err;
  34 };
  35
  36 struct saved_msr {
  37         bool valid;
  38         struct msr_info info;
  39 };
  40
  41 struct saved_msrs {
  42         unsigned int num;
  43         struct saved_msr *array;
  44 };
  45
  46 /*
  47  * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
  48  * constraint has different meanings. For i386, "A" means exactly
  49  * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
  50  * it means rax *or* rdx.
  51  */
  52 #ifdef CONFIG_X86_64
  53 /* Using 64-bit values saves one instruction clearing the high half of low */
  54 #define DECLARE_ARGS(val, low, high)    unsigned long low, high
  55 #define EAX_EDX_VAL(val, low, high)     ((low) | (high) << 32)
  56 #define EAX_EDX_RET(val, low, high)     "=a" (low), "=d" (high)
  57 #else
  58 #define DECLARE_ARGS(val, low, high)    unsigned long long val
  59 #define EAX_EDX_VAL(val, low, high)     (val)
  60 #define EAX_EDX_RET(val, low, high)     "=A" (val)
  61 #endif
  62
  63 /*
  64  * Be very careful with includes. This header is prone to include loops.
  65  */
  66 #include <asm/atomic.h>
  67 #include <linux/tracepoint-defs.h>
  68
  69 #ifdef CONFIG_TRACEPOINTS
  70 DECLARE_TRACEPOINT(read_msr);
  71 DECLARE_TRACEPOINT(write_msr);
  72 DECLARE_TRACEPOINT(rdpmc);
  73 extern void do_trace_write_msr(unsigned int msr, u64 val, int failed);
  74 extern void do_trace_read_msr(unsigned int msr, u64 val, int failed);
  75 extern void do_trace_rdpmc(unsigned int msr, u64 val, int failed);
  76 #else
  77 static inline void do_trace_write_msr(unsigned int msr, u64 val, int failed) {}
  78 static inline void do_trace_read_msr(unsigned int msr, u64 val, int failed) {}
  79 static inline void do_trace_rdpmc(unsigned int msr, u64 val, int failed) {}
  80 #endif
  81
  82 /*
  83  * __rdmsr() and __wrmsr() are the two primitives which are the bare minimum MSR
  84  * accessors and should not have any tracing or other functionality piggybacking
  85  * on them - those are *purely* for accessing MSRs and nothing more. So don't even
  86  * think of extending them - you will be slapped with a stinking trout or a frozen
  87  * shark will reach you, wherever you are! You've been warned.
  88  */
  89 static inline unsigned long long notrace __rdmsr(unsigned int msr)
  90 {
  91         DECLARE_ARGS(val, low, high);
  92
  93         asm volatile("1: rdmsr\n"
  94                      "2:\n"
  95                      _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_rdmsr_unsafe)
  96                      : EAX_EDX_RET(val, low, high) : "c" (msr));
  97
  98         return EAX_EDX_VAL(val, low, high);
  99 }
 100
 101 static inline void notrace __wrmsr(unsigned int msr, u32 low, u32 high)
 102 {
 103         asm volatile("1: wrmsr\n"
 104                      "2:\n"
 105                      _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_unsafe)
 106                      : : "c" (msr), "a"(low), "d" (high) : "memory");
 107 }
 108
 109 #define native_rdmsr(msr, val1, val2)                   \
 110 do {                                                    \
 111         u64 __val = __rdmsr((msr));                     \
 112         (void)((val1) = (u32)__val);                    \
 113         (void)((val2) = (u32)(__val >> 32));            \
 114 } while (0)
 115
 116 #define native_wrmsr(msr, low, high)                    \
 117         __wrmsr(msr, low, high)
 118
 119 #define native_wrmsrl(msr, val)                         \
 120         __wrmsr((msr), (u32)((u64)(val)),               \
 121                        (u32)((u64)(val) >> 32))
 122
 123 static inline unsigned long long native_read_msr(unsigned int msr)
 124 {
 125         unsigned long long val;
 126
 127         val = __rdmsr(msr);
 128
 129         if (tracepoint_enabled(read_msr))
 130                 do_trace_read_msr(msr, val, 0);
 131
 132         return val;
 133 }
 134
 135 static inline unsigned long long native_read_msr_safe(unsigned int msr,
 136                                                       int *err)
 137 {
 138         DECLARE_ARGS(val, low, high);
 139
 140         asm volatile("2: rdmsr ; xor %[err],%[err]\n"
 141                      "1:\n\t"
 142                      ".section .fixup,\"ax\"\n\t"
 143                      "3: mov %[fault],%[err]\n\t"
 144                      "xorl %%eax, %%eax\n\t"
 145                      "xorl %%edx, %%edx\n\t"
 146                      "jmp 1b\n\t"
 147                      ".previous\n\t"
 148                      _ASM_EXTABLE(2b, 3b)
 149                      : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
 150                      : "c" (msr), [fault] "i" (-EIO));
 151         if (tracepoint_enabled(read_msr))
 152                 do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err);
 153         return EAX_EDX_VAL(val, low, high);
 154 }
 155
 156 /* Can be uninlined because referenced by paravirt */
 157 static inline void notrace
 158 native_write_msr(unsigned int msr, u32 low, u32 high)
 159 {
 160         __wrmsr(msr, low, high);
 161
 162         if (tracepoint_enabled(write_msr))
 163                 do_trace_write_msr(msr, ((u64)high << 32 | low), 0);
 164 }
 165
 166 /* Can be uninlined because referenced by paravirt */
 167 static inline int notrace
 168 native_write_msr_safe(unsigned int msr, u32 low, u32 high)
 169 {
 170         int err;
 171
 172         asm volatile("2: wrmsr ; xor %[err],%[err]\n"
 173                      "1:\n\t"
 174                      ".section .fixup,\"ax\"\n\t"
 175                      "3:  mov %[fault],%[err] ; jmp 1b\n\t"
 176                      ".previous\n\t"
 177                      _ASM_EXTABLE(2b, 3b)
 178                      : [err] "=a" (err)
 179                      : "c" (msr), "0" (low), "d" (high),
 180                        [fault] "i" (-EIO)
 181                      : "memory");
 182         if (tracepoint_enabled(write_msr))
 183                 do_trace_write_msr(msr, ((u64)high << 32 | low), err);
 184         return err;
 185 }
 186
 187 extern int rdmsr_safe_regs(u32 regs[8]);
 188 extern int wrmsr_safe_regs(u32 regs[8]);
 189
 190 /**
 191  * rdtsc() - returns the current TSC without ordering constraints
 192  *
 193  * rdtsc() returns the result of RDTSC as a 64-bit integer.  The
 194  * only ordering constraint it supplies is the ordering implied by
 195  * "asm volatile": it will put the RDTSC in the place you expect.  The
 196  * CPU can and will speculatively execute that RDTSC, though, so the
 197  * results can be non-monotonic if compared on different CPUs.
 198  */
 199 static __always_inline unsigned long long rdtsc(void)
 200 {
 201         DECLARE_ARGS(val, low, high);
 202
 203         asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
 204
 205         return EAX_EDX_VAL(val, low, high);
 206 }
 207
 208 /**
 209  * rdtsc_ordered() - read the current TSC in program order
 210  *
 211  * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer.
 212  * It is ordered like a load to a global in-memory counter.  It should
 213  * be impossible to observe non-monotonic rdtsc_unordered() behavior
 214  * across multiple CPUs as long as the TSC is synced.
 215  */
 216 static __always_inline unsigned long long rdtsc_ordered(void)
 217 {
 218         DECLARE_ARGS(val, low, high);
 219
 220         /*
 221          * The RDTSC instruction is not ordered relative to memory
 222          * access.  The Intel SDM and the AMD APM are both vague on this
 223          * point, but empirically an RDTSC instruction can be
 224          * speculatively executed before prior loads.  An RDTSC
 225          * immediately after an appropriate barrier appears to be
 226          * ordered as a normal load, that is, it provides the same
 227          * ordering guarantees as reading from a global memory location
 228          * that some other imaginary CPU is updating continuously with a
 229          * time stamp.
 230          *
 231          * Thus, use the preferred barrier on the respective CPU, aiming for
 232          * RDTSCP as the default.
 233          */
 234         asm volatile(ALTERNATIVE_2("rdtsc",
 235                                    "lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC,
 236                                    "rdtscp", X86_FEATURE_RDTSCP)
 237                         : EAX_EDX_RET(val, low, high)
 238                         /* RDTSCP clobbers ECX with MSR_TSC_AUX. */
 239                         :: "ecx");
 240
 241         return EAX_EDX_VAL(val, low, high);
 242 }
 243
 244 static inline unsigned long long native_read_pmc(int counter)
 245 {
 246         DECLARE_ARGS(val, low, high);
 247
 248         asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
 249         if (tracepoint_enabled(rdpmc))
 250                 do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0);
 251         return EAX_EDX_VAL(val, low, high);
 252 }
 253
 254 #ifdef CONFIG_PARAVIRT_XXL
 255 #include <asm/paravirt.h>
 256 #else
 257 #include <linux/errno.h>
 258 /*
 259  * Access to machine-specific registers (available on 586 and better only)
 260  * Note: the rd* operations modify the parameters directly (without using
 261  * pointer indirection), this allows gcc to optimize better
 262  */
 263
 264 #define rdmsr(msr, low, high)                                   \
 265 do {                                                            \
 266         u64 __val = native_read_msr((msr));                     \
 267         (void)((low) = (u32)__val);                             \
 268         (void)((high) = (u32)(__val >> 32));                    \
 269 } while (0)
 270
 271 static inline void wrmsr(unsigned int msr, u32 low, u32 high)
 272 {
 273         native_write_msr(msr, low, high);
 274 }
 275
 276 #define rdmsrl(msr, val)                        \
 277         ((val) = native_read_msr((msr)))
 278
 279 static inline void wrmsrl(unsigned int msr, u64 val)
 280 {
 281         native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32));
 282 }
 283
 284 /* wrmsr with exception handling */
 285 static inline int wrmsr_safe(unsigned int msr, u32 low, u32 high)
 286 {
 287         return native_write_msr_safe(msr, low, high);
 288 }
 289
 290 /* rdmsr with exception handling */
 291 #define rdmsr_safe(msr, low, high)                              \
 292 ({                                                              \
 293         int __err;                                              \
 294         u64 __val = native_read_msr_safe((msr), &__err);        \
 295         (*low) = (u32)__val;                                    \
 296         (*high) = (u32)(__val >> 32);                           \
 297         __err;                                                  \
 298 })
 299
 300 static inline int rdmsrl_safe(unsigned int msr, unsigned long long *p)
 301 {
 302         int err;
 303
 304         *p = native_read_msr_safe(msr, &err);
 305         return err;
 306 }
 307
 308 #define rdpmc(counter, low, high)                       \
 309 do {                                                    \
 310         u64 _l = native_read_pmc((counter));            \
 311         (low)  = (u32)_l;                               \
 312         (high) = (u32)(_l >> 32);                       \
 313 } while (0)
 314
 315 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
 316
 317 #endif  /* !CONFIG_PARAVIRT_XXL */
 318
 319 /*
 320  * 64-bit version of wrmsr_safe():
 321  */
 322 static inline int wrmsrl_safe(u32 msr, u64 val)
 323 {
 324         return wrmsr_safe(msr, (u32)val,  (u32)(val >> 32));
 325 }
 326
 327 #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high))
 328
 329 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
 330
 331 struct msr *msrs_alloc(void);
 332 void msrs_free(struct msr *msrs);
 333 int msr_set_bit(u32 msr, u8 bit);
 334 int msr_clear_bit(u32 msr, u8 bit);
 335
 336 #ifdef CONFIG_SMP
 337 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
 338 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 339 int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
 340 int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
 341 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
 342 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
 343 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
 344 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 345 int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
 346 int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
 347 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
 348 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
 349 #else  /*  CONFIG_SMP  */
 350 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
 351 {
 352         rdmsr(msr_no, *l, *h);
 353         return 0;
 354 }
 355 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 356 {
 357         wrmsr(msr_no, l, h);
 358         return 0;
 359 }
 360 static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
 361 {
 362         rdmsrl(msr_no, *q);
 363         return 0;
 364 }
 365 static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
 366 {
 367         wrmsrl(msr_no, q);
 368         return 0;
 369 }
 370 static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no,
 371                                 struct msr *msrs)
 372 {
 373         rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h));
 374 }
 375 static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no,
 376                                 struct msr *msrs)
 377 {
 378         wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h);
 379 }
 380 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
 381                                     u32 *l, u32 *h)
 382 {
 383         return rdmsr_safe(msr_no, l, h);
 384 }
 385 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 386 {
 387         return wrmsr_safe(msr_no, l, h);
 388 }
 389 static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
 390 {
 391         return rdmsrl_safe(msr_no, q);
 392 }
 393 static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
 394 {
 395         return wrmsrl_safe(msr_no, q);
 396 }
 397 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
 398 {
 399         return rdmsr_safe_regs(regs);
 400 }
 401 static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
 402 {
 403         return wrmsr_safe_regs(regs);
 404 }
 405 #endif  /* CONFIG_SMP */
 406 #endif /* __ASSEMBLY__ */
 407 #endif /* _ASM_X86_MSR_H */