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WIP FPC-III support
[linux/fpc-iii.git] / arch / x86 / kvm / svm / svm.c
blob7ef171790d02b669ffaa677cf0519972774ea384
1 #define pr_fmt(fmt) "SVM: " fmt
2
3 #include <linux/kvm_host.h>
4
5 #include "irq.h"
6 #include "mmu.h"
7 #include "kvm_cache_regs.h"
8 #include "x86.h"
9 #include "cpuid.h"
10 #include "pmu.h"
11
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/objtool.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
28
29 #include <asm/apic.h>
30 #include <asm/perf_event.h>
31 #include <asm/tlbflush.h>
32 #include <asm/desc.h>
33 #include <asm/debugreg.h>
34 #include <asm/kvm_para.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/spec-ctrl.h>
37 #include <asm/cpu_device_id.h>
38 #include <asm/traps.h>
39
40 #include <asm/virtext.h>
41 #include "trace.h"
42
43 #include "svm.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
49
50 #ifdef MODULE
51 static const struct x86_cpu_id svm_cpu_id[] = {
52 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
53 {}
54 };
55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
56 #endif
57
58 #define IOPM_ALLOC_ORDER 2
59 #define MSRPM_ALLOC_ORDER 1
60
61 #define SEG_TYPE_LDT 2
62 #define SEG_TYPE_BUSY_TSS16 3
63
64 #define SVM_FEATURE_LBRV (1 << 1)
65 #define SVM_FEATURE_SVML (1 << 2)
66 #define SVM_FEATURE_TSC_RATE (1 << 4)
67 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
69 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
70 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
71
72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
73
74 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
75 #define TSC_RATIO_MIN 0x0000000000000001ULL
76 #define TSC_RATIO_MAX 0x000000ffffffffffULL
77
78 static bool erratum_383_found __read_mostly;
79
80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
81
82 /*
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
85 */
86 static uint64_t osvw_len = 4, osvw_status;
87
88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
89 #define TSC_RATIO_DEFAULT 0x0100000000ULL
90
91 static const struct svm_direct_access_msrs {
92 u32 index; /* Index of the MSR */
93 bool always; /* True if intercept is initially cleared */
94 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
95 { .index = MSR_STAR, .always = true },
96 { .index = MSR_IA32_SYSENTER_CS, .always = true },
97 #ifdef CONFIG_X86_64
98 { .index = MSR_GS_BASE, .always = true },
99 { .index = MSR_FS_BASE, .always = true },
100 { .index = MSR_KERNEL_GS_BASE, .always = true },
101 { .index = MSR_LSTAR, .always = true },
102 { .index = MSR_CSTAR, .always = true },
103 { .index = MSR_SYSCALL_MASK, .always = true },
104 #endif
105 { .index = MSR_IA32_SPEC_CTRL, .always = false },
106 { .index = MSR_IA32_PRED_CMD, .always = false },
107 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
108 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
109 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
110 { .index = MSR_IA32_LASTINTTOIP, .always = false },
111 { .index = MSR_EFER, .always = false },
112 { .index = MSR_IA32_CR_PAT, .always = false },
113 { .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
114 { .index = MSR_INVALID, .always = false },
115 };
116
117 /* enable NPT for AMD64 and X86 with PAE */
118 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
119 bool npt_enabled = true;
120 #else
121 bool npt_enabled;
122 #endif
123
124 /*
125 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
126 * pause_filter_count: On processors that support Pause filtering(indicated
127 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
128 * count value. On VMRUN this value is loaded into an internal counter.
129 * Each time a pause instruction is executed, this counter is decremented
130 * until it reaches zero at which time a #VMEXIT is generated if pause
131 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
132 * Intercept Filtering for more details.
133 * This also indicate if ple logic enabled.
134 *
135 * pause_filter_thresh: In addition, some processor families support advanced
136 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
137 * the amount of time a guest is allowed to execute in a pause loop.
138 * In this mode, a 16-bit pause filter threshold field is added in the
139 * VMCB. The threshold value is a cycle count that is used to reset the
140 * pause counter. As with simple pause filtering, VMRUN loads the pause
141 * count value from VMCB into an internal counter. Then, on each pause
142 * instruction the hardware checks the elapsed number of cycles since
143 * the most recent pause instruction against the pause filter threshold.
144 * If the elapsed cycle count is greater than the pause filter threshold,
145 * then the internal pause count is reloaded from the VMCB and execution
146 * continues. If the elapsed cycle count is less than the pause filter
147 * threshold, then the internal pause count is decremented. If the count
148 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
149 * triggered. If advanced pause filtering is supported and pause filter
150 * threshold field is set to zero, the filter will operate in the simpler,
151 * count only mode.
152 */
153
154 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
155 module_param(pause_filter_thresh, ushort, 0444);
156
157 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
158 module_param(pause_filter_count, ushort, 0444);
159
160 /* Default doubles per-vcpu window every exit. */
161 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
162 module_param(pause_filter_count_grow, ushort, 0444);
163
164 /* Default resets per-vcpu window every exit to pause_filter_count. */
165 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
166 module_param(pause_filter_count_shrink, ushort, 0444);
167
168 /* Default is to compute the maximum so we can never overflow. */
169 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
170 module_param(pause_filter_count_max, ushort, 0444);
171
172 /* allow nested paging (virtualized MMU) for all guests */
173 static int npt = true;
174 module_param(npt, int, S_IRUGO);
175
176 /* allow nested virtualization in KVM/SVM */
177 static int nested = true;
178 module_param(nested, int, S_IRUGO);
179
180 /* enable/disable Next RIP Save */
181 static int nrips = true;
182 module_param(nrips, int, 0444);
183
184 /* enable/disable Virtual VMLOAD VMSAVE */
185 static int vls = true;
186 module_param(vls, int, 0444);
187
188 /* enable/disable Virtual GIF */
189 static int vgif = true;
190 module_param(vgif, int, 0444);
191
192 /* enable/disable SEV support */
193 int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
194 module_param(sev, int, 0444);
195
196 /* enable/disable SEV-ES support */
197 int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
198 module_param(sev_es, int, 0444);
199
200 bool __read_mostly dump_invalid_vmcb;
201 module_param(dump_invalid_vmcb, bool, 0644);
202
203 static u8 rsm_ins_bytes[] = "\x0f\xaa";
204
205 static void svm_complete_interrupts(struct vcpu_svm *svm);
206
207 static unsigned long iopm_base;
208
209 struct kvm_ldttss_desc {
210 u16 limit0;
211 u16 base0;
212 unsigned base1:8, type:5, dpl:2, p:1;
213 unsigned limit1:4, zero0:3, g:1, base2:8;
214 u32 base3;
215 u32 zero1;
216 } __attribute__((packed));
217
218 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
219
220 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
221
222 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
223 #define MSRS_RANGE_SIZE 2048
224 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
225
226 u32 svm_msrpm_offset(u32 msr)
227 {
228 u32 offset;
229 int i;
230
231 for (i = 0; i < NUM_MSR_MAPS; i++) {
232 if (msr < msrpm_ranges[i] ||
233 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
234 continue;
235
236 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
237 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
238
239 /* Now we have the u8 offset - but need the u32 offset */
240 return offset / 4;
241 }
242
243 /* MSR not in any range */
244 return MSR_INVALID;
245 }
246
247 #define MAX_INST_SIZE 15
248
249 static inline void clgi(void)
250 {
251 asm volatile (__ex("clgi"));
252 }
253
254 static inline void stgi(void)
255 {
256 asm volatile (__ex("stgi"));
257 }
258
259 static inline void invlpga(unsigned long addr, u32 asid)
260 {
261 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
262 }
263
264 static int get_max_npt_level(void)
265 {
266 #ifdef CONFIG_X86_64
267 return PT64_ROOT_4LEVEL;
268 #else
269 return PT32E_ROOT_LEVEL;
270 #endif
271 }
272
273 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
274 {
275 struct vcpu_svm *svm = to_svm(vcpu);
276 u64 old_efer = vcpu->arch.efer;
277 vcpu->arch.efer = efer;
278
279 if (!npt_enabled) {
280 /* Shadow paging assumes NX to be available. */
281 efer |= EFER_NX;
282
283 if (!(efer & EFER_LMA))
284 efer &= ~EFER_LME;
285 }
286
287 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
288 if (!(efer & EFER_SVME)) {
289 svm_leave_nested(svm);
290 svm_set_gif(svm, true);
291
292 /*
293 * Free the nested guest state, unless we are in SMM.
294 * In this case we will return to the nested guest
295 * as soon as we leave SMM.
296 */
297 if (!is_smm(&svm->vcpu))
298 svm_free_nested(svm);
299
300 } else {
301 int ret = svm_allocate_nested(svm);
302
303 if (ret) {
304 vcpu->arch.efer = old_efer;
305 return ret;
306 }
307 }
308 }
309
310 svm->vmcb->save.efer = efer | EFER_SVME;
311 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
312 return 0;
313 }
314
315 static int is_external_interrupt(u32 info)
316 {
317 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
318 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
319 }
320
321 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
322 {
323 struct vcpu_svm *svm = to_svm(vcpu);
324 u32 ret = 0;
325
326 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
327 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
328 return ret;
329 }
330
331 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
332 {
333 struct vcpu_svm *svm = to_svm(vcpu);
334
335 if (mask == 0)
336 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
337 else
338 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
339
340 }
341
342 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
343 {
344 struct vcpu_svm *svm = to_svm(vcpu);
345
346 /*
347 * SEV-ES does not expose the next RIP. The RIP update is controlled by
348 * the type of exit and the #VC handler in the guest.
349 */
350 if (sev_es_guest(vcpu->kvm))
351 goto done;
352
353 if (nrips && svm->vmcb->control.next_rip != 0) {
354 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
355 svm->next_rip = svm->vmcb->control.next_rip;
356 }
357
358 if (!svm->next_rip) {
359 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
360 return 0;
361 } else {
362 kvm_rip_write(vcpu, svm->next_rip);
363 }
364
365 done:
366 svm_set_interrupt_shadow(vcpu, 0);
367
368 return 1;
369 }
370
371 static void svm_queue_exception(struct kvm_vcpu *vcpu)
372 {
373 struct vcpu_svm *svm = to_svm(vcpu);
374 unsigned nr = vcpu->arch.exception.nr;
375 bool has_error_code = vcpu->arch.exception.has_error_code;
376 u32 error_code = vcpu->arch.exception.error_code;
377
378 kvm_deliver_exception_payload(&svm->vcpu);
379
380 if (nr == BP_VECTOR && !nrips) {
381 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
382
383 /*
384 * For guest debugging where we have to reinject #BP if some
385 * INT3 is guest-owned:
386 * Emulate nRIP by moving RIP forward. Will fail if injection
387 * raises a fault that is not intercepted. Still better than
388 * failing in all cases.
389 */
390 (void)skip_emulated_instruction(&svm->vcpu);
391 rip = kvm_rip_read(&svm->vcpu);
392 svm->int3_rip = rip + svm->vmcb->save.cs.base;
393 svm->int3_injected = rip - old_rip;
394 }
395
396 svm->vmcb->control.event_inj = nr
397 | SVM_EVTINJ_VALID
398 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
399 | SVM_EVTINJ_TYPE_EXEPT;
400 svm->vmcb->control.event_inj_err = error_code;
401 }
402
403 static void svm_init_erratum_383(void)
404 {
405 u32 low, high;
406 int err;
407 u64 val;
408
409 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
410 return;
411
412 /* Use _safe variants to not break nested virtualization */
413 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
414 if (err)
415 return;
416
417 val |= (1ULL << 47);
418
419 low = lower_32_bits(val);
420 high = upper_32_bits(val);
421
422 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
423
424 erratum_383_found = true;
425 }
426
427 static void svm_init_osvw(struct kvm_vcpu *vcpu)
428 {
429 /*
430 * Guests should see errata 400 and 415 as fixed (assuming that
431 * HLT and IO instructions are intercepted).
432 */
433 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
434 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
435
436 /*
437 * By increasing VCPU's osvw.length to 3 we are telling the guest that
438 * all osvw.status bits inside that length, including bit 0 (which is
439 * reserved for erratum 298), are valid. However, if host processor's
440 * osvw_len is 0 then osvw_status[0] carries no information. We need to
441 * be conservative here and therefore we tell the guest that erratum 298
442 * is present (because we really don't know).
443 */
444 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
445 vcpu->arch.osvw.status |= 1;
446 }
447
448 static int has_svm(void)
449 {
450 const char *msg;
451
452 if (!cpu_has_svm(&msg)) {
453 printk(KERN_INFO "has_svm: %s\n", msg);
454 return 0;
455 }
456
457 return 1;
458 }
459
460 static void svm_hardware_disable(void)
461 {
462 /* Make sure we clean up behind us */
463 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
464 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
465
466 cpu_svm_disable();
467
468 amd_pmu_disable_virt();
469 }
470
471 static int svm_hardware_enable(void)
472 {
473
474 struct svm_cpu_data *sd;
475 uint64_t efer;
476 struct desc_struct *gdt;
477 int me = raw_smp_processor_id();
478
479 rdmsrl(MSR_EFER, efer);
480 if (efer & EFER_SVME)
481 return -EBUSY;
482
483 if (!has_svm()) {
484 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
485 return -EINVAL;
486 }
487 sd = per_cpu(svm_data, me);
488 if (!sd) {
489 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
490 return -EINVAL;
491 }
492
493 sd->asid_generation = 1;
494 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
495 sd->next_asid = sd->max_asid + 1;
496 sd->min_asid = max_sev_asid + 1;
497
498 gdt = get_current_gdt_rw();
499 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
500
501 wrmsrl(MSR_EFER, efer | EFER_SVME);
502
503 wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
504
505 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
506 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
507 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
508 }
509
510
511 /*
512 * Get OSVW bits.
513 *
514 * Note that it is possible to have a system with mixed processor
515 * revisions and therefore different OSVW bits. If bits are not the same
516 * on different processors then choose the worst case (i.e. if erratum
517 * is present on one processor and not on another then assume that the
518 * erratum is present everywhere).
519 */
520 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
521 uint64_t len, status = 0;
522 int err;
523
524 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
525 if (!err)
526 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
527 &err);
528
529 if (err)
530 osvw_status = osvw_len = 0;
531 else {
532 if (len < osvw_len)
533 osvw_len = len;
534 osvw_status |= status;
535 osvw_status &= (1ULL << osvw_len) - 1;
536 }
537 } else
538 osvw_status = osvw_len = 0;
539
540 svm_init_erratum_383();
541
542 amd_pmu_enable_virt();
543
544 return 0;
545 }
546
547 static void svm_cpu_uninit(int cpu)
548 {
549 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
550
551 if (!sd)
552 return;
553
554 per_cpu(svm_data, cpu) = NULL;
555 kfree(sd->sev_vmcbs);
556 __free_page(sd->save_area);
557 kfree(sd);
558 }
559
560 static int svm_cpu_init(int cpu)
561 {
562 struct svm_cpu_data *sd;
563
564 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
565 if (!sd)
566 return -ENOMEM;
567 sd->cpu = cpu;
568 sd->save_area = alloc_page(GFP_KERNEL);
569 if (!sd->save_area)
570 goto free_cpu_data;
571 clear_page(page_address(sd->save_area));
572
573 if (svm_sev_enabled()) {
574 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
575 sizeof(void *),
576 GFP_KERNEL);
577 if (!sd->sev_vmcbs)
578 goto free_save_area;
579 }
580
581 per_cpu(svm_data, cpu) = sd;
582
583 return 0;
584
585 free_save_area:
586 __free_page(sd->save_area);
587 free_cpu_data:
588 kfree(sd);
589 return -ENOMEM;
590
591 }
592
593 static int direct_access_msr_slot(u32 msr)
594 {
595 u32 i;
596
597 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
598 if (direct_access_msrs[i].index == msr)
599 return i;
600
601 return -ENOENT;
602 }
603
604 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
605 int write)
606 {
607 struct vcpu_svm *svm = to_svm(vcpu);
608 int slot = direct_access_msr_slot(msr);
609
610 if (slot == -ENOENT)
611 return;
612
613 /* Set the shadow bitmaps to the desired intercept states */
614 if (read)
615 set_bit(slot, svm->shadow_msr_intercept.read);
616 else
617 clear_bit(slot, svm->shadow_msr_intercept.read);
618
619 if (write)
620 set_bit(slot, svm->shadow_msr_intercept.write);
621 else
622 clear_bit(slot, svm->shadow_msr_intercept.write);
623 }
624
625 static bool valid_msr_intercept(u32 index)
626 {
627 return direct_access_msr_slot(index) != -ENOENT;
628 }
629
630 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
631 {
632 u8 bit_write;
633 unsigned long tmp;
634 u32 offset;
635 u32 *msrpm;
636
637 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
638 to_svm(vcpu)->msrpm;
639
640 offset = svm_msrpm_offset(msr);
641 bit_write = 2 * (msr & 0x0f) + 1;
642 tmp = msrpm[offset];
643
644 BUG_ON(offset == MSR_INVALID);
645
646 return !!test_bit(bit_write, &tmp);
647 }
648
649 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
650 u32 msr, int read, int write)
651 {
652 u8 bit_read, bit_write;
653 unsigned long tmp;
654 u32 offset;
655
656 /*
657 * If this warning triggers extend the direct_access_msrs list at the
658 * beginning of the file
659 */
660 WARN_ON(!valid_msr_intercept(msr));
661
662 /* Enforce non allowed MSRs to trap */
663 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
664 read = 0;
665
666 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
667 write = 0;
668
669 offset = svm_msrpm_offset(msr);
670 bit_read = 2 * (msr & 0x0f);
671 bit_write = 2 * (msr & 0x0f) + 1;
672 tmp = msrpm[offset];
673
674 BUG_ON(offset == MSR_INVALID);
675
676 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
677 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
678
679 msrpm[offset] = tmp;
680 }
681
682 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
683 int read, int write)
684 {
685 set_shadow_msr_intercept(vcpu, msr, read, write);
686 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
687 }
688
689 u32 *svm_vcpu_alloc_msrpm(void)
690 {
691 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
692 u32 *msrpm;
693
694 if (!pages)
695 return NULL;
696
697 msrpm = page_address(pages);
698 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
699
700 return msrpm;
701 }
702
703 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
704 {
705 int i;
706
707 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
708 if (!direct_access_msrs[i].always)
709 continue;
710 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
711 }
712 }
713
714
715 void svm_vcpu_free_msrpm(u32 *msrpm)
716 {
717 __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
718 }
719
720 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
721 {
722 struct vcpu_svm *svm = to_svm(vcpu);
723 u32 i;
724
725 /*
726 * Set intercept permissions for all direct access MSRs again. They
727 * will automatically get filtered through the MSR filter, so we are
728 * back in sync after this.
729 */
730 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
731 u32 msr = direct_access_msrs[i].index;
732 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
733 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
734
735 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
736 }
737 }
738
739 static void add_msr_offset(u32 offset)
740 {
741 int i;
742
743 for (i = 0; i < MSRPM_OFFSETS; ++i) {
744
745 /* Offset already in list? */
746 if (msrpm_offsets[i] == offset)
747 return;
748
749 /* Slot used by another offset? */
750 if (msrpm_offsets[i] != MSR_INVALID)
751 continue;
752
753 /* Add offset to list */
754 msrpm_offsets[i] = offset;
755
756 return;
757 }
758
759 /*
760 * If this BUG triggers the msrpm_offsets table has an overflow. Just
761 * increase MSRPM_OFFSETS in this case.
762 */
763 BUG();
764 }
765
766 static void init_msrpm_offsets(void)
767 {
768 int i;
769
770 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
771
772 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
773 u32 offset;
774
775 offset = svm_msrpm_offset(direct_access_msrs[i].index);
776 BUG_ON(offset == MSR_INVALID);
777
778 add_msr_offset(offset);
779 }
780 }
781
782 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
783 {
784 struct vcpu_svm *svm = to_svm(vcpu);
785
786 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
787 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
788 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
789 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
790 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
791 }
792
793 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
794 {
795 struct vcpu_svm *svm = to_svm(vcpu);
796
797 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
798 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
799 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
800 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
801 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
802 }
803
804 void disable_nmi_singlestep(struct vcpu_svm *svm)
805 {
806 svm->nmi_singlestep = false;
807
808 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
809 /* Clear our flags if they were not set by the guest */
810 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
811 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
812 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
813 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
814 }
815 }
816
817 static void grow_ple_window(struct kvm_vcpu *vcpu)
818 {
819 struct vcpu_svm *svm = to_svm(vcpu);
820 struct vmcb_control_area *control = &svm->vmcb->control;
821 int old = control->pause_filter_count;
822
823 control->pause_filter_count = __grow_ple_window(old,
824 pause_filter_count,
825 pause_filter_count_grow,
826 pause_filter_count_max);
827
828 if (control->pause_filter_count != old) {
829 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
830 trace_kvm_ple_window_update(vcpu->vcpu_id,
831 control->pause_filter_count, old);
832 }
833 }
834
835 static void shrink_ple_window(struct kvm_vcpu *vcpu)
836 {
837 struct vcpu_svm *svm = to_svm(vcpu);
838 struct vmcb_control_area *control = &svm->vmcb->control;
839 int old = control->pause_filter_count;
840
841 control->pause_filter_count =
842 __shrink_ple_window(old,
843 pause_filter_count,
844 pause_filter_count_shrink,
845 pause_filter_count);
846 if (control->pause_filter_count != old) {
847 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
848 trace_kvm_ple_window_update(vcpu->vcpu_id,
849 control->pause_filter_count, old);
850 }
851 }
852
853 /*
854 * The default MMIO mask is a single bit (excluding the present bit),
855 * which could conflict with the memory encryption bit. Check for
856 * memory encryption support and override the default MMIO mask if
857 * memory encryption is enabled.
858 */
859 static __init void svm_adjust_mmio_mask(void)
860 {
861 unsigned int enc_bit, mask_bit;
862 u64 msr, mask;
863
864 /* If there is no memory encryption support, use existing mask */
865 if (cpuid_eax(0x80000000) < 0x8000001f)
866 return;
867
868 /* If memory encryption is not enabled, use existing mask */
869 rdmsrl(MSR_K8_SYSCFG, msr);
870 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
871 return;
872
873 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
874 mask_bit = boot_cpu_data.x86_phys_bits;
875
876 /* Increment the mask bit if it is the same as the encryption bit */
877 if (enc_bit == mask_bit)
878 mask_bit++;
879
880 /*
881 * If the mask bit location is below 52, then some bits above the
882 * physical addressing limit will always be reserved, so use the
883 * rsvd_bits() function to generate the mask. This mask, along with
884 * the present bit, will be used to generate a page fault with
885 * PFER.RSV = 1.
886 *
887 * If the mask bit location is 52 (or above), then clear the mask.
888 */
889 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
890
891 kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
892 }
893
894 static void svm_hardware_teardown(void)
895 {
896 int cpu;
897
898 if (svm_sev_enabled())
899 sev_hardware_teardown();
900
901 for_each_possible_cpu(cpu)
902 svm_cpu_uninit(cpu);
903
904 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
905 iopm_base = 0;
906 }
907
908 static __init void svm_set_cpu_caps(void)
909 {
910 kvm_set_cpu_caps();
911
912 supported_xss = 0;
913
914 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
915 if (nested) {
916 kvm_cpu_cap_set(X86_FEATURE_SVM);
917
918 if (nrips)
919 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
920
921 if (npt_enabled)
922 kvm_cpu_cap_set(X86_FEATURE_NPT);
923 }
924
925 /* CPUID 0x80000008 */
926 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
927 boot_cpu_has(X86_FEATURE_AMD_SSBD))
928 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
929
930 /* Enable INVPCID feature */
931 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
932 }
933
934 static __init int svm_hardware_setup(void)
935 {
936 int cpu;
937 struct page *iopm_pages;
938 void *iopm_va;
939 int r;
940
941 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
942
943 if (!iopm_pages)
944 return -ENOMEM;
945
946 iopm_va = page_address(iopm_pages);
947 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
948 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
949
950 init_msrpm_offsets();
951
952 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
953
954 if (boot_cpu_has(X86_FEATURE_NX))
955 kvm_enable_efer_bits(EFER_NX);
956
957 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
958 kvm_enable_efer_bits(EFER_FFXSR);
959
960 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
961 kvm_has_tsc_control = true;
962 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
963 kvm_tsc_scaling_ratio_frac_bits = 32;
964 }
965
966 /* Check for pause filtering support */
967 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
968 pause_filter_count = 0;
969 pause_filter_thresh = 0;
970 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
971 pause_filter_thresh = 0;
972 }
973
974 if (nested) {
975 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
976 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
977 }
978
979 if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
980 sev_hardware_setup();
981 } else {
982 sev = false;
983 sev_es = false;
984 }
985
986 svm_adjust_mmio_mask();
987
988 for_each_possible_cpu(cpu) {
989 r = svm_cpu_init(cpu);
990 if (r)
991 goto err;
992 }
993
994 if (!boot_cpu_has(X86_FEATURE_NPT))
995 npt_enabled = false;
996
997 if (npt_enabled && !npt)
998 npt_enabled = false;
999
1000 kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
1001 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
1002
1003 if (nrips) {
1004 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1005 nrips = false;
1006 }
1007
1008 if (avic) {
1009 if (!npt_enabled ||
1010 !boot_cpu_has(X86_FEATURE_AVIC) ||
1011 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1012 avic = false;
1013 } else {
1014 pr_info("AVIC enabled\n");
1015
1016 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1017 }
1018 }
1019
1020 if (vls) {
1021 if (!npt_enabled ||
1022 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1023 !IS_ENABLED(CONFIG_X86_64)) {
1024 vls = false;
1025 } else {
1026 pr_info("Virtual VMLOAD VMSAVE supported\n");
1027 }
1028 }
1029
1030 if (vgif) {
1031 if (!boot_cpu_has(X86_FEATURE_VGIF))
1032 vgif = false;
1033 else
1034 pr_info("Virtual GIF supported\n");
1035 }
1036
1037 svm_set_cpu_caps();
1038
1039 /*
1040 * It seems that on AMD processors PTE's accessed bit is
1041 * being set by the CPU hardware before the NPF vmexit.
1042 * This is not expected behaviour and our tests fail because
1043 * of it.
1044 * A workaround here is to disable support for
1045 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1046 * In this case userspace can know if there is support using
1047 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1048 * it
1049 * If future AMD CPU models change the behaviour described above,
1050 * this variable can be changed accordingly
1051 */
1052 allow_smaller_maxphyaddr = !npt_enabled;
1053
1054 return 0;
1055
1056 err:
1057 svm_hardware_teardown();
1058 return r;
1059 }
1060
1061 static void init_seg(struct vmcb_seg *seg)
1062 {
1063 seg->selector = 0;
1064 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1065 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1066 seg->limit = 0xffff;
1067 seg->base = 0;
1068 }
1069
1070 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1071 {
1072 seg->selector = 0;
1073 seg->attrib = SVM_SELECTOR_P_MASK | type;
1074 seg->limit = 0xffff;
1075 seg->base = 0;
1076 }
1077
1078 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1079 {
1080 struct vcpu_svm *svm = to_svm(vcpu);
1081 u64 g_tsc_offset = 0;
1082
1083 if (is_guest_mode(vcpu)) {
1084 /* Write L1's TSC offset. */
1085 g_tsc_offset = svm->vmcb->control.tsc_offset -
1086 svm->nested.hsave->control.tsc_offset;
1087 svm->nested.hsave->control.tsc_offset = offset;
1088 }
1089
1090 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1091 svm->vmcb->control.tsc_offset - g_tsc_offset,
1092 offset);
1093
1094 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1095
1096 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1097 return svm->vmcb->control.tsc_offset;
1098 }
1099
1100 static void svm_check_invpcid(struct vcpu_svm *svm)
1101 {
1102 /*
1103 * Intercept INVPCID instruction only if shadow page table is
1104 * enabled. Interception is not required with nested page table
1105 * enabled.
1106 */
1107 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1108 if (!npt_enabled)
1109 svm_set_intercept(svm, INTERCEPT_INVPCID);
1110 else
1111 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1112 }
1113 }
1114
1115 static void init_vmcb(struct vcpu_svm *svm)
1116 {
1117 struct vmcb_control_area *control = &svm->vmcb->control;
1118 struct vmcb_save_area *save = &svm->vmcb->save;
1119
1120 svm->vcpu.arch.hflags = 0;
1121
1122 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1123 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1124 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1125 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1126 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1127 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1128 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1129 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1130
1131 set_dr_intercepts(svm);
1132
1133 set_exception_intercept(svm, PF_VECTOR);
1134 set_exception_intercept(svm, UD_VECTOR);
1135 set_exception_intercept(svm, MC_VECTOR);
1136 set_exception_intercept(svm, AC_VECTOR);
1137 set_exception_intercept(svm, DB_VECTOR);
1138 /*
1139 * Guest access to VMware backdoor ports could legitimately
1140 * trigger #GP because of TSS I/O permission bitmap.
1141 * We intercept those #GP and allow access to them anyway
1142 * as VMware does.
1143 */
1144 if (enable_vmware_backdoor)
1145 set_exception_intercept(svm, GP_VECTOR);
1146
1147 svm_set_intercept(svm, INTERCEPT_INTR);
1148 svm_set_intercept(svm, INTERCEPT_NMI);
1149 svm_set_intercept(svm, INTERCEPT_SMI);
1150 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1151 svm_set_intercept(svm, INTERCEPT_RDPMC);
1152 svm_set_intercept(svm, INTERCEPT_CPUID);
1153 svm_set_intercept(svm, INTERCEPT_INVD);
1154 svm_set_intercept(svm, INTERCEPT_INVLPG);
1155 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1156 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1157 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1158 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1159 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1160 svm_set_intercept(svm, INTERCEPT_VMRUN);
1161 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1162 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1163 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1164 svm_set_intercept(svm, INTERCEPT_STGI);
1165 svm_set_intercept(svm, INTERCEPT_CLGI);
1166 svm_set_intercept(svm, INTERCEPT_SKINIT);
1167 svm_set_intercept(svm, INTERCEPT_WBINVD);
1168 svm_set_intercept(svm, INTERCEPT_XSETBV);
1169 svm_set_intercept(svm, INTERCEPT_RDPRU);
1170 svm_set_intercept(svm, INTERCEPT_RSM);
1171
1172 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1173 svm_set_intercept(svm, INTERCEPT_MONITOR);
1174 svm_set_intercept(svm, INTERCEPT_MWAIT);
1175 }
1176
1177 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1178 svm_set_intercept(svm, INTERCEPT_HLT);
1179
1180 control->iopm_base_pa = __sme_set(iopm_base);
1181 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1182 control->int_ctl = V_INTR_MASKING_MASK;
1183
1184 init_seg(&save->es);
1185 init_seg(&save->ss);
1186 init_seg(&save->ds);
1187 init_seg(&save->fs);
1188 init_seg(&save->gs);
1189
1190 save->cs.selector = 0xf000;
1191 save->cs.base = 0xffff0000;
1192 /* Executable/Readable Code Segment */
1193 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1194 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1195 save->cs.limit = 0xffff;
1196
1197 save->gdtr.limit = 0xffff;
1198 save->idtr.limit = 0xffff;
1199
1200 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1201 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1202
1203 svm_set_efer(&svm->vcpu, 0);
1204 save->dr6 = 0xffff0ff0;
1205 kvm_set_rflags(&svm->vcpu, 2);
1206 save->rip = 0x0000fff0;
1207 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1208
1209 /*
1210 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1211 * It also updates the guest-visible cr0 value.
1212 */
1213 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1214 kvm_mmu_reset_context(&svm->vcpu);
1215
1216 save->cr4 = X86_CR4_PAE;
1217 /* rdx = ?? */
1218
1219 if (npt_enabled) {
1220 /* Setup VMCB for Nested Paging */
1221 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1222 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1223 clr_exception_intercept(svm, PF_VECTOR);
1224 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1225 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1226 save->g_pat = svm->vcpu.arch.pat;
1227 save->cr3 = 0;
1228 save->cr4 = 0;
1229 }
1230 svm->asid_generation = 0;
1231 svm->asid = 0;
1232
1233 svm->nested.vmcb12_gpa = 0;
1234 svm->vcpu.arch.hflags = 0;
1235
1236 if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1237 control->pause_filter_count = pause_filter_count;
1238 if (pause_filter_thresh)
1239 control->pause_filter_thresh = pause_filter_thresh;
1240 svm_set_intercept(svm, INTERCEPT_PAUSE);
1241 } else {
1242 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1243 }
1244
1245 svm_check_invpcid(svm);
1246
1247 if (kvm_vcpu_apicv_active(&svm->vcpu))
1248 avic_init_vmcb(svm);
1249
1250 /*
1251 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1252 * in VMCB and clear intercepts to avoid #VMEXIT.
1253 */
1254 if (vls) {
1255 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1256 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1257 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1258 }
1259
1260 if (vgif) {
1261 svm_clr_intercept(svm, INTERCEPT_STGI);
1262 svm_clr_intercept(svm, INTERCEPT_CLGI);
1263 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1264 }
1265
1266 if (sev_guest(svm->vcpu.kvm)) {
1267 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1268 clr_exception_intercept(svm, UD_VECTOR);
1269
1270 if (sev_es_guest(svm->vcpu.kvm)) {
1271 /* Perform SEV-ES specific VMCB updates */
1272 sev_es_init_vmcb(svm);
1273 }
1274 }
1275
1276 vmcb_mark_all_dirty(svm->vmcb);
1277
1278 enable_gif(svm);
1279
1280 }
1281
1282 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1283 {
1284 struct vcpu_svm *svm = to_svm(vcpu);
1285 u32 dummy;
1286 u32 eax = 1;
1287
1288 svm->spec_ctrl = 0;
1289 svm->virt_spec_ctrl = 0;
1290
1291 if (!init_event) {
1292 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1293 MSR_IA32_APICBASE_ENABLE;
1294 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1295 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1296 }
1297 init_vmcb(svm);
1298
1299 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1300 kvm_rdx_write(vcpu, eax);
1301
1302 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1303 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1304 }
1305
1306 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1307 {
1308 struct vcpu_svm *svm;
1309 struct page *vmcb_page;
1310 struct page *vmsa_page = NULL;
1311 int err;
1312
1313 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1314 svm = to_svm(vcpu);
1315
1316 err = -ENOMEM;
1317 vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1318 if (!vmcb_page)
1319 goto out;
1320
1321 if (sev_es_guest(svm->vcpu.kvm)) {
1322 /*
1323 * SEV-ES guests require a separate VMSA page used to contain
1324 * the encrypted register state of the guest.
1325 */
1326 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1327 if (!vmsa_page)
1328 goto error_free_vmcb_page;
1329
1330 /*
1331 * SEV-ES guests maintain an encrypted version of their FPU
1332 * state which is restored and saved on VMRUN and VMEXIT.
1333 * Free the fpu structure to prevent KVM from attempting to
1334 * access the FPU state.
1335 */
1336 kvm_free_guest_fpu(vcpu);
1337 }
1338
1339 err = avic_init_vcpu(svm);
1340 if (err)
1341 goto error_free_vmsa_page;
1342
1343 /* We initialize this flag to true to make sure that the is_running
1344 * bit would be set the first time the vcpu is loaded.
1345 */
1346 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1347 svm->avic_is_running = true;
1348
1349 svm->msrpm = svm_vcpu_alloc_msrpm();
1350 if (!svm->msrpm) {
1351 err = -ENOMEM;
1352 goto error_free_vmsa_page;
1353 }
1354
1355 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1356
1357 svm->vmcb = page_address(vmcb_page);
1358 svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
1359
1360 if (vmsa_page)
1361 svm->vmsa = page_address(vmsa_page);
1362
1363 svm->asid_generation = 0;
1364 init_vmcb(svm);
1365
1366 svm_init_osvw(vcpu);
1367 vcpu->arch.microcode_version = 0x01000065;
1368
1369 if (sev_es_guest(svm->vcpu.kvm))
1370 /* Perform SEV-ES specific VMCB creation updates */
1371 sev_es_create_vcpu(svm);
1372
1373 return 0;
1374
1375 error_free_vmsa_page:
1376 if (vmsa_page)
1377 __free_page(vmsa_page);
1378 error_free_vmcb_page:
1379 __free_page(vmcb_page);
1380 out:
1381 return err;
1382 }
1383
1384 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1385 {
1386 int i;
1387
1388 for_each_online_cpu(i)
1389 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1390 }
1391
1392 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1393 {
1394 struct vcpu_svm *svm = to_svm(vcpu);
1395
1396 /*
1397 * The vmcb page can be recycled, causing a false negative in
1398 * svm_vcpu_load(). So, ensure that no logical CPU has this
1399 * vmcb page recorded as its current vmcb.
1400 */
1401 svm_clear_current_vmcb(svm->vmcb);
1402
1403 svm_free_nested(svm);
1404
1405 sev_free_vcpu(vcpu);
1406
1407 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1408 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1409 }
1410
1411 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1412 {
1413 struct vcpu_svm *svm = to_svm(vcpu);
1414 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1415 int i;
1416
1417 if (unlikely(cpu != vcpu->cpu)) {
1418 svm->asid_generation = 0;
1419 vmcb_mark_all_dirty(svm->vmcb);
1420 }
1421
1422 if (sev_es_guest(svm->vcpu.kvm)) {
1423 sev_es_vcpu_load(svm, cpu);
1424 } else {
1425 #ifdef CONFIG_X86_64
1426 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1427 #endif
1428 savesegment(fs, svm->host.fs);
1429 savesegment(gs, svm->host.gs);
1430 svm->host.ldt = kvm_read_ldt();
1431
1432 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1433 rdmsrl(host_save_user_msrs[i].index,
1434 svm->host_user_msrs[i]);
1435 }
1436
1437 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1438 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1439 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1440 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1441 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1442 }
1443 }
1444 /* This assumes that the kernel never uses MSR_TSC_AUX */
1445 if (static_cpu_has(X86_FEATURE_RDTSCP))
1446 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1447
1448 if (sd->current_vmcb != svm->vmcb) {
1449 sd->current_vmcb = svm->vmcb;
1450 indirect_branch_prediction_barrier();
1451 }
1452 avic_vcpu_load(vcpu, cpu);
1453 }
1454
1455 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1456 {
1457 struct vcpu_svm *svm = to_svm(vcpu);
1458 int i;
1459
1460 avic_vcpu_put(vcpu);
1461
1462 ++vcpu->stat.host_state_reload;
1463 if (sev_es_guest(svm->vcpu.kvm)) {
1464 sev_es_vcpu_put(svm);
1465 } else {
1466 kvm_load_ldt(svm->host.ldt);
1467 #ifdef CONFIG_X86_64
1468 loadsegment(fs, svm->host.fs);
1469 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1470 load_gs_index(svm->host.gs);
1471 #else
1472 #ifdef CONFIG_X86_32_LAZY_GS
1473 loadsegment(gs, svm->host.gs);
1474 #endif
1475 #endif
1476
1477 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1478 wrmsrl(host_save_user_msrs[i].index,
1479 svm->host_user_msrs[i]);
1480 }
1481 }
1482
1483 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1484 {
1485 struct vcpu_svm *svm = to_svm(vcpu);
1486 unsigned long rflags = svm->vmcb->save.rflags;
1487
1488 if (svm->nmi_singlestep) {
1489 /* Hide our flags if they were not set by the guest */
1490 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1491 rflags &= ~X86_EFLAGS_TF;
1492 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1493 rflags &= ~X86_EFLAGS_RF;
1494 }
1495 return rflags;
1496 }
1497
1498 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1499 {
1500 if (to_svm(vcpu)->nmi_singlestep)
1501 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1502
1503 /*
1504 * Any change of EFLAGS.VM is accompanied by a reload of SS
1505 * (caused by either a task switch or an inter-privilege IRET),
1506 * so we do not need to update the CPL here.
1507 */
1508 to_svm(vcpu)->vmcb->save.rflags = rflags;
1509 }
1510
1511 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1512 {
1513 switch (reg) {
1514 case VCPU_EXREG_PDPTR:
1515 BUG_ON(!npt_enabled);
1516 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1517 break;
1518 default:
1519 WARN_ON_ONCE(1);
1520 }
1521 }
1522
1523 static void svm_set_vintr(struct vcpu_svm *svm)
1524 {
1525 struct vmcb_control_area *control;
1526
1527 /* The following fields are ignored when AVIC is enabled */
1528 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1529 svm_set_intercept(svm, INTERCEPT_VINTR);
1530
1531 /*
1532 * This is just a dummy VINTR to actually cause a vmexit to happen.
1533 * Actual injection of virtual interrupts happens through EVENTINJ.
1534 */
1535 control = &svm->vmcb->control;
1536 control->int_vector = 0x0;
1537 control->int_ctl &= ~V_INTR_PRIO_MASK;
1538 control->int_ctl |= V_IRQ_MASK |
1539 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1540 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1541 }
1542
1543 static void svm_clear_vintr(struct vcpu_svm *svm)
1544 {
1545 const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1546 svm_clr_intercept(svm, INTERCEPT_VINTR);
1547
1548 /* Drop int_ctl fields related to VINTR injection. */
1549 svm->vmcb->control.int_ctl &= mask;
1550 if (is_guest_mode(&svm->vcpu)) {
1551 svm->nested.hsave->control.int_ctl &= mask;
1552
1553 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1554 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1555 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1556 }
1557
1558 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1559 }
1560
1561 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1562 {
1563 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1564
1565 switch (seg) {
1566 case VCPU_SREG_CS: return &save->cs;
1567 case VCPU_SREG_DS: return &save->ds;
1568 case VCPU_SREG_ES: return &save->es;
1569 case VCPU_SREG_FS: return &save->fs;
1570 case VCPU_SREG_GS: return &save->gs;
1571 case VCPU_SREG_SS: return &save->ss;
1572 case VCPU_SREG_TR: return &save->tr;
1573 case VCPU_SREG_LDTR: return &save->ldtr;
1574 }
1575 BUG();
1576 return NULL;
1577 }
1578
1579 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1580 {
1581 struct vmcb_seg *s = svm_seg(vcpu, seg);
1582
1583 return s->base;
1584 }
1585
1586 static void svm_get_segment(struct kvm_vcpu *vcpu,
1587 struct kvm_segment *var, int seg)
1588 {
1589 struct vmcb_seg *s = svm_seg(vcpu, seg);
1590
1591 var->base = s->base;
1592 var->limit = s->limit;
1593 var->selector = s->selector;
1594 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1595 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1596 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1597 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1598 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1599 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1600 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1601
1602 /*
1603 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1604 * However, the SVM spec states that the G bit is not observed by the
1605 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1606 * So let's synthesize a legal G bit for all segments, this helps
1607 * running KVM nested. It also helps cross-vendor migration, because
1608 * Intel's vmentry has a check on the 'G' bit.
1609 */
1610 var->g = s->limit > 0xfffff;
1611
1612 /*
1613 * AMD's VMCB does not have an explicit unusable field, so emulate it
1614 * for cross vendor migration purposes by "not present"
1615 */
1616 var->unusable = !var->present;
1617
1618 switch (seg) {
1619 case VCPU_SREG_TR:
1620 /*
1621 * Work around a bug where the busy flag in the tr selector
1622 * isn't exposed
1623 */
1624 var->type |= 0x2;
1625 break;
1626 case VCPU_SREG_DS:
1627 case VCPU_SREG_ES:
1628 case VCPU_SREG_FS:
1629 case VCPU_SREG_GS:
1630 /*
1631 * The accessed bit must always be set in the segment
1632 * descriptor cache, although it can be cleared in the
1633 * descriptor, the cached bit always remains at 1. Since
1634 * Intel has a check on this, set it here to support
1635 * cross-vendor migration.
1636 */
1637 if (!var->unusable)
1638 var->type |= 0x1;
1639 break;
1640 case VCPU_SREG_SS:
1641 /*
1642 * On AMD CPUs sometimes the DB bit in the segment
1643 * descriptor is left as 1, although the whole segment has
1644 * been made unusable. Clear it here to pass an Intel VMX
1645 * entry check when cross vendor migrating.
1646 */
1647 if (var->unusable)
1648 var->db = 0;
1649 /* This is symmetric with svm_set_segment() */
1650 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1651 break;
1652 }
1653 }
1654
1655 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1656 {
1657 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1658
1659 return save->cpl;
1660 }
1661
1662 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1663 {
1664 struct vcpu_svm *svm = to_svm(vcpu);
1665
1666 dt->size = svm->vmcb->save.idtr.limit;
1667 dt->address = svm->vmcb->save.idtr.base;
1668 }
1669
1670 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1671 {
1672 struct vcpu_svm *svm = to_svm(vcpu);
1673
1674 svm->vmcb->save.idtr.limit = dt->size;
1675 svm->vmcb->save.idtr.base = dt->address ;
1676 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1677 }
1678
1679 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1680 {
1681 struct vcpu_svm *svm = to_svm(vcpu);
1682
1683 dt->size = svm->vmcb->save.gdtr.limit;
1684 dt->address = svm->vmcb->save.gdtr.base;
1685 }
1686
1687 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1688 {
1689 struct vcpu_svm *svm = to_svm(vcpu);
1690
1691 svm->vmcb->save.gdtr.limit = dt->size;
1692 svm->vmcb->save.gdtr.base = dt->address ;
1693 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1694 }
1695
1696 static void update_cr0_intercept(struct vcpu_svm *svm)
1697 {
1698 ulong gcr0;
1699 u64 *hcr0;
1700
1701 /*
1702 * SEV-ES guests must always keep the CR intercepts cleared. CR
1703 * tracking is done using the CR write traps.
1704 */
1705 if (sev_es_guest(svm->vcpu.kvm))
1706 return;
1707
1708 gcr0 = svm->vcpu.arch.cr0;
1709 hcr0 = &svm->vmcb->save.cr0;
1710 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1711 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1712
1713 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1714
1715 if (gcr0 == *hcr0) {
1716 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1717 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1718 } else {
1719 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1720 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1721 }
1722 }
1723
1724 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1725 {
1726 struct vcpu_svm *svm = to_svm(vcpu);
1727
1728 #ifdef CONFIG_X86_64
1729 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1730 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1731 vcpu->arch.efer |= EFER_LMA;
1732 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1733 }
1734
1735 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1736 vcpu->arch.efer &= ~EFER_LMA;
1737 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1738 }
1739 }
1740 #endif
1741 vcpu->arch.cr0 = cr0;
1742
1743 if (!npt_enabled)
1744 cr0 |= X86_CR0_PG | X86_CR0_WP;
1745
1746 /*
1747 * re-enable caching here because the QEMU bios
1748 * does not do it - this results in some delay at
1749 * reboot
1750 */
1751 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1752 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1753 svm->vmcb->save.cr0 = cr0;
1754 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1755 update_cr0_intercept(svm);
1756 }
1757
1758 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1759 {
1760 return true;
1761 }
1762
1763 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1764 {
1765 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1766 unsigned long old_cr4 = vcpu->arch.cr4;
1767
1768 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1769 svm_flush_tlb(vcpu);
1770
1771 vcpu->arch.cr4 = cr4;
1772 if (!npt_enabled)
1773 cr4 |= X86_CR4_PAE;
1774 cr4 |= host_cr4_mce;
1775 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1776 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1777
1778 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1779 kvm_update_cpuid_runtime(vcpu);
1780 }
1781
1782 static void svm_set_segment(struct kvm_vcpu *vcpu,
1783 struct kvm_segment *var, int seg)
1784 {
1785 struct vcpu_svm *svm = to_svm(vcpu);
1786 struct vmcb_seg *s = svm_seg(vcpu, seg);
1787
1788 s->base = var->base;
1789 s->limit = var->limit;
1790 s->selector = var->selector;
1791 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1792 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1793 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1794 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1795 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1796 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1797 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1798 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1799
1800 /*
1801 * This is always accurate, except if SYSRET returned to a segment
1802 * with SS.DPL != 3. Intel does not have this quirk, and always
1803 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1804 * would entail passing the CPL to userspace and back.
1805 */
1806 if (seg == VCPU_SREG_SS)
1807 /* This is symmetric with svm_get_segment() */
1808 svm->vmcb->save.cpl = (var->dpl & 3);
1809
1810 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1811 }
1812
1813 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1814 {
1815 struct vcpu_svm *svm = to_svm(vcpu);
1816
1817 clr_exception_intercept(svm, BP_VECTOR);
1818
1819 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1820 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1821 set_exception_intercept(svm, BP_VECTOR);
1822 }
1823 }
1824
1825 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1826 {
1827 if (sd->next_asid > sd->max_asid) {
1828 ++sd->asid_generation;
1829 sd->next_asid = sd->min_asid;
1830 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1831 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1832 }
1833
1834 svm->asid_generation = sd->asid_generation;
1835 svm->asid = sd->next_asid++;
1836 }
1837
1838 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1839 {
1840 struct vmcb *vmcb = svm->vmcb;
1841
1842 if (svm->vcpu.arch.guest_state_protected)
1843 return;
1844
1845 if (unlikely(value != vmcb->save.dr6)) {
1846 vmcb->save.dr6 = value;
1847 vmcb_mark_dirty(vmcb, VMCB_DR);
1848 }
1849 }
1850
1851 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1852 {
1853 struct vcpu_svm *svm = to_svm(vcpu);
1854
1855 if (vcpu->arch.guest_state_protected)
1856 return;
1857
1858 get_debugreg(vcpu->arch.db[0], 0);
1859 get_debugreg(vcpu->arch.db[1], 1);
1860 get_debugreg(vcpu->arch.db[2], 2);
1861 get_debugreg(vcpu->arch.db[3], 3);
1862 /*
1863 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1864 * because db_interception might need it. We can do it before vmentry.
1865 */
1866 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1867 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1868 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1869 set_dr_intercepts(svm);
1870 }
1871
1872 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1873 {
1874 struct vcpu_svm *svm = to_svm(vcpu);
1875
1876 if (vcpu->arch.guest_state_protected)
1877 return;
1878
1879 svm->vmcb->save.dr7 = value;
1880 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1881 }
1882
1883 static int pf_interception(struct vcpu_svm *svm)
1884 {
1885 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1886 u64 error_code = svm->vmcb->control.exit_info_1;
1887
1888 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1889 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1890 svm->vmcb->control.insn_bytes : NULL,
1891 svm->vmcb->control.insn_len);
1892 }
1893
1894 static int npf_interception(struct vcpu_svm *svm)
1895 {
1896 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1897 u64 error_code = svm->vmcb->control.exit_info_1;
1898
1899 trace_kvm_page_fault(fault_address, error_code);
1900 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1901 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1902 svm->vmcb->control.insn_bytes : NULL,
1903 svm->vmcb->control.insn_len);
1904 }
1905
1906 static int db_interception(struct vcpu_svm *svm)
1907 {
1908 struct kvm_run *kvm_run = svm->vcpu.run;
1909 struct kvm_vcpu *vcpu = &svm->vcpu;
1910
1911 if (!(svm->vcpu.guest_debug &
1912 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1913 !svm->nmi_singlestep) {
1914 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1915 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1916 return 1;
1917 }
1918
1919 if (svm->nmi_singlestep) {
1920 disable_nmi_singlestep(svm);
1921 /* Make sure we check for pending NMIs upon entry */
1922 kvm_make_request(KVM_REQ_EVENT, vcpu);
1923 }
1924
1925 if (svm->vcpu.guest_debug &
1926 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1927 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1928 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1929 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1930 kvm_run->debug.arch.pc =
1931 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1932 kvm_run->debug.arch.exception = DB_VECTOR;
1933 return 0;
1934 }
1935
1936 return 1;
1937 }
1938
1939 static int bp_interception(struct vcpu_svm *svm)
1940 {
1941 struct kvm_run *kvm_run = svm->vcpu.run;
1942
1943 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1944 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1945 kvm_run->debug.arch.exception = BP_VECTOR;
1946 return 0;
1947 }
1948
1949 static int ud_interception(struct vcpu_svm *svm)
1950 {
1951 return handle_ud(&svm->vcpu);
1952 }
1953
1954 static int ac_interception(struct vcpu_svm *svm)
1955 {
1956 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1957 return 1;
1958 }
1959
1960 static int gp_interception(struct vcpu_svm *svm)
1961 {
1962 struct kvm_vcpu *vcpu = &svm->vcpu;
1963 u32 error_code = svm->vmcb->control.exit_info_1;
1964
1965 WARN_ON_ONCE(!enable_vmware_backdoor);
1966
1967 /*
1968 * VMware backdoor emulation on #GP interception only handles IN{S},
1969 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1970 */
1971 if (error_code) {
1972 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1973 return 1;
1974 }
1975 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1976 }
1977
1978 static bool is_erratum_383(void)
1979 {
1980 int err, i;
1981 u64 value;
1982
1983 if (!erratum_383_found)
1984 return false;
1985
1986 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1987 if (err)
1988 return false;
1989
1990 /* Bit 62 may or may not be set for this mce */
1991 value &= ~(1ULL << 62);
1992
1993 if (value != 0xb600000000010015ULL)
1994 return false;
1995
1996 /* Clear MCi_STATUS registers */
1997 for (i = 0; i < 6; ++i)
1998 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1999
2000 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2001 if (!err) {
2002 u32 low, high;
2003
2004 value &= ~(1ULL << 2);
2005 low = lower_32_bits(value);
2006 high = upper_32_bits(value);
2007
2008 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2009 }
2010
2011 /* Flush tlb to evict multi-match entries */
2012 __flush_tlb_all();
2013
2014 return true;
2015 }
2016
2017 static void svm_handle_mce(struct vcpu_svm *svm)
2018 {
2019 if (is_erratum_383()) {
2020 /*
2021 * Erratum 383 triggered. Guest state is corrupt so kill the
2022 * guest.
2023 */
2024 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2025
2026 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2027
2028 return;
2029 }
2030
2031 /*
2032 * On an #MC intercept the MCE handler is not called automatically in
2033 * the host. So do it by hand here.
2034 */
2035 kvm_machine_check();
2036 }
2037
2038 static int mc_interception(struct vcpu_svm *svm)
2039 {
2040 return 1;
2041 }
2042
2043 static int shutdown_interception(struct vcpu_svm *svm)
2044 {
2045 struct kvm_run *kvm_run = svm->vcpu.run;
2046
2047 /*
2048 * The VM save area has already been encrypted so it
2049 * cannot be reinitialized - just terminate.
2050 */
2051 if (sev_es_guest(svm->vcpu.kvm))
2052 return -EINVAL;
2053
2054 /*
2055 * VMCB is undefined after a SHUTDOWN intercept
2056 * so reinitialize it.
2057 */
2058 clear_page(svm->vmcb);
2059 init_vmcb(svm);
2060
2061 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2062 return 0;
2063 }
2064
2065 static int io_interception(struct vcpu_svm *svm)
2066 {
2067 struct kvm_vcpu *vcpu = &svm->vcpu;
2068 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2069 int size, in, string;
2070 unsigned port;
2071
2072 ++svm->vcpu.stat.io_exits;
2073 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2074 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2075 port = io_info >> 16;
2076 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2077
2078 if (string) {
2079 if (sev_es_guest(vcpu->kvm))
2080 return sev_es_string_io(svm, size, port, in);
2081 else
2082 return kvm_emulate_instruction(vcpu, 0);
2083 }
2084
2085 svm->next_rip = svm->vmcb->control.exit_info_2;
2086
2087 return kvm_fast_pio(&svm->vcpu, size, port, in);
2088 }
2089
2090 static int nmi_interception(struct vcpu_svm *svm)
2091 {
2092 return 1;
2093 }
2094
2095 static int intr_interception(struct vcpu_svm *svm)
2096 {
2097 ++svm->vcpu.stat.irq_exits;
2098 return 1;
2099 }
2100
2101 static int nop_on_interception(struct vcpu_svm *svm)
2102 {
2103 return 1;
2104 }
2105
2106 static int halt_interception(struct vcpu_svm *svm)
2107 {
2108 return kvm_emulate_halt(&svm->vcpu);
2109 }
2110
2111 static int vmmcall_interception(struct vcpu_svm *svm)
2112 {
2113 return kvm_emulate_hypercall(&svm->vcpu);
2114 }
2115
2116 static int vmload_interception(struct vcpu_svm *svm)
2117 {
2118 struct vmcb *nested_vmcb;
2119 struct kvm_host_map map;
2120 int ret;
2121
2122 if (nested_svm_check_permissions(svm))
2123 return 1;
2124
2125 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2126 if (ret) {
2127 if (ret == -EINVAL)
2128 kvm_inject_gp(&svm->vcpu, 0);
2129 return 1;
2130 }
2131
2132 nested_vmcb = map.hva;
2133
2134 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2135
2136 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2137 kvm_vcpu_unmap(&svm->vcpu, &map, true);
2138
2139 return ret;
2140 }
2141
2142 static int vmsave_interception(struct vcpu_svm *svm)
2143 {
2144 struct vmcb *nested_vmcb;
2145 struct kvm_host_map map;
2146 int ret;
2147
2148 if (nested_svm_check_permissions(svm))
2149 return 1;
2150
2151 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2152 if (ret) {
2153 if (ret == -EINVAL)
2154 kvm_inject_gp(&svm->vcpu, 0);
2155 return 1;
2156 }
2157
2158 nested_vmcb = map.hva;
2159
2160 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2161
2162 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2163 kvm_vcpu_unmap(&svm->vcpu, &map, true);
2164
2165 return ret;
2166 }
2167
2168 static int vmrun_interception(struct vcpu_svm *svm)
2169 {
2170 if (nested_svm_check_permissions(svm))
2171 return 1;
2172
2173 return nested_svm_vmrun(svm);
2174 }
2175
2176 void svm_set_gif(struct vcpu_svm *svm, bool value)
2177 {
2178 if (value) {
2179 /*
2180 * If VGIF is enabled, the STGI intercept is only added to
2181 * detect the opening of the SMI/NMI window; remove it now.
2182 * Likewise, clear the VINTR intercept, we will set it
2183 * again while processing KVM_REQ_EVENT if needed.
2184 */
2185 if (vgif_enabled(svm))
2186 svm_clr_intercept(svm, INTERCEPT_STGI);
2187 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2188 svm_clear_vintr(svm);
2189
2190 enable_gif(svm);
2191 if (svm->vcpu.arch.smi_pending ||
2192 svm->vcpu.arch.nmi_pending ||
2193 kvm_cpu_has_injectable_intr(&svm->vcpu))
2194 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2195 } else {
2196 disable_gif(svm);
2197
2198 /*
2199 * After a CLGI no interrupts should come. But if vGIF is
2200 * in use, we still rely on the VINTR intercept (rather than
2201 * STGI) to detect an open interrupt window.
2202 */
2203 if (!vgif_enabled(svm))
2204 svm_clear_vintr(svm);
2205 }
2206 }
2207
2208 static int stgi_interception(struct vcpu_svm *svm)
2209 {
2210 int ret;
2211
2212 if (nested_svm_check_permissions(svm))
2213 return 1;
2214
2215 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2216 svm_set_gif(svm, true);
2217 return ret;
2218 }
2219
2220 static int clgi_interception(struct vcpu_svm *svm)
2221 {
2222 int ret;
2223
2224 if (nested_svm_check_permissions(svm))
2225 return 1;
2226
2227 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2228 svm_set_gif(svm, false);
2229 return ret;
2230 }
2231
2232 static int invlpga_interception(struct vcpu_svm *svm)
2233 {
2234 struct kvm_vcpu *vcpu = &svm->vcpu;
2235
2236 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2237 kvm_rax_read(&svm->vcpu));
2238
2239 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2240 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2241
2242 return kvm_skip_emulated_instruction(&svm->vcpu);
2243 }
2244
2245 static int skinit_interception(struct vcpu_svm *svm)
2246 {
2247 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2248
2249 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2250 return 1;
2251 }
2252
2253 static int wbinvd_interception(struct vcpu_svm *svm)
2254 {
2255 return kvm_emulate_wbinvd(&svm->vcpu);
2256 }
2257
2258 static int xsetbv_interception(struct vcpu_svm *svm)
2259 {
2260 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2261 u32 index = kvm_rcx_read(&svm->vcpu);
2262
2263 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2264 return kvm_skip_emulated_instruction(&svm->vcpu);
2265 }
2266
2267 return 1;
2268 }
2269
2270 static int rdpru_interception(struct vcpu_svm *svm)
2271 {
2272 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2273 return 1;
2274 }
2275
2276 static int task_switch_interception(struct vcpu_svm *svm)
2277 {
2278 u16 tss_selector;
2279 int reason;
2280 int int_type = svm->vmcb->control.exit_int_info &
2281 SVM_EXITINTINFO_TYPE_MASK;
2282 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2283 uint32_t type =
2284 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2285 uint32_t idt_v =
2286 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2287 bool has_error_code = false;
2288 u32 error_code = 0;
2289
2290 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2291
2292 if (svm->vmcb->control.exit_info_2 &
2293 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2294 reason = TASK_SWITCH_IRET;
2295 else if (svm->vmcb->control.exit_info_2 &
2296 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2297 reason = TASK_SWITCH_JMP;
2298 else if (idt_v)
2299 reason = TASK_SWITCH_GATE;
2300 else
2301 reason = TASK_SWITCH_CALL;
2302
2303 if (reason == TASK_SWITCH_GATE) {
2304 switch (type) {
2305 case SVM_EXITINTINFO_TYPE_NMI:
2306 svm->vcpu.arch.nmi_injected = false;
2307 break;
2308 case SVM_EXITINTINFO_TYPE_EXEPT:
2309 if (svm->vmcb->control.exit_info_2 &
2310 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2311 has_error_code = true;
2312 error_code =
2313 (u32)svm->vmcb->control.exit_info_2;
2314 }
2315 kvm_clear_exception_queue(&svm->vcpu);
2316 break;
2317 case SVM_EXITINTINFO_TYPE_INTR:
2318 kvm_clear_interrupt_queue(&svm->vcpu);
2319 break;
2320 default:
2321 break;
2322 }
2323 }
2324
2325 if (reason != TASK_SWITCH_GATE ||
2326 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2327 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2328 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2329 if (!skip_emulated_instruction(&svm->vcpu))
2330 return 0;
2331 }
2332
2333 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2334 int_vec = -1;
2335
2336 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2337 has_error_code, error_code);
2338 }
2339
2340 static int cpuid_interception(struct vcpu_svm *svm)
2341 {
2342 return kvm_emulate_cpuid(&svm->vcpu);
2343 }
2344
2345 static int iret_interception(struct vcpu_svm *svm)
2346 {
2347 ++svm->vcpu.stat.nmi_window_exits;
2348 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2349 if (!sev_es_guest(svm->vcpu.kvm)) {
2350 svm_clr_intercept(svm, INTERCEPT_IRET);
2351 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2352 }
2353 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2354 return 1;
2355 }
2356
2357 static int invd_interception(struct vcpu_svm *svm)
2358 {
2359 /* Treat an INVD instruction as a NOP and just skip it. */
2360 return kvm_skip_emulated_instruction(&svm->vcpu);
2361 }
2362
2363 static int invlpg_interception(struct vcpu_svm *svm)
2364 {
2365 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2366 return kvm_emulate_instruction(&svm->vcpu, 0);
2367
2368 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2369 return kvm_skip_emulated_instruction(&svm->vcpu);
2370 }
2371
2372 static int emulate_on_interception(struct vcpu_svm *svm)
2373 {
2374 return kvm_emulate_instruction(&svm->vcpu, 0);
2375 }
2376
2377 static int rsm_interception(struct vcpu_svm *svm)
2378 {
2379 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2380 }
2381
2382 static int rdpmc_interception(struct vcpu_svm *svm)
2383 {
2384 int err;
2385
2386 if (!nrips)
2387 return emulate_on_interception(svm);
2388
2389 err = kvm_rdpmc(&svm->vcpu);
2390 return kvm_complete_insn_gp(&svm->vcpu, err);
2391 }
2392
2393 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2394 unsigned long val)
2395 {
2396 unsigned long cr0 = svm->vcpu.arch.cr0;
2397 bool ret = false;
2398
2399 if (!is_guest_mode(&svm->vcpu) ||
2400 (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2401 return false;
2402
2403 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2404 val &= ~SVM_CR0_SELECTIVE_MASK;
2405
2406 if (cr0 ^ val) {
2407 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2408 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2409 }
2410
2411 return ret;
2412 }
2413
2414 #define CR_VALID (1ULL << 63)
2415
2416 static int cr_interception(struct vcpu_svm *svm)
2417 {
2418 int reg, cr;
2419 unsigned long val;
2420 int err;
2421
2422 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2423 return emulate_on_interception(svm);
2424
2425 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2426 return emulate_on_interception(svm);
2427
2428 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2429 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2430 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2431 else
2432 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2433
2434 err = 0;
2435 if (cr >= 16) { /* mov to cr */
2436 cr -= 16;
2437 val = kvm_register_read(&svm->vcpu, reg);
2438 trace_kvm_cr_write(cr, val);
2439 switch (cr) {
2440 case 0:
2441 if (!check_selective_cr0_intercepted(svm, val))
2442 err = kvm_set_cr0(&svm->vcpu, val);
2443 else
2444 return 1;
2445
2446 break;
2447 case 3:
2448 err = kvm_set_cr3(&svm->vcpu, val);
2449 break;
2450 case 4:
2451 err = kvm_set_cr4(&svm->vcpu, val);
2452 break;
2453 case 8:
2454 err = kvm_set_cr8(&svm->vcpu, val);
2455 break;
2456 default:
2457 WARN(1, "unhandled write to CR%d", cr);
2458 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2459 return 1;
2460 }
2461 } else { /* mov from cr */
2462 switch (cr) {
2463 case 0:
2464 val = kvm_read_cr0(&svm->vcpu);
2465 break;
2466 case 2:
2467 val = svm->vcpu.arch.cr2;
2468 break;
2469 case 3:
2470 val = kvm_read_cr3(&svm->vcpu);
2471 break;
2472 case 4:
2473 val = kvm_read_cr4(&svm->vcpu);
2474 break;
2475 case 8:
2476 val = kvm_get_cr8(&svm->vcpu);
2477 break;
2478 default:
2479 WARN(1, "unhandled read from CR%d", cr);
2480 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2481 return 1;
2482 }
2483 kvm_register_write(&svm->vcpu, reg, val);
2484 trace_kvm_cr_read(cr, val);
2485 }
2486 return kvm_complete_insn_gp(&svm->vcpu, err);
2487 }
2488
2489 static int cr_trap(struct vcpu_svm *svm)
2490 {
2491 struct kvm_vcpu *vcpu = &svm->vcpu;
2492 unsigned long old_value, new_value;
2493 unsigned int cr;
2494 int ret = 0;
2495
2496 new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2497
2498 cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2499 switch (cr) {
2500 case 0:
2501 old_value = kvm_read_cr0(vcpu);
2502 svm_set_cr0(vcpu, new_value);
2503
2504 kvm_post_set_cr0(vcpu, old_value, new_value);
2505 break;
2506 case 4:
2507 old_value = kvm_read_cr4(vcpu);
2508 svm_set_cr4(vcpu, new_value);
2509
2510 kvm_post_set_cr4(vcpu, old_value, new_value);
2511 break;
2512 case 8:
2513 ret = kvm_set_cr8(&svm->vcpu, new_value);
2514 break;
2515 default:
2516 WARN(1, "unhandled CR%d write trap", cr);
2517 kvm_queue_exception(vcpu, UD_VECTOR);
2518 return 1;
2519 }
2520
2521 return kvm_complete_insn_gp(vcpu, ret);
2522 }
2523
2524 static int dr_interception(struct vcpu_svm *svm)
2525 {
2526 int reg, dr;
2527 unsigned long val;
2528
2529 if (svm->vcpu.guest_debug == 0) {
2530 /*
2531 * No more DR vmexits; force a reload of the debug registers
2532 * and reenter on this instruction. The next vmexit will
2533 * retrieve the full state of the debug registers.
2534 */
2535 clr_dr_intercepts(svm);
2536 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2537 return 1;
2538 }
2539
2540 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2541 return emulate_on_interception(svm);
2542
2543 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2544 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2545
2546 if (dr >= 16) { /* mov to DRn */
2547 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2548 return 1;
2549 val = kvm_register_read(&svm->vcpu, reg);
2550 kvm_set_dr(&svm->vcpu, dr - 16, val);
2551 } else {
2552 if (!kvm_require_dr(&svm->vcpu, dr))
2553 return 1;
2554 kvm_get_dr(&svm->vcpu, dr, &val);
2555 kvm_register_write(&svm->vcpu, reg, val);
2556 }
2557
2558 return kvm_skip_emulated_instruction(&svm->vcpu);
2559 }
2560
2561 static int cr8_write_interception(struct vcpu_svm *svm)
2562 {
2563 struct kvm_run *kvm_run = svm->vcpu.run;
2564 int r;
2565
2566 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2567 /* instruction emulation calls kvm_set_cr8() */
2568 r = cr_interception(svm);
2569 if (lapic_in_kernel(&svm->vcpu))
2570 return r;
2571 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2572 return r;
2573 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2574 return 0;
2575 }
2576
2577 static int efer_trap(struct vcpu_svm *svm)
2578 {
2579 struct msr_data msr_info;
2580 int ret;
2581
2582 /*
2583 * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2584 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2585 * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2586 * the guest doesn't have X86_FEATURE_SVM.
2587 */
2588 msr_info.host_initiated = false;
2589 msr_info.index = MSR_EFER;
2590 msr_info.data = svm->vmcb->control.exit_info_1 & ~EFER_SVME;
2591 ret = kvm_set_msr_common(&svm->vcpu, &msr_info);
2592
2593 return kvm_complete_insn_gp(&svm->vcpu, ret);
2594 }
2595
2596 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2597 {
2598 msr->data = 0;
2599
2600 switch (msr->index) {
2601 case MSR_F10H_DECFG:
2602 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2603 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2604 break;
2605 case MSR_IA32_PERF_CAPABILITIES:
2606 return 0;
2607 default:
2608 return KVM_MSR_RET_INVALID;
2609 }
2610
2611 return 0;
2612 }
2613
2614 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2615 {
2616 struct vcpu_svm *svm = to_svm(vcpu);
2617
2618 switch (msr_info->index) {
2619 case MSR_STAR:
2620 msr_info->data = svm->vmcb->save.star;
2621 break;
2622 #ifdef CONFIG_X86_64
2623 case MSR_LSTAR:
2624 msr_info->data = svm->vmcb->save.lstar;
2625 break;
2626 case MSR_CSTAR:
2627 msr_info->data = svm->vmcb->save.cstar;
2628 break;
2629 case MSR_KERNEL_GS_BASE:
2630 msr_info->data = svm->vmcb->save.kernel_gs_base;
2631 break;
2632 case MSR_SYSCALL_MASK:
2633 msr_info->data = svm->vmcb->save.sfmask;
2634 break;
2635 #endif
2636 case MSR_IA32_SYSENTER_CS:
2637 msr_info->data = svm->vmcb->save.sysenter_cs;
2638 break;
2639 case MSR_IA32_SYSENTER_EIP:
2640 msr_info->data = svm->sysenter_eip;
2641 break;
2642 case MSR_IA32_SYSENTER_ESP:
2643 msr_info->data = svm->sysenter_esp;
2644 break;
2645 case MSR_TSC_AUX:
2646 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2647 return 1;
2648 msr_info->data = svm->tsc_aux;
2649 break;
2650 /*
2651 * Nobody will change the following 5 values in the VMCB so we can
2652 * safely return them on rdmsr. They will always be 0 until LBRV is
2653 * implemented.
2654 */
2655 case MSR_IA32_DEBUGCTLMSR:
2656 msr_info->data = svm->vmcb->save.dbgctl;
2657 break;
2658 case MSR_IA32_LASTBRANCHFROMIP:
2659 msr_info->data = svm->vmcb->save.br_from;
2660 break;
2661 case MSR_IA32_LASTBRANCHTOIP:
2662 msr_info->data = svm->vmcb->save.br_to;
2663 break;
2664 case MSR_IA32_LASTINTFROMIP:
2665 msr_info->data = svm->vmcb->save.last_excp_from;
2666 break;
2667 case MSR_IA32_LASTINTTOIP:
2668 msr_info->data = svm->vmcb->save.last_excp_to;
2669 break;
2670 case MSR_VM_HSAVE_PA:
2671 msr_info->data = svm->nested.hsave_msr;
2672 break;
2673 case MSR_VM_CR:
2674 msr_info->data = svm->nested.vm_cr_msr;
2675 break;
2676 case MSR_IA32_SPEC_CTRL:
2677 if (!msr_info->host_initiated &&
2678 !guest_has_spec_ctrl_msr(vcpu))
2679 return 1;
2680
2681 msr_info->data = svm->spec_ctrl;
2682 break;
2683 case MSR_AMD64_VIRT_SPEC_CTRL:
2684 if (!msr_info->host_initiated &&
2685 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2686 return 1;
2687
2688 msr_info->data = svm->virt_spec_ctrl;
2689 break;
2690 case MSR_F15H_IC_CFG: {
2691
2692 int family, model;
2693
2694 family = guest_cpuid_family(vcpu);
2695 model = guest_cpuid_model(vcpu);
2696
2697 if (family < 0 || model < 0)
2698 return kvm_get_msr_common(vcpu, msr_info);
2699
2700 msr_info->data = 0;
2701
2702 if (family == 0x15 &&
2703 (model >= 0x2 && model < 0x20))
2704 msr_info->data = 0x1E;
2705 }
2706 break;
2707 case MSR_F10H_DECFG:
2708 msr_info->data = svm->msr_decfg;
2709 break;
2710 default:
2711 return kvm_get_msr_common(vcpu, msr_info);
2712 }
2713 return 0;
2714 }
2715
2716 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2717 {
2718 struct vcpu_svm *svm = to_svm(vcpu);
2719 if (!sev_es_guest(svm->vcpu.kvm) || !err)
2720 return kvm_complete_insn_gp(&svm->vcpu, err);
2721
2722 ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2723 ghcb_set_sw_exit_info_2(svm->ghcb,
2724 X86_TRAP_GP |
2725 SVM_EVTINJ_TYPE_EXEPT |
2726 SVM_EVTINJ_VALID);
2727 return 1;
2728 }
2729
2730 static int rdmsr_interception(struct vcpu_svm *svm)
2731 {
2732 return kvm_emulate_rdmsr(&svm->vcpu);
2733 }
2734
2735 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2736 {
2737 struct vcpu_svm *svm = to_svm(vcpu);
2738 int svm_dis, chg_mask;
2739
2740 if (data & ~SVM_VM_CR_VALID_MASK)
2741 return 1;
2742
2743 chg_mask = SVM_VM_CR_VALID_MASK;
2744
2745 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2746 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2747
2748 svm->nested.vm_cr_msr &= ~chg_mask;
2749 svm->nested.vm_cr_msr |= (data & chg_mask);
2750
2751 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2752
2753 /* check for svm_disable while efer.svme is set */
2754 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2755 return 1;
2756
2757 return 0;
2758 }
2759
2760 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2761 {
2762 struct vcpu_svm *svm = to_svm(vcpu);
2763
2764 u32 ecx = msr->index;
2765 u64 data = msr->data;
2766 switch (ecx) {
2767 case MSR_IA32_CR_PAT:
2768 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2769 return 1;
2770 vcpu->arch.pat = data;
2771 svm->vmcb->save.g_pat = data;
2772 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2773 break;
2774 case MSR_IA32_SPEC_CTRL:
2775 if (!msr->host_initiated &&
2776 !guest_has_spec_ctrl_msr(vcpu))
2777 return 1;
2778
2779 if (kvm_spec_ctrl_test_value(data))
2780 return 1;
2781
2782 svm->spec_ctrl = data;
2783 if (!data)
2784 break;
2785
2786 /*
2787 * For non-nested:
2788 * When it's written (to non-zero) for the first time, pass
2789 * it through.
2790 *
2791 * For nested:
2792 * The handling of the MSR bitmap for L2 guests is done in
2793 * nested_svm_vmrun_msrpm.
2794 * We update the L1 MSR bit as well since it will end up
2795 * touching the MSR anyway now.
2796 */
2797 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2798 break;
2799 case MSR_IA32_PRED_CMD:
2800 if (!msr->host_initiated &&
2801 !guest_has_pred_cmd_msr(vcpu))
2802 return 1;
2803
2804 if (data & ~PRED_CMD_IBPB)
2805 return 1;
2806 if (!boot_cpu_has(X86_FEATURE_IBPB))
2807 return 1;
2808 if (!data)
2809 break;
2810
2811 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2812 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2813 break;
2814 case MSR_AMD64_VIRT_SPEC_CTRL:
2815 if (!msr->host_initiated &&
2816 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2817 return 1;
2818
2819 if (data & ~SPEC_CTRL_SSBD)
2820 return 1;
2821
2822 svm->virt_spec_ctrl = data;
2823 break;
2824 case MSR_STAR:
2825 svm->vmcb->save.star = data;
2826 break;
2827 #ifdef CONFIG_X86_64
2828 case MSR_LSTAR:
2829 svm->vmcb->save.lstar = data;
2830 break;
2831 case MSR_CSTAR:
2832 svm->vmcb->save.cstar = data;
2833 break;
2834 case MSR_KERNEL_GS_BASE:
2835 svm->vmcb->save.kernel_gs_base = data;
2836 break;
2837 case MSR_SYSCALL_MASK:
2838 svm->vmcb->save.sfmask = data;
2839 break;
2840 #endif
2841 case MSR_IA32_SYSENTER_CS:
2842 svm->vmcb->save.sysenter_cs = data;
2843 break;
2844 case MSR_IA32_SYSENTER_EIP:
2845 svm->sysenter_eip = data;
2846 svm->vmcb->save.sysenter_eip = data;
2847 break;
2848 case MSR_IA32_SYSENTER_ESP:
2849 svm->sysenter_esp = data;
2850 svm->vmcb->save.sysenter_esp = data;
2851 break;
2852 case MSR_TSC_AUX:
2853 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2854 return 1;
2855
2856 /*
2857 * This is rare, so we update the MSR here instead of using
2858 * direct_access_msrs. Doing that would require a rdmsr in
2859 * svm_vcpu_put.
2860 */
2861 svm->tsc_aux = data;
2862 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2863 break;
2864 case MSR_IA32_DEBUGCTLMSR:
2865 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2866 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2867 __func__, data);
2868 break;
2869 }
2870 if (data & DEBUGCTL_RESERVED_BITS)
2871 return 1;
2872
2873 svm->vmcb->save.dbgctl = data;
2874 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2875 if (data & (1ULL<<0))
2876 svm_enable_lbrv(vcpu);
2877 else
2878 svm_disable_lbrv(vcpu);
2879 break;
2880 case MSR_VM_HSAVE_PA:
2881 svm->nested.hsave_msr = data;
2882 break;
2883 case MSR_VM_CR:
2884 return svm_set_vm_cr(vcpu, data);
2885 case MSR_VM_IGNNE:
2886 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2887 break;
2888 case MSR_F10H_DECFG: {
2889 struct kvm_msr_entry msr_entry;
2890
2891 msr_entry.index = msr->index;
2892 if (svm_get_msr_feature(&msr_entry))
2893 return 1;
2894
2895 /* Check the supported bits */
2896 if (data & ~msr_entry.data)
2897 return 1;
2898
2899 /* Don't allow the guest to change a bit, #GP */
2900 if (!msr->host_initiated && (data ^ msr_entry.data))
2901 return 1;
2902
2903 svm->msr_decfg = data;
2904 break;
2905 }
2906 case MSR_IA32_APICBASE:
2907 if (kvm_vcpu_apicv_active(vcpu))
2908 avic_update_vapic_bar(to_svm(vcpu), data);
2909 fallthrough;
2910 default:
2911 return kvm_set_msr_common(vcpu, msr);
2912 }
2913 return 0;
2914 }
2915
2916 static int wrmsr_interception(struct vcpu_svm *svm)
2917 {
2918 return kvm_emulate_wrmsr(&svm->vcpu);
2919 }
2920
2921 static int msr_interception(struct vcpu_svm *svm)
2922 {
2923 if (svm->vmcb->control.exit_info_1)
2924 return wrmsr_interception(svm);
2925 else
2926 return rdmsr_interception(svm);
2927 }
2928
2929 static int interrupt_window_interception(struct vcpu_svm *svm)
2930 {
2931 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2932 svm_clear_vintr(svm);
2933
2934 /*
2935 * For AVIC, the only reason to end up here is ExtINTs.
2936 * In this case AVIC was temporarily disabled for
2937 * requesting the IRQ window and we have to re-enable it.
2938 */
2939 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2940
2941 ++svm->vcpu.stat.irq_window_exits;
2942 return 1;
2943 }
2944
2945 static int pause_interception(struct vcpu_svm *svm)
2946 {
2947 struct kvm_vcpu *vcpu = &svm->vcpu;
2948 bool in_kernel;
2949
2950 /*
2951 * CPL is not made available for an SEV-ES guest, therefore
2952 * vcpu->arch.preempted_in_kernel can never be true. Just
2953 * set in_kernel to false as well.
2954 */
2955 in_kernel = !sev_es_guest(svm->vcpu.kvm) && svm_get_cpl(vcpu) == 0;
2956
2957 if (!kvm_pause_in_guest(vcpu->kvm))
2958 grow_ple_window(vcpu);
2959
2960 kvm_vcpu_on_spin(vcpu, in_kernel);
2961 return 1;
2962 }
2963
2964 static int nop_interception(struct vcpu_svm *svm)
2965 {
2966 return kvm_skip_emulated_instruction(&(svm->vcpu));
2967 }
2968
2969 static int monitor_interception(struct vcpu_svm *svm)
2970 {
2971 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2972 return nop_interception(svm);
2973 }
2974
2975 static int mwait_interception(struct vcpu_svm *svm)
2976 {
2977 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2978 return nop_interception(svm);
2979 }
2980
2981 static int invpcid_interception(struct vcpu_svm *svm)
2982 {
2983 struct kvm_vcpu *vcpu = &svm->vcpu;
2984 unsigned long type;
2985 gva_t gva;
2986
2987 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
2988 kvm_queue_exception(vcpu, UD_VECTOR);
2989 return 1;
2990 }
2991
2992 /*
2993 * For an INVPCID intercept:
2994 * EXITINFO1 provides the linear address of the memory operand.
2995 * EXITINFO2 provides the contents of the register operand.
2996 */
2997 type = svm->vmcb->control.exit_info_2;
2998 gva = svm->vmcb->control.exit_info_1;
2999
3000 if (type > 3) {
3001 kvm_inject_gp(vcpu, 0);
3002 return 1;
3003 }
3004
3005 return kvm_handle_invpcid(vcpu, type, gva);
3006 }
3007
3008 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3009 [SVM_EXIT_READ_CR0] = cr_interception,
3010 [SVM_EXIT_READ_CR3] = cr_interception,
3011 [SVM_EXIT_READ_CR4] = cr_interception,
3012 [SVM_EXIT_READ_CR8] = cr_interception,
3013 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3014 [SVM_EXIT_WRITE_CR0] = cr_interception,
3015 [SVM_EXIT_WRITE_CR3] = cr_interception,
3016 [SVM_EXIT_WRITE_CR4] = cr_interception,
3017 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3018 [SVM_EXIT_READ_DR0] = dr_interception,
3019 [SVM_EXIT_READ_DR1] = dr_interception,
3020 [SVM_EXIT_READ_DR2] = dr_interception,
3021 [SVM_EXIT_READ_DR3] = dr_interception,
3022 [SVM_EXIT_READ_DR4] = dr_interception,
3023 [SVM_EXIT_READ_DR5] = dr_interception,
3024 [SVM_EXIT_READ_DR6] = dr_interception,
3025 [SVM_EXIT_READ_DR7] = dr_interception,
3026 [SVM_EXIT_WRITE_DR0] = dr_interception,
3027 [SVM_EXIT_WRITE_DR1] = dr_interception,
3028 [SVM_EXIT_WRITE_DR2] = dr_interception,
3029 [SVM_EXIT_WRITE_DR3] = dr_interception,
3030 [SVM_EXIT_WRITE_DR4] = dr_interception,
3031 [SVM_EXIT_WRITE_DR5] = dr_interception,
3032 [SVM_EXIT_WRITE_DR6] = dr_interception,
3033 [SVM_EXIT_WRITE_DR7] = dr_interception,
3034 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3035 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3036 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3037 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3038 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3039 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3040 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
3041 [SVM_EXIT_INTR] = intr_interception,
3042 [SVM_EXIT_NMI] = nmi_interception,
3043 [SVM_EXIT_SMI] = nop_on_interception,
3044 [SVM_EXIT_INIT] = nop_on_interception,
3045 [SVM_EXIT_VINTR] = interrupt_window_interception,
3046 [SVM_EXIT_RDPMC] = rdpmc_interception,
3047 [SVM_EXIT_CPUID] = cpuid_interception,
3048 [SVM_EXIT_IRET] = iret_interception,
3049 [SVM_EXIT_INVD] = invd_interception,
3050 [SVM_EXIT_PAUSE] = pause_interception,
3051 [SVM_EXIT_HLT] = halt_interception,
3052 [SVM_EXIT_INVLPG] = invlpg_interception,
3053 [SVM_EXIT_INVLPGA] = invlpga_interception,
3054 [SVM_EXIT_IOIO] = io_interception,
3055 [SVM_EXIT_MSR] = msr_interception,
3056 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3057 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3058 [SVM_EXIT_VMRUN] = vmrun_interception,
3059 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3060 [SVM_EXIT_VMLOAD] = vmload_interception,
3061 [SVM_EXIT_VMSAVE] = vmsave_interception,
3062 [SVM_EXIT_STGI] = stgi_interception,
3063 [SVM_EXIT_CLGI] = clgi_interception,
3064 [SVM_EXIT_SKINIT] = skinit_interception,
3065 [SVM_EXIT_WBINVD] = wbinvd_interception,
3066 [SVM_EXIT_MONITOR] = monitor_interception,
3067 [SVM_EXIT_MWAIT] = mwait_interception,
3068 [SVM_EXIT_XSETBV] = xsetbv_interception,
3069 [SVM_EXIT_RDPRU] = rdpru_interception,
3070 [SVM_EXIT_EFER_WRITE_TRAP] = efer_trap,
3071 [SVM_EXIT_CR0_WRITE_TRAP] = cr_trap,
3072 [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap,
3073 [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap,
3074 [SVM_EXIT_INVPCID] = invpcid_interception,
3075 [SVM_EXIT_NPF] = npf_interception,
3076 [SVM_EXIT_RSM] = rsm_interception,
3077 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
3078 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
3079 [SVM_EXIT_VMGEXIT] = sev_handle_vmgexit,
3080 };
3081
3082 static void dump_vmcb(struct kvm_vcpu *vcpu)
3083 {
3084 struct vcpu_svm *svm = to_svm(vcpu);
3085 struct vmcb_control_area *control = &svm->vmcb->control;
3086 struct vmcb_save_area *save = &svm->vmcb->save;
3087
3088 if (!dump_invalid_vmcb) {
3089 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3090 return;
3091 }
3092
3093 pr_err("VMCB Control Area:\n");
3094 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3095 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3096 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3097 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3098 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3099 pr_err("%-20s%08x %08x\n", "intercepts:",
3100 control->intercepts[INTERCEPT_WORD3],
3101 control->intercepts[INTERCEPT_WORD4]);
3102 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3103 pr_err("%-20s%d\n", "pause filter threshold:",
3104 control->pause_filter_thresh);
3105 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3106 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3107 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3108 pr_err("%-20s%d\n", "asid:", control->asid);
3109 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3110 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3111 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3112 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3113 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3114 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3115 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3116 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3117 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3118 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3119 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3120 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3121 pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3122 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3123 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3124 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3125 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3126 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3127 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3128 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3129 pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3130 pr_err("VMCB State Save Area:\n");
3131 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3132 "es:",
3133 save->es.selector, save->es.attrib,
3134 save->es.limit, save->es.base);
3135 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3136 "cs:",
3137 save->cs.selector, save->cs.attrib,
3138 save->cs.limit, save->cs.base);
3139 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3140 "ss:",
3141 save->ss.selector, save->ss.attrib,
3142 save->ss.limit, save->ss.base);
3143 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3144 "ds:",
3145 save->ds.selector, save->ds.attrib,
3146 save->ds.limit, save->ds.base);
3147 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3148 "fs:",
3149 save->fs.selector, save->fs.attrib,
3150 save->fs.limit, save->fs.base);
3151 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3152 "gs:",
3153 save->gs.selector, save->gs.attrib,
3154 save->gs.limit, save->gs.base);
3155 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3156 "gdtr:",
3157 save->gdtr.selector, save->gdtr.attrib,
3158 save->gdtr.limit, save->gdtr.base);
3159 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3160 "ldtr:",
3161 save->ldtr.selector, save->ldtr.attrib,
3162 save->ldtr.limit, save->ldtr.base);
3163 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3164 "idtr:",
3165 save->idtr.selector, save->idtr.attrib,
3166 save->idtr.limit, save->idtr.base);
3167 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3168 "tr:",
3169 save->tr.selector, save->tr.attrib,
3170 save->tr.limit, save->tr.base);
3171 pr_err("cpl: %d efer: %016llx\n",
3172 save->cpl, save->efer);
3173 pr_err("%-15s %016llx %-13s %016llx\n",
3174 "cr0:", save->cr0, "cr2:", save->cr2);
3175 pr_err("%-15s %016llx %-13s %016llx\n",
3176 "cr3:", save->cr3, "cr4:", save->cr4);
3177 pr_err("%-15s %016llx %-13s %016llx\n",
3178 "dr6:", save->dr6, "dr7:", save->dr7);
3179 pr_err("%-15s %016llx %-13s %016llx\n",
3180 "rip:", save->rip, "rflags:", save->rflags);
3181 pr_err("%-15s %016llx %-13s %016llx\n",
3182 "rsp:", save->rsp, "rax:", save->rax);
3183 pr_err("%-15s %016llx %-13s %016llx\n",
3184 "star:", save->star, "lstar:", save->lstar);
3185 pr_err("%-15s %016llx %-13s %016llx\n",
3186 "cstar:", save->cstar, "sfmask:", save->sfmask);
3187 pr_err("%-15s %016llx %-13s %016llx\n",
3188 "kernel_gs_base:", save->kernel_gs_base,
3189 "sysenter_cs:", save->sysenter_cs);
3190 pr_err("%-15s %016llx %-13s %016llx\n",
3191 "sysenter_esp:", save->sysenter_esp,
3192 "sysenter_eip:", save->sysenter_eip);
3193 pr_err("%-15s %016llx %-13s %016llx\n",
3194 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3195 pr_err("%-15s %016llx %-13s %016llx\n",
3196 "br_from:", save->br_from, "br_to:", save->br_to);
3197 pr_err("%-15s %016llx %-13s %016llx\n",
3198 "excp_from:", save->last_excp_from,
3199 "excp_to:", save->last_excp_to);
3200 }
3201
3202 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3203 {
3204 if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3205 svm_exit_handlers[exit_code])
3206 return 0;
3207
3208 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3209 dump_vmcb(vcpu);
3210 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3211 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3212 vcpu->run->internal.ndata = 2;
3213 vcpu->run->internal.data[0] = exit_code;
3214 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3215
3216 return -EINVAL;
3217 }
3218
3219 int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code)
3220 {
3221 if (svm_handle_invalid_exit(&svm->vcpu, exit_code))
3222 return 0;
3223
3224 #ifdef CONFIG_RETPOLINE
3225 if (exit_code == SVM_EXIT_MSR)
3226 return msr_interception(svm);
3227 else if (exit_code == SVM_EXIT_VINTR)
3228 return interrupt_window_interception(svm);
3229 else if (exit_code == SVM_EXIT_INTR)
3230 return intr_interception(svm);
3231 else if (exit_code == SVM_EXIT_HLT)
3232 return halt_interception(svm);
3233 else if (exit_code == SVM_EXIT_NPF)
3234 return npf_interception(svm);
3235 #endif
3236 return svm_exit_handlers[exit_code](svm);
3237 }
3238
3239 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3240 u32 *intr_info, u32 *error_code)
3241 {
3242 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3243
3244 *info1 = control->exit_info_1;
3245 *info2 = control->exit_info_2;
3246 *intr_info = control->exit_int_info;
3247 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3248 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3249 *error_code = control->exit_int_info_err;
3250 else
3251 *error_code = 0;
3252 }
3253
3254 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3255 {
3256 struct vcpu_svm *svm = to_svm(vcpu);
3257 struct kvm_run *kvm_run = vcpu->run;
3258 u32 exit_code = svm->vmcb->control.exit_code;
3259
3260 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3261
3262 /* SEV-ES guests must use the CR write traps to track CR registers. */
3263 if (!sev_es_guest(vcpu->kvm)) {
3264 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3265 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3266 if (npt_enabled)
3267 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3268 }
3269
3270 if (is_guest_mode(vcpu)) {
3271 int vmexit;
3272
3273 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3274
3275 vmexit = nested_svm_exit_special(svm);
3276
3277 if (vmexit == NESTED_EXIT_CONTINUE)
3278 vmexit = nested_svm_exit_handled(svm);
3279
3280 if (vmexit == NESTED_EXIT_DONE)
3281 return 1;
3282 }
3283
3284 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3285 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3286 kvm_run->fail_entry.hardware_entry_failure_reason
3287 = svm->vmcb->control.exit_code;
3288 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3289 dump_vmcb(vcpu);
3290 return 0;
3291 }
3292
3293 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3294 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3295 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3296 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3297 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3298 "exit_code 0x%x\n",
3299 __func__, svm->vmcb->control.exit_int_info,
3300 exit_code);
3301
3302 if (exit_fastpath != EXIT_FASTPATH_NONE)
3303 return 1;
3304
3305 return svm_invoke_exit_handler(svm, exit_code);
3306 }
3307
3308 static void reload_tss(struct kvm_vcpu *vcpu)
3309 {
3310 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3311
3312 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3313 load_TR_desc();
3314 }
3315
3316 static void pre_svm_run(struct vcpu_svm *svm)
3317 {
3318 struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3319
3320 if (sev_guest(svm->vcpu.kvm))
3321 return pre_sev_run(svm, svm->vcpu.cpu);
3322
3323 /* FIXME: handle wraparound of asid_generation */
3324 if (svm->asid_generation != sd->asid_generation)
3325 new_asid(svm, sd);
3326 }
3327
3328 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3329 {
3330 struct vcpu_svm *svm = to_svm(vcpu);
3331
3332 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3333 vcpu->arch.hflags |= HF_NMI_MASK;
3334 if (!sev_es_guest(svm->vcpu.kvm))
3335 svm_set_intercept(svm, INTERCEPT_IRET);
3336 ++vcpu->stat.nmi_injections;
3337 }
3338
3339 static void svm_set_irq(struct kvm_vcpu *vcpu)
3340 {
3341 struct vcpu_svm *svm = to_svm(vcpu);
3342
3343 BUG_ON(!(gif_set(svm)));
3344
3345 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3346 ++vcpu->stat.irq_injections;
3347
3348 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3349 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3350 }
3351
3352 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3353 {
3354 struct vcpu_svm *svm = to_svm(vcpu);
3355
3356 /*
3357 * SEV-ES guests must always keep the CR intercepts cleared. CR
3358 * tracking is done using the CR write traps.
3359 */
3360 if (sev_es_guest(vcpu->kvm))
3361 return;
3362
3363 if (nested_svm_virtualize_tpr(vcpu))
3364 return;
3365
3366 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3367
3368 if (irr == -1)
3369 return;
3370
3371 if (tpr >= irr)
3372 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3373 }
3374
3375 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3376 {
3377 struct vcpu_svm *svm = to_svm(vcpu);
3378 struct vmcb *vmcb = svm->vmcb;
3379 bool ret;
3380
3381 if (!gif_set(svm))
3382 return true;
3383
3384 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3385 return false;
3386
3387 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3388 (svm->vcpu.arch.hflags & HF_NMI_MASK);
3389
3390 return ret;
3391 }
3392
3393 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3394 {
3395 struct vcpu_svm *svm = to_svm(vcpu);
3396 if (svm->nested.nested_run_pending)
3397 return -EBUSY;
3398
3399 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3400 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3401 return -EBUSY;
3402
3403 return !svm_nmi_blocked(vcpu);
3404 }
3405
3406 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3407 {
3408 struct vcpu_svm *svm = to_svm(vcpu);
3409
3410 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3411 }
3412
3413 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3414 {
3415 struct vcpu_svm *svm = to_svm(vcpu);
3416
3417 if (masked) {
3418 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3419 if (!sev_es_guest(svm->vcpu.kvm))
3420 svm_set_intercept(svm, INTERCEPT_IRET);
3421 } else {
3422 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3423 if (!sev_es_guest(svm->vcpu.kvm))
3424 svm_clr_intercept(svm, INTERCEPT_IRET);
3425 }
3426 }
3427
3428 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3429 {
3430 struct vcpu_svm *svm = to_svm(vcpu);
3431 struct vmcb *vmcb = svm->vmcb;
3432
3433 if (!gif_set(svm))
3434 return true;
3435
3436 if (sev_es_guest(svm->vcpu.kvm)) {
3437 /*
3438 * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3439 * bit to determine the state of the IF flag.
3440 */
3441 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3442 return true;
3443 } else if (is_guest_mode(vcpu)) {
3444 /* As long as interrupts are being delivered... */
3445 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3446 ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3447 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3448 return true;
3449
3450 /* ... vmexits aren't blocked by the interrupt shadow */
3451 if (nested_exit_on_intr(svm))
3452 return false;
3453 } else {
3454 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3455 return true;
3456 }
3457
3458 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3459 }
3460
3461 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3462 {
3463 struct vcpu_svm *svm = to_svm(vcpu);
3464 if (svm->nested.nested_run_pending)
3465 return -EBUSY;
3466
3467 /*
3468 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3469 * e.g. if the IRQ arrived asynchronously after checking nested events.
3470 */
3471 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3472 return -EBUSY;
3473
3474 return !svm_interrupt_blocked(vcpu);
3475 }
3476
3477 static void enable_irq_window(struct kvm_vcpu *vcpu)
3478 {
3479 struct vcpu_svm *svm = to_svm(vcpu);
3480
3481 /*
3482 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3483 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3484 * get that intercept, this function will be called again though and
3485 * we'll get the vintr intercept. However, if the vGIF feature is
3486 * enabled, the STGI interception will not occur. Enable the irq
3487 * window under the assumption that the hardware will set the GIF.
3488 */
3489 if (vgif_enabled(svm) || gif_set(svm)) {
3490 /*
3491 * IRQ window is not needed when AVIC is enabled,
3492 * unless we have pending ExtINT since it cannot be injected
3493 * via AVIC. In such case, we need to temporarily disable AVIC,
3494 * and fallback to injecting IRQ via V_IRQ.
3495 */
3496 svm_toggle_avic_for_irq_window(vcpu, false);
3497 svm_set_vintr(svm);
3498 }
3499 }
3500
3501 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3502 {
3503 struct vcpu_svm *svm = to_svm(vcpu);
3504
3505 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3506 == HF_NMI_MASK)
3507 return; /* IRET will cause a vm exit */
3508
3509 if (!gif_set(svm)) {
3510 if (vgif_enabled(svm))
3511 svm_set_intercept(svm, INTERCEPT_STGI);
3512 return; /* STGI will cause a vm exit */
3513 }
3514
3515 /*
3516 * Something prevents NMI from been injected. Single step over possible
3517 * problem (IRET or exception injection or interrupt shadow)
3518 */
3519 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3520 svm->nmi_singlestep = true;
3521 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3522 }
3523
3524 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3525 {
3526 return 0;
3527 }
3528
3529 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3530 {
3531 return 0;
3532 }
3533
3534 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3535 {
3536 struct vcpu_svm *svm = to_svm(vcpu);
3537
3538 /*
3539 * Flush only the current ASID even if the TLB flush was invoked via
3540 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3541 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3542 * unconditionally does a TLB flush on both nested VM-Enter and nested
3543 * VM-Exit (via kvm_mmu_reset_context()).
3544 */
3545 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3546 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3547 else
3548 svm->asid_generation--;
3549 }
3550
3551 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3552 {
3553 struct vcpu_svm *svm = to_svm(vcpu);
3554
3555 invlpga(gva, svm->vmcb->control.asid);
3556 }
3557
3558 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3559 {
3560 }
3561
3562 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3563 {
3564 struct vcpu_svm *svm = to_svm(vcpu);
3565
3566 if (nested_svm_virtualize_tpr(vcpu))
3567 return;
3568
3569 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3570 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3571 kvm_set_cr8(vcpu, cr8);
3572 }
3573 }
3574
3575 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3576 {
3577 struct vcpu_svm *svm = to_svm(vcpu);
3578 u64 cr8;
3579
3580 if (nested_svm_virtualize_tpr(vcpu) ||
3581 kvm_vcpu_apicv_active(vcpu))
3582 return;
3583
3584 cr8 = kvm_get_cr8(vcpu);
3585 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3586 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3587 }
3588
3589 static void svm_complete_interrupts(struct vcpu_svm *svm)
3590 {
3591 u8 vector;
3592 int type;
3593 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3594 unsigned int3_injected = svm->int3_injected;
3595
3596 svm->int3_injected = 0;
3597
3598 /*
3599 * If we've made progress since setting HF_IRET_MASK, we've
3600 * executed an IRET and can allow NMI injection.
3601 */
3602 if ((svm->vcpu.arch.hflags & HF_IRET_MASK) &&
3603 (sev_es_guest(svm->vcpu.kvm) ||
3604 kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip)) {
3605 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3606 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3607 }
3608
3609 svm->vcpu.arch.nmi_injected = false;
3610 kvm_clear_exception_queue(&svm->vcpu);
3611 kvm_clear_interrupt_queue(&svm->vcpu);
3612
3613 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3614 return;
3615
3616 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3617
3618 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3619 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3620
3621 switch (type) {
3622 case SVM_EXITINTINFO_TYPE_NMI:
3623 svm->vcpu.arch.nmi_injected = true;
3624 break;
3625 case SVM_EXITINTINFO_TYPE_EXEPT:
3626 /*
3627 * Never re-inject a #VC exception.
3628 */
3629 if (vector == X86_TRAP_VC)
3630 break;
3631
3632 /*
3633 * In case of software exceptions, do not reinject the vector,
3634 * but re-execute the instruction instead. Rewind RIP first
3635 * if we emulated INT3 before.
3636 */
3637 if (kvm_exception_is_soft(vector)) {
3638 if (vector == BP_VECTOR && int3_injected &&
3639 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3640 kvm_rip_write(&svm->vcpu,
3641 kvm_rip_read(&svm->vcpu) -
3642 int3_injected);
3643 break;
3644 }
3645 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3646 u32 err = svm->vmcb->control.exit_int_info_err;
3647 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3648
3649 } else
3650 kvm_requeue_exception(&svm->vcpu, vector);
3651 break;
3652 case SVM_EXITINTINFO_TYPE_INTR:
3653 kvm_queue_interrupt(&svm->vcpu, vector, false);
3654 break;
3655 default:
3656 break;
3657 }
3658 }
3659
3660 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3661 {
3662 struct vcpu_svm *svm = to_svm(vcpu);
3663 struct vmcb_control_area *control = &svm->vmcb->control;
3664
3665 control->exit_int_info = control->event_inj;
3666 control->exit_int_info_err = control->event_inj_err;
3667 control->event_inj = 0;
3668 svm_complete_interrupts(svm);
3669 }
3670
3671 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3672 {
3673 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3674 to_svm(vcpu)->vmcb->control.exit_info_1)
3675 return handle_fastpath_set_msr_irqoff(vcpu);
3676
3677 return EXIT_FASTPATH_NONE;
3678 }
3679
3680 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3681 struct vcpu_svm *svm)
3682 {
3683 /*
3684 * VMENTER enables interrupts (host state), but the kernel state is
3685 * interrupts disabled when this is invoked. Also tell RCU about
3686 * it. This is the same logic as for exit_to_user_mode().
3687 *
3688 * This ensures that e.g. latency analysis on the host observes
3689 * guest mode as interrupt enabled.
3690 *
3691 * guest_enter_irqoff() informs context tracking about the
3692 * transition to guest mode and if enabled adjusts RCU state
3693 * accordingly.
3694 */
3695 instrumentation_begin();
3696 trace_hardirqs_on_prepare();
3697 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3698 instrumentation_end();
3699
3700 guest_enter_irqoff();
3701 lockdep_hardirqs_on(CALLER_ADDR0);
3702
3703 if (sev_es_guest(svm->vcpu.kvm)) {
3704 __svm_sev_es_vcpu_run(svm->vmcb_pa);
3705 } else {
3706 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3707
3708 #ifdef CONFIG_X86_64
3709 native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3710 #else
3711 loadsegment(fs, svm->host.fs);
3712 #ifndef CONFIG_X86_32_LAZY_GS
3713 loadsegment(gs, svm->host.gs);
3714 #endif
3715 #endif
3716 }
3717
3718 /*
3719 * VMEXIT disables interrupts (host state), but tracing and lockdep
3720 * have them in state 'on' as recorded before entering guest mode.
3721 * Same as enter_from_user_mode().
3722 *
3723 * guest_exit_irqoff() restores host context and reinstates RCU if
3724 * enabled and required.
3725 *
3726 * This needs to be done before the below as native_read_msr()
3727 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3728 * into world and some more.
3729 */
3730 lockdep_hardirqs_off(CALLER_ADDR0);
3731 guest_exit_irqoff();
3732
3733 instrumentation_begin();
3734 trace_hardirqs_off_finish();
3735 instrumentation_end();
3736 }
3737
3738 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3739 {
3740 struct vcpu_svm *svm = to_svm(vcpu);
3741
3742 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3743 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3744 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3745
3746 /*
3747 * Disable singlestep if we're injecting an interrupt/exception.
3748 * We don't want our modified rflags to be pushed on the stack where
3749 * we might not be able to easily reset them if we disabled NMI
3750 * singlestep later.
3751 */
3752 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3753 /*
3754 * Event injection happens before external interrupts cause a
3755 * vmexit and interrupts are disabled here, so smp_send_reschedule
3756 * is enough to force an immediate vmexit.
3757 */
3758 disable_nmi_singlestep(svm);
3759 smp_send_reschedule(vcpu->cpu);
3760 }
3761
3762 pre_svm_run(svm);
3763
3764 sync_lapic_to_cr8(vcpu);
3765
3766 if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3767 svm->vmcb->control.asid = svm->asid;
3768 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3769 }
3770 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3771
3772 /*
3773 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3774 * of a #DB.
3775 */
3776 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3777 svm_set_dr6(svm, vcpu->arch.dr6);
3778 else
3779 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3780
3781 clgi();
3782 kvm_load_guest_xsave_state(vcpu);
3783
3784 kvm_wait_lapic_expire(vcpu);
3785
3786 /*
3787 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3788 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3789 * is no need to worry about the conditional branch over the wrmsr
3790 * being speculatively taken.
3791 */
3792 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3793
3794 svm_vcpu_enter_exit(vcpu, svm);
3795
3796 /*
3797 * We do not use IBRS in the kernel. If this vCPU has used the
3798 * SPEC_CTRL MSR it may have left it on; save the value and
3799 * turn it off. This is much more efficient than blindly adding
3800 * it to the atomic save/restore list. Especially as the former
3801 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3802 *
3803 * For non-nested case:
3804 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3805 * save it.
3806 *
3807 * For nested case:
3808 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3809 * save it.
3810 */
3811 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3812 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3813
3814 if (!sev_es_guest(svm->vcpu.kvm))
3815 reload_tss(vcpu);
3816
3817 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3818
3819 if (!sev_es_guest(svm->vcpu.kvm)) {
3820 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3821 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3822 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3823 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3824 }
3825
3826 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3827 kvm_before_interrupt(&svm->vcpu);
3828
3829 kvm_load_host_xsave_state(vcpu);
3830 stgi();
3831
3832 /* Any pending NMI will happen here */
3833
3834 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3835 kvm_after_interrupt(&svm->vcpu);
3836
3837 sync_cr8_to_lapic(vcpu);
3838
3839 svm->next_rip = 0;
3840 if (is_guest_mode(&svm->vcpu)) {
3841 sync_nested_vmcb_control(svm);
3842 svm->nested.nested_run_pending = 0;
3843 }
3844
3845 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3846 vmcb_mark_all_clean(svm->vmcb);
3847
3848 /* if exit due to PF check for async PF */
3849 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3850 svm->vcpu.arch.apf.host_apf_flags =
3851 kvm_read_and_reset_apf_flags();
3852
3853 if (npt_enabled) {
3854 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3855 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3856 }
3857
3858 /*
3859 * We need to handle MC intercepts here before the vcpu has a chance to
3860 * change the physical cpu
3861 */
3862 if (unlikely(svm->vmcb->control.exit_code ==
3863 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3864 svm_handle_mce(svm);
3865
3866 svm_complete_interrupts(svm);
3867
3868 if (is_guest_mode(vcpu))
3869 return EXIT_FASTPATH_NONE;
3870
3871 return svm_exit_handlers_fastpath(vcpu);
3872 }
3873
3874 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3875 int root_level)
3876 {
3877 struct vcpu_svm *svm = to_svm(vcpu);
3878 unsigned long cr3;
3879
3880 cr3 = __sme_set(root);
3881 if (npt_enabled) {
3882 svm->vmcb->control.nested_cr3 = cr3;
3883 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3884
3885 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
3886 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3887 return;
3888 cr3 = vcpu->arch.cr3;
3889 }
3890
3891 svm->vmcb->save.cr3 = cr3;
3892 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3893 }
3894
3895 static int is_disabled(void)
3896 {
3897 u64 vm_cr;
3898
3899 rdmsrl(MSR_VM_CR, vm_cr);
3900 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3901 return 1;
3902
3903 return 0;
3904 }
3905
3906 static void
3907 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3908 {
3909 /*
3910 * Patch in the VMMCALL instruction:
3911 */
3912 hypercall[0] = 0x0f;
3913 hypercall[1] = 0x01;
3914 hypercall[2] = 0xd9;
3915 }
3916
3917 static int __init svm_check_processor_compat(void)
3918 {
3919 return 0;
3920 }
3921
3922 static bool svm_cpu_has_accelerated_tpr(void)
3923 {
3924 return false;
3925 }
3926
3927 /*
3928 * The kvm parameter can be NULL (module initialization, or invocation before
3929 * VM creation). Be sure to check the kvm parameter before using it.
3930 */
3931 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
3932 {
3933 switch (index) {
3934 case MSR_IA32_MCG_EXT_CTL:
3935 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3936 return false;
3937 case MSR_IA32_SMBASE:
3938 /* SEV-ES guests do not support SMM, so report false */
3939 if (kvm && sev_es_guest(kvm))
3940 return false;
3941 break;
3942 default:
3943 break;
3944 }
3945
3946 return true;
3947 }
3948
3949 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3950 {
3951 return 0;
3952 }
3953
3954 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3955 {
3956 struct vcpu_svm *svm = to_svm(vcpu);
3957 struct kvm_cpuid_entry2 *best;
3958
3959 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3960 boot_cpu_has(X86_FEATURE_XSAVE) &&
3961 boot_cpu_has(X86_FEATURE_XSAVES);
3962
3963 /* Update nrips enabled cache */
3964 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3965 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3966
3967 /* Check again if INVPCID interception if required */
3968 svm_check_invpcid(svm);
3969
3970 /* For sev guests, the memory encryption bit is not reserved in CR3. */
3971 if (sev_guest(vcpu->kvm)) {
3972 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
3973 if (best)
3974 vcpu->arch.cr3_lm_rsvd_bits &= ~(1UL << (best->ebx & 0x3f));
3975 }
3976
3977 if (!kvm_vcpu_apicv_active(vcpu))
3978 return;
3979
3980 /*
3981 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3982 * is exposed to the guest, disable AVIC.
3983 */
3984 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3985 kvm_request_apicv_update(vcpu->kvm, false,
3986 APICV_INHIBIT_REASON_X2APIC);
3987
3988 /*
3989 * Currently, AVIC does not work with nested virtualization.
3990 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3991 */
3992 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3993 kvm_request_apicv_update(vcpu->kvm, false,
3994 APICV_INHIBIT_REASON_NESTED);
3995 }
3996
3997 static bool svm_has_wbinvd_exit(void)
3998 {
3999 return true;
4000 }
4001
4002 #define PRE_EX(exit) { .exit_code = (exit), \
4003 .stage = X86_ICPT_PRE_EXCEPT, }
4004 #define POST_EX(exit) { .exit_code = (exit), \
4005 .stage = X86_ICPT_POST_EXCEPT, }
4006 #define POST_MEM(exit) { .exit_code = (exit), \
4007 .stage = X86_ICPT_POST_MEMACCESS, }
4008
4009 static const struct __x86_intercept {
4010 u32 exit_code;
4011 enum x86_intercept_stage stage;
4012 } x86_intercept_map[] = {
4013 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4014 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4015 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4016 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4017 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4018 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4019 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4020 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4021 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4022 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4023 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4024 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4025 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4026 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4027 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4028 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4029 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4030 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4031 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4032 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4033 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4034 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4035 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4036 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4037 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4038 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4039 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4040 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4041 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4042 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4043 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4044 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4045 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4046 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4047 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4048 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4049 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4050 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4051 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4052 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4053 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4054 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4055 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4056 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4057 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4058 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4059 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
4060 };
4061
4062 #undef PRE_EX
4063 #undef POST_EX
4064 #undef POST_MEM
4065
4066 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4067 struct x86_instruction_info *info,
4068 enum x86_intercept_stage stage,
4069 struct x86_exception *exception)
4070 {
4071 struct vcpu_svm *svm = to_svm(vcpu);
4072 int vmexit, ret = X86EMUL_CONTINUE;
4073 struct __x86_intercept icpt_info;
4074 struct vmcb *vmcb = svm->vmcb;
4075
4076 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4077 goto out;
4078
4079 icpt_info = x86_intercept_map[info->intercept];
4080
4081 if (stage != icpt_info.stage)
4082 goto out;
4083
4084 switch (icpt_info.exit_code) {
4085 case SVM_EXIT_READ_CR0:
4086 if (info->intercept == x86_intercept_cr_read)
4087 icpt_info.exit_code += info->modrm_reg;
4088 break;
4089 case SVM_EXIT_WRITE_CR0: {
4090 unsigned long cr0, val;
4091
4092 if (info->intercept == x86_intercept_cr_write)
4093 icpt_info.exit_code += info->modrm_reg;
4094
4095 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4096 info->intercept == x86_intercept_clts)
4097 break;
4098
4099 if (!(vmcb_is_intercept(&svm->nested.ctl,
4100 INTERCEPT_SELECTIVE_CR0)))
4101 break;
4102
4103 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4104 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4105
4106 if (info->intercept == x86_intercept_lmsw) {
4107 cr0 &= 0xfUL;
4108 val &= 0xfUL;
4109 /* lmsw can't clear PE - catch this here */
4110 if (cr0 & X86_CR0_PE)
4111 val |= X86_CR0_PE;
4112 }
4113
4114 if (cr0 ^ val)
4115 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4116
4117 break;
4118 }
4119 case SVM_EXIT_READ_DR0:
4120 case SVM_EXIT_WRITE_DR0:
4121 icpt_info.exit_code += info->modrm_reg;
4122 break;
4123 case SVM_EXIT_MSR:
4124 if (info->intercept == x86_intercept_wrmsr)
4125 vmcb->control.exit_info_1 = 1;
4126 else
4127 vmcb->control.exit_info_1 = 0;
4128 break;
4129 case SVM_EXIT_PAUSE:
4130 /*
4131 * We get this for NOP only, but pause
4132 * is rep not, check this here
4133 */
4134 if (info->rep_prefix != REPE_PREFIX)
4135 goto out;
4136 break;
4137 case SVM_EXIT_IOIO: {
4138 u64 exit_info;
4139 u32 bytes;
4140
4141 if (info->intercept == x86_intercept_in ||
4142 info->intercept == x86_intercept_ins) {
4143 exit_info = ((info->src_val & 0xffff) << 16) |
4144 SVM_IOIO_TYPE_MASK;
4145 bytes = info->dst_bytes;
4146 } else {
4147 exit_info = (info->dst_val & 0xffff) << 16;
4148 bytes = info->src_bytes;
4149 }
4150
4151 if (info->intercept == x86_intercept_outs ||
4152 info->intercept == x86_intercept_ins)
4153 exit_info |= SVM_IOIO_STR_MASK;
4154
4155 if (info->rep_prefix)
4156 exit_info |= SVM_IOIO_REP_MASK;
4157
4158 bytes = min(bytes, 4u);
4159
4160 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4161
4162 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4163
4164 vmcb->control.exit_info_1 = exit_info;
4165 vmcb->control.exit_info_2 = info->next_rip;
4166
4167 break;
4168 }
4169 default:
4170 break;
4171 }
4172
4173 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4174 if (static_cpu_has(X86_FEATURE_NRIPS))
4175 vmcb->control.next_rip = info->next_rip;
4176 vmcb->control.exit_code = icpt_info.exit_code;
4177 vmexit = nested_svm_exit_handled(svm);
4178
4179 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4180 : X86EMUL_CONTINUE;
4181
4182 out:
4183 return ret;
4184 }
4185
4186 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4187 {
4188 }
4189
4190 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4191 {
4192 if (!kvm_pause_in_guest(vcpu->kvm))
4193 shrink_ple_window(vcpu);
4194 }
4195
4196 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4197 {
4198 /* [63:9] are reserved. */
4199 vcpu->arch.mcg_cap &= 0x1ff;
4200 }
4201
4202 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4203 {
4204 struct vcpu_svm *svm = to_svm(vcpu);
4205
4206 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4207 if (!gif_set(svm))
4208 return true;
4209
4210 return is_smm(vcpu);
4211 }
4212
4213 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4214 {
4215 struct vcpu_svm *svm = to_svm(vcpu);
4216 if (svm->nested.nested_run_pending)
4217 return -EBUSY;
4218
4219 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4220 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4221 return -EBUSY;
4222
4223 return !svm_smi_blocked(vcpu);
4224 }
4225
4226 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4227 {
4228 struct vcpu_svm *svm = to_svm(vcpu);
4229 int ret;
4230
4231 if (is_guest_mode(vcpu)) {
4232 /* FED8h - SVM Guest */
4233 put_smstate(u64, smstate, 0x7ed8, 1);
4234 /* FEE0h - SVM Guest VMCB Physical Address */
4235 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4236
4237 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4238 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4239 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4240
4241 ret = nested_svm_vmexit(svm);
4242 if (ret)
4243 return ret;
4244 }
4245 return 0;
4246 }
4247
4248 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4249 {
4250 struct vcpu_svm *svm = to_svm(vcpu);
4251 struct kvm_host_map map;
4252 int ret = 0;
4253
4254 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4255 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4256 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4257 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4258
4259 if (guest) {
4260 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4261 return 1;
4262
4263 if (!(saved_efer & EFER_SVME))
4264 return 1;
4265
4266 if (kvm_vcpu_map(&svm->vcpu,
4267 gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4268 return 1;
4269
4270 if (svm_allocate_nested(svm))
4271 return 1;
4272
4273 ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
4274 kvm_vcpu_unmap(&svm->vcpu, &map, true);
4275 }
4276 }
4277
4278 return ret;
4279 }
4280
4281 static void enable_smi_window(struct kvm_vcpu *vcpu)
4282 {
4283 struct vcpu_svm *svm = to_svm(vcpu);
4284
4285 if (!gif_set(svm)) {
4286 if (vgif_enabled(svm))
4287 svm_set_intercept(svm, INTERCEPT_STGI);
4288 /* STGI will cause a vm exit */
4289 } else {
4290 /* We must be in SMM; RSM will cause a vmexit anyway. */
4291 }
4292 }
4293
4294 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4295 {
4296 bool smep, smap, is_user;
4297 unsigned long cr4;
4298
4299 /*
4300 * When the guest is an SEV-ES guest, emulation is not possible.
4301 */
4302 if (sev_es_guest(vcpu->kvm))
4303 return false;
4304
4305 /*
4306 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4307 *
4308 * Errata:
4309 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4310 * possible that CPU microcode implementing DecodeAssist will fail
4311 * to read bytes of instruction which caused #NPF. In this case,
4312 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4313 * return 0 instead of the correct guest instruction bytes.
4314 *
4315 * This happens because CPU microcode reading instruction bytes
4316 * uses a special opcode which attempts to read data using CPL=0
4317 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4318 * fault, it gives up and returns no instruction bytes.
4319 *
4320 * Detection:
4321 * We reach here in case CPU supports DecodeAssist, raised #NPF and
4322 * returned 0 in GuestIntrBytes field of the VMCB.
4323 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4324 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4325 * in case vCPU CPL==3 (Because otherwise guest would have triggered
4326 * a SMEP fault instead of #NPF).
4327 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4328 * As most guests enable SMAP if they have also enabled SMEP, use above
4329 * logic in order to attempt minimize false-positive of detecting errata
4330 * while still preserving all cases semantic correctness.
4331 *
4332 * Workaround:
4333 * To determine what instruction the guest was executing, the hypervisor
4334 * will have to decode the instruction at the instruction pointer.
4335 *
4336 * In non SEV guest, hypervisor will be able to read the guest
4337 * memory to decode the instruction pointer when insn_len is zero
4338 * so we return true to indicate that decoding is possible.
4339 *
4340 * But in the SEV guest, the guest memory is encrypted with the
4341 * guest specific key and hypervisor will not be able to decode the
4342 * instruction pointer so we will not able to workaround it. Lets
4343 * print the error and request to kill the guest.
4344 */
4345 if (likely(!insn || insn_len))
4346 return true;
4347
4348 /*
4349 * If RIP is invalid, go ahead with emulation which will cause an
4350 * internal error exit.
4351 */
4352 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4353 return true;
4354
4355 cr4 = kvm_read_cr4(vcpu);
4356 smep = cr4 & X86_CR4_SMEP;
4357 smap = cr4 & X86_CR4_SMAP;
4358 is_user = svm_get_cpl(vcpu) == 3;
4359 if (smap && (!smep || is_user)) {
4360 if (!sev_guest(vcpu->kvm))
4361 return true;
4362
4363 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4364 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4365 }
4366
4367 return false;
4368 }
4369
4370 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4371 {
4372 struct vcpu_svm *svm = to_svm(vcpu);
4373
4374 /*
4375 * TODO: Last condition latch INIT signals on vCPU when
4376 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4377 * To properly emulate the INIT intercept,
4378 * svm_check_nested_events() should call nested_svm_vmexit()
4379 * if an INIT signal is pending.
4380 */
4381 return !gif_set(svm) ||
4382 (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4383 }
4384
4385 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4386 {
4387 if (!sev_es_guest(vcpu->kvm))
4388 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4389
4390 sev_vcpu_deliver_sipi_vector(vcpu, vector);
4391 }
4392
4393 static void svm_vm_destroy(struct kvm *kvm)
4394 {
4395 avic_vm_destroy(kvm);
4396 sev_vm_destroy(kvm);
4397 }
4398
4399 static int svm_vm_init(struct kvm *kvm)
4400 {
4401 if (!pause_filter_count || !pause_filter_thresh)
4402 kvm->arch.pause_in_guest = true;
4403
4404 if (avic) {
4405 int ret = avic_vm_init(kvm);
4406 if (ret)
4407 return ret;
4408 }
4409
4410 kvm_apicv_init(kvm, avic);
4411 return 0;
4412 }
4413
4414 static struct kvm_x86_ops svm_x86_ops __initdata = {
4415 .hardware_unsetup = svm_hardware_teardown,
4416 .hardware_enable = svm_hardware_enable,
4417 .hardware_disable = svm_hardware_disable,
4418 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4419 .has_emulated_msr = svm_has_emulated_msr,
4420
4421 .vcpu_create = svm_create_vcpu,
4422 .vcpu_free = svm_free_vcpu,
4423 .vcpu_reset = svm_vcpu_reset,
4424
4425 .vm_size = sizeof(struct kvm_svm),
4426 .vm_init = svm_vm_init,
4427 .vm_destroy = svm_vm_destroy,
4428
4429 .prepare_guest_switch = svm_prepare_guest_switch,
4430 .vcpu_load = svm_vcpu_load,
4431 .vcpu_put = svm_vcpu_put,
4432 .vcpu_blocking = svm_vcpu_blocking,
4433 .vcpu_unblocking = svm_vcpu_unblocking,
4434
4435 .update_exception_bitmap = update_exception_bitmap,
4436 .get_msr_feature = svm_get_msr_feature,
4437 .get_msr = svm_get_msr,
4438 .set_msr = svm_set_msr,
4439 .get_segment_base = svm_get_segment_base,
4440 .get_segment = svm_get_segment,
4441 .set_segment = svm_set_segment,
4442 .get_cpl = svm_get_cpl,
4443 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4444 .set_cr0 = svm_set_cr0,
4445 .is_valid_cr4 = svm_is_valid_cr4,
4446 .set_cr4 = svm_set_cr4,
4447 .set_efer = svm_set_efer,
4448 .get_idt = svm_get_idt,
4449 .set_idt = svm_set_idt,
4450 .get_gdt = svm_get_gdt,
4451 .set_gdt = svm_set_gdt,
4452 .set_dr7 = svm_set_dr7,
4453 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4454 .cache_reg = svm_cache_reg,
4455 .get_rflags = svm_get_rflags,
4456 .set_rflags = svm_set_rflags,
4457
4458 .tlb_flush_all = svm_flush_tlb,
4459 .tlb_flush_current = svm_flush_tlb,
4460 .tlb_flush_gva = svm_flush_tlb_gva,
4461 .tlb_flush_guest = svm_flush_tlb,
4462
4463 .run = svm_vcpu_run,
4464 .handle_exit = handle_exit,
4465 .skip_emulated_instruction = skip_emulated_instruction,
4466 .update_emulated_instruction = NULL,
4467 .set_interrupt_shadow = svm_set_interrupt_shadow,
4468 .get_interrupt_shadow = svm_get_interrupt_shadow,
4469 .patch_hypercall = svm_patch_hypercall,
4470 .set_irq = svm_set_irq,
4471 .set_nmi = svm_inject_nmi,
4472 .queue_exception = svm_queue_exception,
4473 .cancel_injection = svm_cancel_injection,
4474 .interrupt_allowed = svm_interrupt_allowed,
4475 .nmi_allowed = svm_nmi_allowed,
4476 .get_nmi_mask = svm_get_nmi_mask,
4477 .set_nmi_mask = svm_set_nmi_mask,
4478 .enable_nmi_window = enable_nmi_window,
4479 .enable_irq_window = enable_irq_window,
4480 .update_cr8_intercept = update_cr8_intercept,
4481 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4482 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4483 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4484 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4485 .load_eoi_exitmap = svm_load_eoi_exitmap,
4486 .hwapic_irr_update = svm_hwapic_irr_update,
4487 .hwapic_isr_update = svm_hwapic_isr_update,
4488 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4489 .apicv_post_state_restore = avic_post_state_restore,
4490
4491 .set_tss_addr = svm_set_tss_addr,
4492 .set_identity_map_addr = svm_set_identity_map_addr,
4493 .get_mt_mask = svm_get_mt_mask,
4494
4495 .get_exit_info = svm_get_exit_info,
4496
4497 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4498
4499 .has_wbinvd_exit = svm_has_wbinvd_exit,
4500
4501 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4502
4503 .load_mmu_pgd = svm_load_mmu_pgd,
4504
4505 .check_intercept = svm_check_intercept,
4506 .handle_exit_irqoff = svm_handle_exit_irqoff,
4507
4508 .request_immediate_exit = __kvm_request_immediate_exit,
4509
4510 .sched_in = svm_sched_in,
4511
4512 .pmu_ops = &amd_pmu_ops,
4513 .nested_ops = &svm_nested_ops,
4514
4515 .deliver_posted_interrupt = svm_deliver_avic_intr,
4516 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4517 .update_pi_irte = svm_update_pi_irte,
4518 .setup_mce = svm_setup_mce,
4519
4520 .smi_allowed = svm_smi_allowed,
4521 .pre_enter_smm = svm_pre_enter_smm,
4522 .pre_leave_smm = svm_pre_leave_smm,
4523 .enable_smi_window = enable_smi_window,
4524
4525 .mem_enc_op = svm_mem_enc_op,
4526 .mem_enc_reg_region = svm_register_enc_region,
4527 .mem_enc_unreg_region = svm_unregister_enc_region,
4528
4529 .can_emulate_instruction = svm_can_emulate_instruction,
4530
4531 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4532
4533 .msr_filter_changed = svm_msr_filter_changed,
4534 .complete_emulated_msr = svm_complete_emulated_msr,
4535
4536 .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4537 };
4538
4539 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4540 .cpu_has_kvm_support = has_svm,
4541 .disabled_by_bios = is_disabled,
4542 .hardware_setup = svm_hardware_setup,
4543 .check_processor_compatibility = svm_check_processor_compat,
4544
4545 .runtime_ops = &svm_x86_ops,
4546 };
4547
4548 static int __init svm_init(void)
4549 {
4550 __unused_size_checks();
4551
4552 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4553 __alignof__(struct vcpu_svm), THIS_MODULE);
4554 }
4555
4556 static void __exit svm_exit(void)
4557 {
4558 kvm_exit();
4559 }
4560
4561 module_init(svm_init)
4562 module_exit(svm_exit)
Linux with added FPC-III support