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WIP FPC-III support
[linux/fpc-iii.git] / drivers / clk / clk-litex.c
blob2e1f89d795b5e05854f4087fc0d5eb643938cd9c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2020 Antmicro Ltd. <www.antmicro.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.
8 */
9 #include "clk-litex.h"
10 #include <linux/litex.h>
11 #include <linux/platform_device.h>
12 #include <linux/module.h>
13 #include <linux/clk-provider.h>
14 #include <linux/delay.h>
15
16 struct litex_drp_reg {
17 u32 offset;
18 u32 size;
19 };
20
21 struct litex_drp_reg drp[] = {
22 {DRP_OF_RESET, DRP_SIZE_RESET},
23 {DRP_OF_READ, DRP_SIZE_READ},
24 {DRP_OF_WRITE, DRP_SIZE_WRITE},
25 {DRP_OF_DRDY, DRP_SIZE_DRDY},
26 {DRP_OF_ADR, DRP_SIZE_ADR},
27 {DRP_OF_DAT_W, DRP_SIZE_DAT_W},
28 {DRP_OF_DAT_R, DRP_SIZE_DAT_R},
29 {DRP_OF_LOCKED, DRP_SIZE_LOCKED},
30 };
31
32 struct litex_clk_device {
33 void __iomem *base;
34 int is_clkout;
35 struct clk_hw clk_hw;
36 struct litex_clk_clkout *clkouts;
37 u32 nclkout;
38 u32 lock_timeout;
39 u32 drdy_timeout;
40 u32 sys_clk_freq;
41 };
42
43 struct litex_clk_clkout_addr {
44 u8 reg1;
45 u8 reg2;
46 };
47
48 struct litex_clk_regs_addr {
49 struct litex_clk_clkout_addr clkout[CLKOUT_MAX];
50 };
51
52 struct litex_clk_clkout {
53 void __iomem *base;
54 int is_clkout;
55 struct clk_hw clk_hw;
56 u32 id;
57 u32 default_freq;
58 u32 default_phase;
59 u32 default_duty_num;
60 u32 default_duty_den;
61 u32 lock_timeout;
62 u32 drdy_timeout;
63 u32 sys_clk_freq;
64 };
65
66 struct litex_clk_regs_addr litex_clk_regs_addr_init(void)
67 {
68 struct litex_clk_regs_addr m;
69 u32 i, addr;
70
71 addr = CLKOUT0_REG1;
72 for (i = 0; i <= CLKOUT_MAX; i++) {
73 if (i == 5) {
74 /*
75 *special case because CLKOUT5 have its reg addresses
76 *placed lower than other CLKOUTs
77 */
78 m.clkout[5].reg1 = CLKOUT5_REG1;
79 m.clkout[5].reg2 = CLKOUT5_REG2;
80 } else {
81 m.clkout[i].reg1 = addr;
82 addr++;
83 m.clkout[i].reg2 = addr;
84 addr++;
85 }
86 }
87 return m;
88 }
89
90 /*
91 * This code is taken from:
92 * https://github.com/torvalds/linux/blob/master/drivers/clk/clk-axi-clkgen.c
93 *
94 * Copyright 2012-2013 Analog Devices Inc.
95 * Author: Lars-Peter Clausen <lars@metafoo.de>
96 *
97 * FIXME: make this code common
98 */
99
100 /* MMCM loop filter lookup table */
101 static u32 litex_clk_lookup_filter(u32 glob_mul)
102 {
103 switch (glob_mul) {
104 case 0:
105 return 0x01001990;
106 case 1:
107 return 0x01001190;
108 case 2:
109 return 0x01009890;
110 case 3:
111 return 0x01001890;
112 case 4:
113 return 0x01008890;
114 case 5 ... 8:
115 return 0x01009090;
116 case 9 ... 11:
117 return 0x01000890;
118 case 12:
119 return 0x08009090;
120 case 13 ... 22:
121 return 0x01001090;
122 case 23 ... 36:
123 return 0x01008090;
124 case 37 ... 46:
125 return 0x08001090;
126 default:
127 return 0x08008090;
128 }
129 }
130
131 /* MMCM lock detection lookup table */
132 static const u32 litex_clk_lock_table[] = {
133 0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
134 0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
135 0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
136 0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
137 0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
138 0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
139 0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
140 0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
141 0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
142 };
143
144 /* Helper function for lock lookup table */
145 static u32 litex_clk_lookup_lock(u32 glob_mul)
146 {
147 if (glob_mul < ARRAY_SIZE(litex_clk_lock_table))
148 return litex_clk_lock_table[glob_mul];
149 return 0x1f1f00fa;
150 }
151 /* End of copied code */
152
153 static inline struct litex_clk_device *clk_hw_to_litex_clk_device
154 (struct clk_hw *clk_hw)
155 {
156 return container_of(clk_hw, struct litex_clk_device, clk_hw);
157 }
158
159 static inline struct litex_clk_clkout *clk_hw_to_litex_clk_clkout
160 (struct clk_hw *clk_hw)
161 {
162 return container_of(clk_hw, struct litex_clk_clkout, clk_hw);
163 }
164
165 /* Clock control driver functions */
166 static inline void litex_clk_set_reg(struct clk_hw *clk_hw, u32 reg, u32 val)
167 {
168 struct litex_clk_clkout *l_clk = clk_hw_to_litex_clk_clkout(clk_hw);
169
170 _litex_set_reg(l_clk->base + drp[reg].offset, drp[reg].size, val);
171 }
172
173 static inline u32 litex_clk_get_reg(struct clk_hw *clk_hw, u32 reg)
174 {
175 struct litex_clk_clkout *l_clk = clk_hw_to_litex_clk_clkout(clk_hw);
176
177 return _litex_get_reg(l_clk->base + drp[reg].offset, drp[reg].size);
178 }
179
180 static inline void litex_clk_assert_reg(struct clk_hw *clk_hw, u32 reg)
181 {
182 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1;
183
184 litex_clk_set_reg(clk_hw, reg, assert);
185 }
186
187 static inline void litex_clk_deassert_reg(struct clk_hw *clk_hw, u32 reg)
188 {
189 litex_clk_set_reg(clk_hw, reg, ZERO_REG);
190 }
191
192 static int litex_clk_wait_lock(struct clk_hw *clk_hw)
193 {
194 struct litex_clk_clkout *l_clk;
195 u32 timeout;
196
197 l_clk = clk_hw_to_litex_clk_clkout(clk_hw);
198
199 /* Check if clk_hw is global or clkout specific */
200 if (l_clk->is_clkout) {
201 timeout = l_clk->lock_timeout;
202 } else {
203 /* clk hw is global */
204 struct litex_clk_device *l_dev;
205
206 l_dev = clk_hw_to_litex_clk_device(clk_hw);
207 timeout = l_dev->lock_timeout;
208 }
209
210 /*Waiting for LOCK signal to assert in MMCM*/
211 while (!litex_clk_get_reg(clk_hw, DRP_LOCKED) && timeout) {
212 timeout--;
213 usleep_range(900, 1000);
214 }
215 if (timeout == 0) {
216 pr_err("CLKOUT%d: %s timeout", l_clk->id, __func__);
217 return -ETIME;
218 }
219 return 0;
220 }
221
222 static int litex_clk_wait_drdy(struct clk_hw *clk_hw)
223 {
224 struct litex_clk_clkout *l_clk;
225 u32 timeout;
226
227 l_clk = clk_hw_to_litex_clk_clkout(clk_hw);
228
229 /* Check if clk_hw is global or clkout specific */
230 if (l_clk->is_clkout) {
231 timeout = l_clk->drdy_timeout;
232 } else {
233 /* clk hw is global */
234 struct litex_clk_device *l_dev;
235
236 l_dev = clk_hw_to_litex_clk_device(clk_hw);
237 timeout = l_dev->drdy_timeout;
238 }
239
240 /*Waiting for DRDY signal to assert in MMCM*/
241 while (!litex_clk_get_reg(clk_hw, DRP_DRDY) && timeout) {
242 timeout--;
243 usleep_range(900, 1000);
244 }
245 if (timeout == 0) {
246 pr_err("CLKOUT%d: %s timeout", l_clk->id, __func__);
247 return -ETIME;
248 }
249 return 0;
250 }
251
252 /* Read value written in given internal MMCM register*/
253 static int litex_clk_get_DO(struct clk_hw *clk_hw, u8 clk_reg_addr, u16 *res)
254 {
255 int ret;
256
257 litex_clk_set_reg(clk_hw, DRP_ADR, clk_reg_addr);
258 litex_clk_assert_reg(clk_hw, DRP_READ);
259
260 litex_clk_deassert_reg(clk_hw, DRP_READ);
261 ret = litex_clk_wait_drdy(clk_hw);
262 if (ret != 0)
263 return ret;
264
265 *res = litex_clk_get_reg(clk_hw, DRP_DAT_R);
266
267 return 0;
268 }
269
270 /* Return global divider and multiplier values */
271 static int litex_clk_get_global_divider(struct clk_hw *hw, u32 *divider,
272 u32 *multiplier)
273 {
274 int ret;
275 u16 divreg, mult;
276 u8 low_time, high_time;
277
278 ret = litex_clk_get_DO(hw, CLKFBOUT_REG1, &mult);
279 if (ret != 0)
280 return ret;
281 ret = litex_clk_get_DO(hw, DIV_REG, &divreg);
282 if (ret != 0)
283 return ret;
284
285 low_time = mult & HL_TIME_MASK;
286 high_time = (mult >> HIGH_TIME_POS) & HL_TIME_MASK;
287 *multiplier = low_time + high_time;
288
289 low_time = divreg & HL_TIME_MASK;
290 high_time = (divreg >> HIGH_TIME_POS) & HL_TIME_MASK;
291 *divider = low_time + high_time;
292
293 return 0;
294 }
295
296 /* Calculate frequency after global divider and multiplier */
297 static u32 litex_clk_get_real_global_frequency(struct clk_hw *hw)
298 {
299 struct litex_clk_clkout *l_clkout = clk_hw_to_litex_clk_clkout(hw);
300 u32 g_divider, g_multiplier;
301
302 litex_clk_get_global_divider(hw, &g_divider, &g_multiplier);
303 return l_clkout->sys_clk_freq * g_multiplier / g_divider;
304 }
305
306 /* Calculate frequency after global divider and multiplier without clk_hw */
307 static u32 litex_clk_get_expctd_global_frequency(u32 sys_clk_freq)
308 {
309 u32 g_divider, g_multiplier;
310
311 g_divider = (GLOB_DIV_VAL & HL_TIME_MASK) +
312 ((GLOB_DIV_VAL >> HIGH_TIME_POS) & HL_TIME_MASK);
313
314 g_multiplier = (GLOB_MUL_VAL & HL_TIME_MASK) +
315 ((GLOB_MUL_VAL >> HIGH_TIME_POS) & HL_TIME_MASK);
316
317 return sys_clk_freq * g_multiplier / g_divider;
318 }
319 /* Return dividers of given CLKOUT */
320 static int litex_clk_get_clkout_divider(struct clk_hw *hw, u32 *divider,
321 u32 *fract_cnt)
322 {
323 struct litex_clk_clkout *l_clkout = clk_hw_to_litex_clk_clkout(hw);
324 struct litex_clk_regs_addr drp_addr = litex_clk_regs_addr_init();
325 int ret;
326 u16 div, frac;
327 u8 clkout_nr = l_clkout->id;
328 u8 low_time, high_time;
329
330 ret = litex_clk_get_DO(hw, drp_addr.clkout[clkout_nr].reg1, &div);
331 if (ret != 0)
332 return ret;
333 ret = litex_clk_get_DO(hw, drp_addr.clkout[clkout_nr].reg2, &frac);
334 if (ret != 0)
335 return ret;
336
337 low_time = div & HL_TIME_MASK;
338 high_time = (div >> HIGH_TIME_POS) & HL_TIME_MASK;
339 *divider = low_time + high_time;
340 *fract_cnt = (frac >> FRAC_POS) & FRAC_MASK;
341
342 return 0;
343 }
344
345 /* Debug functions */
346 #ifdef DEBUG
347 static void litex_clk_print_general_regs(struct clk_hw *clk_hw)
348 {
349 u16 power_reg, div_reg, clkfbout_reg, lock_reg1,
350 lock_reg2, lock_reg3, filt_reg1, filt_reg2;
351
352 litex_clk_get_DO(clk_hw, POWER_REG, &power_reg);
353 litex_clk_get_DO(clk_hw, DIV_REG, &div_reg);
354 litex_clk_get_DO(clk_hw, CLKFBOUT_REG1, &clkfbout_reg);
355 litex_clk_get_DO(clk_hw, LOCK_REG1, &lock_reg1);
356 litex_clk_get_DO(clk_hw, LOCK_REG2, &lock_reg2);
357 litex_clk_get_DO(clk_hw, LOCK_REG3, &lock_reg3);
358 litex_clk_get_DO(clk_hw, FILT_REG1, &filt_reg1);
359 litex_clk_get_DO(clk_hw, FILT_REG2, &filt_reg2);
360
361 pr_debug("POWER REG: 0x%x\n", power_reg);
362 pr_debug("DIV REG: 0x%x\n", div_reg);
363 pr_debug("MUL REG: 0x%x\n", clkfbout_reg);
364 pr_debug("LOCK_REG1: 0x%x\n", lock_reg1);
365 pr_debug("LOCK_REG2: 0x%x\n", lock_reg2);
366 pr_debug("LOCK_REG3: 0x%x\n", lock_reg3);
367 pr_debug("FILT_REG1: 0x%x\n", filt_reg1);
368 pr_debug("FILT_REG2: 0x%x\n", filt_reg2);
369 }
370
371 static void litex_clk_print_clkout_regs(struct clk_hw *clk_hw, u8 clkout,
372 u8 reg1, u8 reg2)
373 {
374 u16 clkout_reg1, clkout_reg2;
375
376 litex_clk_get_DO(clk_hw, reg1, &clkout_reg1);
377 pr_debug("CLKOUT%d REG1: 0x%x\n", clkout, clkout_reg1);
378
379 litex_clk_get_DO(clk_hw, reg1, &clkout_reg2);
380 pr_debug("CLKOUT%d REG2: 0x%x\n", clkout, clkout_reg2);
381 }
382
383 static void litex_clk_print_all_regs(struct clk_hw *clk_hw)
384 {
385 struct litex_clk_regs_addr drp_addr = litex_clk_regs_addr_init();
386 u32 i;
387
388 pr_debug("General regs:\n");
389 litex_clk_print_general_regs(clk_hw);
390 for (i = 0; i < CLKOUT_MAX; i++)
391 litex_clk_print_clkout_regs(clk_hw, i, drp_addr.clkout[i].reg1,
392 drp_addr.clkout[i].reg2);
393 }
394 #endif /* #ifdef DEBUG */
395
396 /* Return raw value ready to be written into DRP */
397 static inline u16 litex_clk_calc_DI(u16 DO_val, u16 mask, u16 bitset)
398 {
399 u16 DI_val;
400
401 DI_val = DO_val & mask;
402 DI_val |= bitset;
403
404 return DI_val;
405 }
406
407 /* Sets calculated DI value into DI DRP register */
408 static int litex_clk_set_DI(struct clk_hw *clk_hw, u16 DI_val)
409 {
410 int ret;
411
412 litex_clk_set_reg(clk_hw, DRP_DAT_W, DI_val);
413 litex_clk_assert_reg(clk_hw, DRP_WRITE);
414 litex_clk_deassert_reg(clk_hw, DRP_WRITE);
415 ret = litex_clk_wait_drdy(clk_hw);
416 if (ret != 0)
417 return ret;
418 return 0;
419 }
420
421 /*
422 * Change register value as specified in arguments
423 *
424 * clk_hw: hardware specific clock structure for selecting CLKOUT
425 * mask: preserve or zero MMCM register bits
426 * by selecting 1 or 0 on desired specific mask positions
427 * bitset: set those bits in MMCM register which are 1 in bitset
428 * clk_reg_addr: internal MMCM address of control register
429 *
430 */
431 static int litex_clk_change_value(struct clk_hw *clk_hw, u16 mask, u16 bitset,
432 u8 clk_reg_addr)
433 {
434 u16 DO_val, DI_val;
435 int ret;
436
437 litex_clk_assert_reg(clk_hw, DRP_RESET);
438
439 ret = litex_clk_get_DO(clk_hw, clk_reg_addr, &DO_val);
440 if (ret != 0)
441 return ret;
442 DI_val = litex_clk_calc_DI(DO_val, mask, bitset);
443 ret = litex_clk_set_DI(clk_hw, DI_val);
444 if (ret != 0)
445 return ret;
446 #ifdef DEBUG
447 DI_val = litex_clk_get_reg(clk_hw, DRP_DAT_W);
448 #endif
449 litex_clk_deassert_reg(clk_hw, DRP_DAT_W);
450 litex_clk_deassert_reg(clk_hw, DRP_RESET);
451 ret = litex_clk_wait_lock(clk_hw);
452 if (ret != 0)
453 return ret;
454
455 pr_debug("set 0x%x under addr: 0x%x", DI_val, clk_reg_addr);
456 return 0;
457 }
458
459 /*
460 * Set register values for given CLKOUT
461 *
462 * clk_hw: hardware specific clock structure for selecting CLKOUT
463 * clkout_nr: clock output number
464 * mask_regX: preserve or zero MMCM register X bits
465 * by selecting 1 or 0 on desired specific mask positions
466 * bitset_regX: set those bits in MMCM register X which are 1 in bitset
467 *
468 */
469 static int litex_clk_set_clock(struct clk_hw *clk_hw, u8 clkout_nr,
470 u16 mask_reg1, u16 bitset_reg1,
471 u16 mask_reg2, u16 bitset_reg2)
472 {
473 struct litex_clk_regs_addr drp_addr = litex_clk_regs_addr_init();
474 int ret;
475
476 if (!(mask_reg2 == KEEP_REG_16 && bitset_reg2 == ZERO_REG)) {
477 ret = litex_clk_change_value(clk_hw, mask_reg2, bitset_reg2,
478 drp_addr.clkout[clkout_nr].reg2);
479 if (ret != 0)
480 return ret;
481 }
482 if (!(mask_reg1 == KEEP_REG_16 && bitset_reg1 == ZERO_REG)) {
483 ret = litex_clk_change_value(clk_hw, mask_reg1, bitset_reg1,
484 drp_addr.clkout[clkout_nr].reg1);
485 if (ret != 0)
486 return ret;
487 }
488 return 0;
489 }
490
491 /*
492 * Set global divider for all CLKOUTs
493 *
494 * clk_hw: hardware specific clock structure
495 * mask: preserve or zero MMCM register bits
496 * by selecting 1 or 0 on desired specific mask positions
497 * bitset: set those bits in MMCM register which are 1 in bitset
498 *
499 */
500 static int litex_clk_set_divreg(struct clk_hw *clk_hw, u16 mask, u16 bitset)
501 {
502 int ret;
503
504 ret = litex_clk_change_value(clk_hw, mask, bitset, DIV_REG);
505 if (ret != 0)
506 return ret;
507 pr_debug("Global divider set to %d", (bitset % (1 << HIGH_TIME_POS)) +
508 ((bitset >> HIGH_TIME_POS) % (1 << HIGH_TIME_POS)));
509 return 0;
510 }
511
512 /*
513 * Set global multiplier for all CLKOUTs
514 *
515 * clk_hw: hardware specific clock structure
516 * mask: preserve or zero MMCM register bits
517 * by selecting 1 or 0 on desired specific mask positions
518 * bitset: set those bits in MMCM register which are 1 in bitset
519 *
520 */
521 static int litex_clk_set_mulreg(struct clk_hw *clk_hw, u16 mask, u16 bitset)
522 {
523 int ret;
524
525 ret = litex_clk_change_value(clk_hw, mask, bitset, CLKFBOUT_REG1);
526 if (ret != 0)
527 return ret;
528 pr_debug("Global multiplier set to %d",
529 (bitset % (1 << HIGH_TIME_POS)) + ((bitset >> HIGH_TIME_POS) %
530 (1 << HIGH_TIME_POS)));
531 return 0;
532 }
533
534 static int litex_clk_set_filt(struct clk_hw *hw)
535 {
536 u32 filt, mul;
537 int ret;
538
539 mul = GLOB_MUL_VAL && HL_TIME_MASK;
540 mul += (GLOB_MUL_VAL >> HIGH_TIME_POS) && HL_TIME_MASK;
541
542 filt = litex_clk_lookup_filter(mul - 1);
543
544 ret = litex_clk_change_value(hw, FILT_MASK, filt >> 16, FILT_REG1);
545 if (ret != 0)
546 return ret;
547 ret = litex_clk_change_value(hw, FILT_MASK, filt, FILT_REG2);
548 if (ret != 0)
549 return ret;
550 return 0;
551 }
552
553 static int litex_clk_set_lock(struct clk_hw *hw)
554 {
555 u32 lock, mul;
556 int ret;
557
558 mul = GLOB_MUL_VAL && HL_TIME_MASK;
559 mul += (GLOB_MUL_VAL >> HIGH_TIME_POS) && HL_TIME_MASK;
560
561 lock = litex_clk_lookup_lock(mul - 1);
562
563 ret = litex_clk_change_value(hw, LOCK1_MASK, lock & 0x3ff, LOCK_REG1);
564 if (ret != 0)
565 return ret;
566 ret = litex_clk_change_value(hw, LOCK23_MASK,
567 (((lock >> 16) & 0x1f) << 10) | 0x1, LOCK_REG2);
568 if (ret != 0)
569 return ret;
570 ret = litex_clk_change_value(hw, LOCK23_MASK,
571 (((lock >> 24) & 0x1f) << 10) | 0x3e9, LOCK_REG3);
572 if (ret != 0)
573 return ret;
574 return 0;
575 }
576
577 /*
578 * Load default global divider and multiplier values
579 *
580 */
581 static int litex_clk_set_dm(struct clk_hw *clk_hw)
582 {
583 int ret;
584
585 ret = litex_clk_set_divreg(clk_hw, KEEP_IN_DIV, GLOB_DIV_VAL);
586 if (ret != 0)
587 return ret;
588 ret = litex_clk_set_mulreg(clk_hw, KEEP_IN_MUL, GLOB_MUL_VAL);
589 if (ret != 0)
590 return ret;
591 ret = litex_clk_set_filt(clk_hw);
592 if (ret != 0)
593 return ret;
594 ret = litex_clk_set_lock(clk_hw);
595 if (ret != 0)
596 return ret;
597 return 0;
598 }
599
600 /* Round scaled value*/
601 static inline u32 litex_round(u32 val, u32 mod)
602 {
603 if (val % mod > mod / 2)
604 return val / mod + 1;
605 else
606 return val / mod;
607 }
608
609 /*
610 * Duty Cycle
611 */
612
613 /*
614 * Calculate necessary values for setting duty cycle in fractional mode
615 *
616 * divider: frequency divider value for calculating the phase
617 * high_duty: desired duty cycle in percent
618 * fract_cnt: fractional frequency divider value, if not for
619 * CLKOUT0 - set 0
620 * pointers: function return values, used for setting desired duty
621 *
622 * This function is based on Xilinx Unified Simulation Library Component
623 * Advanced Mixed Mode Clock Manager (MMCM) taken from Xilinx Vivado
624 * found in: <Vivado-dir>/data/verilog/src/unisims/MMCME2_ADV.v
625 *
626 */
627 static int litex_clk_calc_duty_fract(int divider, int high_duty, int fract_cnt,
628 u8 *edge, u8 *high_time, u8 *low_time,
629 u8 *frac_wf_r, u8 *frac_wf_f)
630 {
631 int even_part_high, even_part_low, odd, odd_and_frac;
632
633 /* divider / 2 */
634 even_part_high = divider >> 1;
635 even_part_low = even_part_high;
636 odd = divider - even_part_high - even_part_low;
637 odd_and_frac = (8 * odd) + fract_cnt;
638
639 *low_time = even_part_high;
640 if (odd_and_frac <= ODD_AND_FRAC)
641 (*low_time)--;
642
643 *high_time = even_part_low;
644 if (odd_and_frac <= EVEN_AND_FRAC)
645 (*high_time)--;
646
647 *edge = divider % 2;
648
649 if (((odd_and_frac >= 2) && (odd_and_frac <= ODD_AND_FRAC)) ||
650 ((fract_cnt == 1) && (divider == 2)))
651 *frac_wf_f = 1;
652 else
653 *frac_wf_f = 0;
654
655 if ((odd_and_frac >= 1) && (odd_and_frac <= EVEN_AND_FRAC))
656 *frac_wf_r = 1;
657 else
658 *frac_wf_r = 0;
659
660 return 0;
661 }
662 /* End of Vivado based code */
663
664 /*
665 * Calculate necessary values for setting duty cycle in normal mode
666 *
667 * divider: frequency divider value for calculating the phase
668 * high_duty: desired duty cycle in percent
669 * pointers: function return values, used for setting desired duty
670 *
671 */
672 static int litex_clk_calc_duty_normal(int divider, int high_duty, u8 *edge,
673 u8 *high_time, u8 *low_time,
674 u8 *frac_wf_r, u8 *frac_wf_f)
675 {
676 int synthetic_duty, delta_d, min_d;
677 u32 high_time_it, ht_aprox, edge_it;
678
679 min_d = INT_MAX;
680 /* check if duty is available to set */
681 ht_aprox = high_duty * divider;
682 if (ht_aprox > ((HIGH_LOW_TIME_REG_MAX * 100) + 50) ||
683 (divider * 100) - ht_aprox >
684 ((HIGH_LOW_TIME_REG_MAX * 100) + 50))
685 return -EINVAL;
686
687 /* to prevent high_time == 0 or low_time == 0 */
688 for (high_time_it = 1; high_time_it < divider; high_time_it++) {
689 for (edge_it = 0; edge_it < 2; edge_it++) {
690 synthetic_duty = (high_time_it * 100 + 50 * edge_it) /
691 divider;
692 delta_d = abs(synthetic_duty - high_duty);
693 /* check if low_time won't be above acceptable range */
694 if (delta_d < min_d && (divider - high_time_it) <=
695 HIGH_LOW_TIME_REG_MAX) {
696 min_d = delta_d;
697 *high_time = high_time_it;
698 *low_time = divider - *high_time;
699 *edge = edge_it;
700 }
701 }
702 }
703 /*
704 * Calculating values in normal mode,
705 * clear control bits of fractional part
706 */
707
708 *frac_wf_f = 0;
709 *frac_wf_r = 0;
710
711 return 0;
712 }
713
714 /* Calculates duty cycle for given ratio in percent, 1% accuracy */
715 static inline int litex_clk_calc_duty_percent(struct clk_hw *hw,
716 struct clk_duty *duty)
717 {
718 u32 div, duty_ratio, ht;
719
720 ht = duty->num;
721 div = duty->den;
722 duty_ratio = ht * 10000 / div;
723
724 return litex_round(duty_ratio, 100);
725 }
726
727 /* Calculates duty high_time for given divider and ratio */
728 static inline int litex_clk_calc_duty_high_time(struct clk_hw *hw,
729 struct clk_duty *duty,
730 u32 divider)
731 {
732 u32 high_duty;
733
734 high_duty = litex_clk_calc_duty_percent(hw, duty) * divider;
735
736 return litex_round(high_duty, 100);
737 }
738
739 /* Returns accurate duty ratio of given clkout*/
740 int litex_clk_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
741 {
742 struct litex_clk_clkout *l_clkout = clk_hw_to_litex_clk_clkout(hw);
743 struct litex_clk_regs_addr drp_addr = litex_clk_regs_addr_init();
744 int ret;
745 u32 divider;
746 u16 clkout_reg1, clkout_reg2;
747 u8 clkout_nr, high_time, edge, no_cnt, frac_en, frac_cnt;
748
749 clkout_nr = l_clkout->id;
750 /* Check if divider is off */
751 ret = litex_clk_get_DO(hw, drp_addr.clkout[clkout_nr].reg2,
752 &clkout_reg2);
753 if (ret != 0)
754 return ret;
755 edge = (clkout_reg2 >> EDGE_POS) & EDGE_MASK;
756 no_cnt = (clkout_reg2 >> NO_CNT_POS) & NO_CNT_MASK;
757 frac_en = (clkout_reg2 >> FRAC_EN_POS) & FRAC_EN_MASK;
758 frac_cnt = (clkout_reg2 >> FRAC_POS) & FRAC_MASK;
759
760 /* get duty 50% when divider is off or fractional is enabled */
761 if (no_cnt || (frac_en && frac_cnt)) {
762 duty->num = 1;
763 duty->den = 2;
764 return 0;
765 }
766
767 ret = litex_clk_get_DO(hw, drp_addr.clkout[clkout_nr].reg1,
768 &clkout_reg1);
769 if (ret != 0)
770 return ret;
771 divider = clkout_reg1 & HL_TIME_MASK;
772 high_time = (clkout_reg1 >> HIGH_TIME_POS) & HL_TIME_MASK;
773 divider += high_time;
774
775 /* Scaling to consider edge control bit */
776 duty->num = high_time * 10 + edge * 5;
777 duty->den = (divider + edge) * 10;
778
779 return 0;
780 }
781
782 /* Set duty cycle with given ratio */
783 int litex_clk_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
784 {
785 struct litex_clk_clkout *l_clkout = clk_hw_to_litex_clk_clkout(hw);
786 u32 divider, fract_cnt, high_duty;
787 u16 bitset1, bitset2;
788 u8 frac_wf_r, frac_wf_f, frac_en, no_cnt,
789 edge, high_time, low_time, clkout_nr;
790
791 clkout_nr = l_clkout->id;
792 edge = 0, high_time = 0, low_time = 0, frac_en = 0,
793 no_cnt = 0, frac_wf_r = 0, frac_wf_f = 0;
794 high_duty = litex_clk_calc_duty_percent(hw, duty);
795
796 litex_clk_get_clkout_divider(hw, &divider, &fract_cnt);
797
798 if (fract_cnt == 0) {
799 int ret;
800
801 ret = litex_clk_calc_duty_normal(divider, high_duty, &edge,
802 &high_time, &low_time,
803 &frac_wf_r, &frac_wf_f);
804 if (ret != 0) {
805 pr_err("CLKOUT%d: cannot set %d%% duty cycle for that frequency",
806 clkout_nr, high_duty);
807 return ret;
808 }
809 } else if (high_duty == 50) {
810 return 0;
811 } else {
812 pr_err("CLKOUT%d: cannot set duty cycle when fractional divider enabled!",
813 clkout_nr);
814 return -EACCES;
815 }
816
817 bitset1 = (high_time << HIGH_TIME_POS) | low_time;
818 bitset2 = (edge << EDGE_POS);
819
820 pr_debug("SET DUTY CYCLE: divider:%d fract_cnt:%d frac_wf_r:%d frac_wf_f:%d frac_en:%d no_cnt:%d edge:%d high_time:%d low_time:%d bitset1: 0x%x bitset2: 0x%x",
821 divider, fract_cnt, frac_wf_r, frac_wf_f, frac_en,
822 no_cnt, edge, high_time, low_time, bitset1, bitset2);
823
824 return litex_clk_set_clock(hw, clkout_nr, REG1_DUTY_MASK, bitset1,
825 REG2_DUTY_MASK, bitset2);
826 }
827
828 /*
829 * Phase
830 */
831
832 /*
833 * Calculate necessary values for setting phase in fractional mode
834 *
835 * clk_hw: hardware specific clock structure
836 * divider: frequency divider value for calculating the phase
837 * fract_cnt: fractional frequency divider value, if not for
838 * CLKOUT0 - set 0
839 * phase_offset: desired phase in angle degrees
840 * pointers: function return values, used for setting desired phase
841 *
842 * This function is based on Xilinx Unified Simulation Library Component
843 * Advanced Mixed Mode Clock Manager (MMCM) taken from Xilinx Vivado
844 * found in: <Vivado-dir>/data/verilog/src/unisims/MMCME2_ADV.v
845 *
846 */
847 static int litex_clk_calc_phase_fract(struct clk_hw *hw, u32 divider,
848 u32 fract_cnt, u32 phase_offset,
849 u32 *phase_mux, u32 *delay_time,
850 u32 *phase_mux_f, u32 *period_offset)
851 {
852 int phase, dt_calc, dt,
853 a_per_in_octets, a_phase_in_cycles,
854 pm_rise_frac, pm_rise_frac_filtered,
855 pm_fall, pm_fall_frac, pm_fall_frac_filtered;
856
857 phase = phase_offset * 1000;
858 a_per_in_octets = (8 * divider) + fract_cnt;
859 a_phase_in_cycles = (phase + 10) * a_per_in_octets / 360000;
860
861 if ((a_phase_in_cycles & FULL_BYTE) != 0)
862 pm_rise_frac = (a_phase_in_cycles & PHASE_MUX_MAX);
863 else
864 pm_rise_frac = 0;
865
866 dt_calc = a_phase_in_cycles / 8;
867 dt = dt_calc & FULL_BYTE;
868
869 pm_rise_frac_filtered = pm_rise_frac;
870 if (pm_rise_frac >= 8)
871 pm_rise_frac_filtered -= 8;
872
873 pm_fall = ((divider % 2) << 2) + ((fract_cnt >> 1) & TWO_LSBITS);
874 pm_fall_frac = pm_fall + pm_rise_frac;
875 pm_fall_frac_filtered = pm_fall + pm_rise_frac -
876 (pm_fall_frac & F_FRAC_MASK);
877
878 /* keep only the lowest bits to fit in control registers bit groups */
879 *delay_time = dt % (1 << 6);
880 *phase_mux = pm_rise_frac_filtered % (1 << 3);
881 *phase_mux_f = pm_fall_frac_filtered % (1 << 3);
882
883 return 0;
884 }
885 /* End of Vivado based code */
886
887 /*
888 * Calculate necessary values for setting phase in normal mode
889 *
890 * clk_hw: hardware specific clock structure
891 * divider: frequency divider value for calculating the phase
892 * fract_cnt: fractional frequency divider value, if not for
893 * CLKOUT0 - set 0
894 * phase_offset: desired phase in angle degrees
895 * pointers: function return values, used for setting desired phase
896 *
897 */
898 static int litex_clk_calc_phase_normal(struct clk_hw *hw, u32 divider,
899 u32 fract_cnt, u32 phase_offset,
900 u32 *phase_mux, u32 *delay_time,
901 u32 *phase_mux_f, u32 *period_offset)
902 {
903 /* ns unit */
904 u32 global_period, clkout_period, post_glob_div_f;
905
906 post_glob_div_f = litex_clk_get_real_global_frequency(hw);
907 global_period = NS_IN_SEC / post_glob_div_f;
908 clkout_period = global_period * divider;
909
910 if (phase_offset != 0) {
911 int synthetic_phase, delta_p, min_p;
912 u8 d_t, p_m;
913
914 *period_offset = litex_round(clkout_period * (*period_offset),
915 10000);
916
917 if (*period_offset / global_period > DELAY_TIME_MAX)
918 return -EINVAL;
919
920 min_p = INT_MAX;
921 /* Delay_time: (0-63) */
922 for (d_t = 0; d_t <= DELAY_TIME_MAX; d_t++) {
923 /* phase_mux: (0-7) */
924 for (p_m = 0; p_m <= PHASE_MUX_MAX; p_m++) {
925 synthetic_phase = (d_t * global_period) +
926 ((p_m * ((global_period * 100) / 8) / 100));
927
928 delta_p = abs(synthetic_phase - *period_offset);
929 if (delta_p < min_p) {
930 min_p = delta_p;
931 *phase_mux = p_m;
932 *delay_time = d_t;
933 }
934 }
935 }
936 } else {
937 /* Don't change phase offset*/
938 *phase_mux = 0;
939 *delay_time = 0;
940 }
941 /* Calculating values in normal mode, fractional control bits need to be zero*/
942 *phase_mux_f = 0;
943
944 return 0;
945 }
946
947 /*
948 * Convert phase offset to positive lower than 360 deg.
949 * and calculate period in nanoseconds
950 *
951 */
952 static int litex_clk_prepare_phase(int *phase_offset, u32 *period_offset)
953 {
954 *phase_offset = *phase_offset % 360;
955
956 if (*phase_offset < 0)
957 *phase_offset += 360;
958
959 *period_offset = ((*phase_offset * 10000) / 360);
960
961 return 0;
962 }
963
964 /*
965 * Calculate necessary values for setting phase
966 *
967 * clk_hw: hardware specific clock structure
968 * divider: frequency divider value for calculating the phase
969 * fract_cnt: fractional frequency divider value, if not for
970 * CLKOUT0 - set 0
971 * clkout_nr: clock output number
972 * phase_offset: desired phase in angle degrees
973 * pointers: function return values, used for setting desired phase
974 *
975 */
976 static int litex_clk_calc_phase(struct clk_hw *clk_hw,
977 u32 divider, u32 fract_cnt,
978 u32 clkout_nr, int phase_offset,
979 u32 *phase_mux, u32 *delay_time,
980 u32 *phase_mux_f, u32 *period_offset)
981 {
982 int ret;
983
984 litex_clk_prepare_phase(&phase_offset, period_offset);
985
986 if (clkout_nr == 0 && fract_cnt > 0)
987 ret = litex_clk_calc_phase_fract(clk_hw, divider, fract_cnt,
988 phase_offset,
989 phase_mux, delay_time,
990 phase_mux_f, period_offset);
991 else
992 ret = litex_clk_calc_phase_normal(clk_hw, divider, fract_cnt,
993 phase_offset,
994 phase_mux, delay_time,
995 phase_mux_f, period_offset);
996 return ret;
997 }
998
999 /* Returns phase-specific values of given clock output */
1000 static int litex_clk_get_phase_data(struct clk_hw *hw, u8 *phase_mux,
1001 u8 *delay_time, u8 *phase_mux_f)
1002 {
1003 struct litex_clk_clkout *l_clkout = clk_hw_to_litex_clk_clkout(hw);
1004 struct litex_clk_regs_addr drp_addr = litex_clk_regs_addr_init();
1005 int ret;
1006 u16 r1, r2;
1007 u8 clkout_nr = l_clkout->id;
1008
1009 ret = litex_clk_get_DO(hw, drp_addr.clkout[clkout_nr].reg1, &r1);
1010 if (ret != 0)
1011 return ret;
1012 ret = litex_clk_get_DO(hw, drp_addr.clkout[clkout_nr].reg2, &r2);
1013 if (ret != 0)
1014 return ret;
1015 *phase_mux = (r1 >> PHASE_MUX_POS) & PHASE_MUX_MASK;
1016 *delay_time = (r2 >> DELAY_TIME_POS) & HL_TIME_MASK;
1017
1018 if (clkout_nr == 0) {
1019 ret = litex_clk_get_DO(hw, CLKOUT5_REG2, &r2);
1020 if (ret != 0)
1021 return ret;
1022 *phase_mux_f = (r2 >> PHASE_MUX_F_POS) & PHASE_MUX_F_MASK;
1023 } else {
1024 *phase_mux_f = 0;
1025 }
1026
1027 return 0;
1028 }
1029
1030 /* Returns phase of given clock output in degrees */
1031 int litex_clk_get_phase(struct clk_hw *hw)
1032 {
1033 u8 phase_mux = 0, delay_time = 0, phase_mux_f;
1034 u32 divider, fract_cnt, post_glob_div_f, pm;
1035 /* ns unit */
1036 u32 global_period, clkout_period, period;
1037
1038 litex_clk_get_phase_data(hw, &phase_mux, &delay_time, &phase_mux_f);
1039 litex_clk_get_clkout_divider(hw, &divider, &fract_cnt);
1040
1041 post_glob_div_f = litex_clk_get_real_global_frequency(hw);
1042 global_period = NS_IN_SEC / post_glob_div_f;
1043 clkout_period = global_period * divider;
1044
1045 pm = (phase_mux * global_period * 1000) / PHASE_MUX_RES_FACTOR;
1046 pm = litex_round(pm, 1000);
1047
1048 period = delay_time * global_period + pm;
1049
1050 period = period * 1000 / clkout_period;
1051 period = period * 360;
1052
1053 return litex_round(period, 1000);
1054 }
1055
1056 /* Sets phase given in degrees on given clock output */
1057 int litex_clk_set_phase(struct clk_hw *hw, int degrees)
1058 {
1059 struct litex_clk_clkout *l_clkout = clk_hw_to_litex_clk_clkout(hw);
1060 u32 phase_mux, divider, fract_cnt,
1061 phase_mux_f, delay_time, period_offset;
1062 u16 bitset1, bitset2, reg2_mask;
1063 u8 clkout_nr, edge, high_time, low_time, frac_wf_r, frac_wf_f;
1064 int ret;
1065
1066 reg2_mask = REG2_PHASE_MASK;
1067 phase_mux = 0;
1068 delay_time = 0;
1069 clkout_nr = l_clkout->id;
1070 litex_clk_get_clkout_divider(hw, &divider, &fract_cnt);
1071 if (fract_cnt > 0 && degrees != 0) {
1072 pr_err("CLKOUT%d: cannot set phase on that frequency",
1073 clkout_nr);
1074 return -ENOSYS;
1075 }
1076 ret = litex_clk_calc_phase(hw, divider, fract_cnt, clkout_nr, degrees,
1077 &phase_mux, &delay_time,
1078 &phase_mux_f, &period_offset);
1079 if (ret != 0) {
1080 pr_err("CLKOUT%d: phase offset %d deg is too high for given frequency",
1081 clkout_nr, degrees);
1082 return ret;
1083 }
1084
1085 bitset1 = (phase_mux << PHASE_MUX_POS);
1086 bitset2 = (delay_time << DELAY_TIME_POS);
1087
1088 if (clkout_nr == 0 && fract_cnt > 0) {
1089 u16 clkout5_reg2_bitset;
1090
1091 litex_clk_calc_duty_fract(divider, 50, fract_cnt,
1092 &edge, &high_time, &low_time,
1093 &frac_wf_r, &frac_wf_f);
1094 bitset2 |= (fract_cnt << FRAC_POS) |
1095 (1 << FRAC_EN_POS) |
1096 (frac_wf_r << FRAC_WF_R_POS);
1097
1098 clkout5_reg2_bitset = (phase_mux_f << PHASE_MUX_F_POS) |
1099 (frac_wf_f << FRAC_WF_F_POS);
1100
1101 ret = litex_clk_change_value(hw, CLKOUT5_FRAC_MASK,
1102 clkout5_reg2_bitset,
1103 CLKOUT5_REG2);
1104 if (ret != 0)
1105 return ret;
1106 reg2_mask = REG2_PHASE_F_MASK;
1107 }
1108
1109 pr_debug("SET PHASE: phase_mux:%d phase_mux_f:%d delay_time:%d bitset1: 0x%x bitset2: 0x%x",
1110 phase_mux, phase_mux_f, delay_time, bitset1, bitset2);
1111
1112 return litex_clk_set_clock(hw, clkout_nr, REG1_PHASE_MASK, bitset1,
1113 reg2_mask, bitset2);
1114 }
1115
1116 /*
1117 * Frequency
1118 */
1119
1120 /*
1121 * Calculate necessary values for setting frequency in fractional mode
1122 *
1123 * clk_hw: hardware specific clock structure
1124 * freq: desired frequency in Hz
1125 * pointers: function return values, used for setting
1126 * desired frequency
1127 */
1128 static int litex_clk_calc_freq_fract(struct clk_hw *clk_hw, u32 freq,
1129 u32 *divider, u8 *frac_en,
1130 u8 *no_cnt, u32 *fract_cnt)
1131 {
1132 int delta_f, synthetic_freq, min_f;
1133 u32 post_glob_div_f, div, f_cnt, fract;
1134
1135 post_glob_div_f = litex_clk_get_real_global_frequency(clk_hw);
1136
1137 delta_f = 0;
1138 synthetic_freq = post_glob_div_f;
1139 min_f = abs(synthetic_freq - freq);
1140 *divider = 1;
1141 /* div is integer divider * 1000 to keep precision */
1142 for (div = MIN_DIVIDER_F; div <= MAX_DIVIDER_F; div += 1000) {
1143 /*
1144 * f_cnt is fractional part of divider * 1000 incremented
1145 * by minimal fractional divider step to keep precision
1146 * and find best divider
1147 */
1148 for (f_cnt = 0, fract = 0; fract < 1000;
1149 fract += FRACT_DIV_RES, f_cnt++) {
1150
1151 synthetic_freq = (post_glob_div_f / (div + fract)) *
1152 1000;
1153 delta_f = abs(synthetic_freq - freq);
1154
1155 if (delta_f < min_f) {
1156 min_f = delta_f;
1157 *divider = div / 1000;
1158 *fract_cnt = f_cnt;
1159 }
1160 }
1161 }
1162 if (*fract_cnt == 0) {
1163 *frac_en = 0;
1164 if (*divider == 1)
1165 *no_cnt = 1;
1166 else
1167 *no_cnt = 0;
1168 } else {
1169 *frac_en = 1;
1170 *no_cnt = 0;
1171 }
1172
1173 return 0;
1174 }
1175
1176 /*
1177 * Calculate necessary values for setting frequency in normal mode
1178 *
1179 * clk_hw: hardware specific clock structure
1180 * freq: desired frequency in Hz
1181 * pointers: function return values, used for setting
1182 * desired frequency
1183 *
1184 */
1185 static int litex_clk_calc_freq_normal(struct clk_hw *clk_hw, u32 freq,
1186 u32 *divider, u8 *frac_en,
1187 u8 *no_cnt, u32 *fract_cnt)
1188 {
1189 int delta_f, synthetic_freq, min_f;
1190 u32 post_glob_div_f, div;
1191
1192 post_glob_div_f = litex_clk_get_real_global_frequency(clk_hw);
1193 synthetic_freq = post_glob_div_f;
1194 min_f = abs(synthetic_freq - freq);
1195 *divider = 1;
1196 delta_f = 0;
1197
1198 for (div = MIN_DIVIDER; div <= MAX_DIVIDER; div++) {
1199 synthetic_freq = post_glob_div_f / div;
1200 delta_f = abs(synthetic_freq - freq);
1201 if (delta_f < min_f) {
1202 min_f = delta_f;
1203 *divider = div;
1204 }
1205 }
1206 if (*divider == 1)
1207 *no_cnt = 1;
1208 else
1209 *no_cnt = 0;
1210
1211 *frac_en = 0;
1212 *fract_cnt = 0;
1213
1214 return 0;
1215 }
1216
1217 /* Returns rate in Hz */
1218 static inline unsigned long litex_clk_calc_rate(struct clk_hw *hw, u32 g_mul,
1219 u32 g_div, u32 div,
1220 u32 fract_cnt)
1221 {
1222 struct litex_clk_clkout *l_clkout = clk_hw_to_litex_clk_clkout(hw);
1223
1224 return (l_clkout->sys_clk_freq * g_mul /
1225 ((div * 1000 + (fract_cnt * FRACT_DIV_RES)) * g_div)) * 1000;
1226 }
1227
1228 /*
1229 * Calculate necessary values for setting frequency
1230 *
1231 * clk_hw: hardware specific clock structure
1232 * rate: desired frequency in Hz
1233 * clkout_nr: clock output number
1234 * pointers: function return values, used for setting
1235 * desired frequency
1236 *
1237 */
1238 static void litex_clk_calc_dividers(struct clk_hw *hw, u32 rate, u8 clkout_nr,
1239 u32 *divider, u32 *fract_cnt,
1240 u8 *frac_wf_r, u8 *frac_wf_f,
1241 u8 *frac_en, u8 *no_cnt, u8 *edge,
1242 u8 *high_time, u8 *low_time)
1243 {
1244 u32 high_duty;
1245 struct clk_duty duty;
1246
1247 litex_clk_get_duty_cycle(hw, &duty);
1248 high_duty = litex_clk_calc_duty_percent(hw, &duty);
1249
1250 if (clkout_nr == 0) {
1251 litex_clk_calc_freq_fract(hw, rate, divider, frac_en, no_cnt,
1252 fract_cnt);
1253 if (*fract_cnt > 0)
1254 litex_clk_calc_duty_fract(*divider, high_duty,
1255 *fract_cnt, edge,
1256 high_time, low_time,
1257 frac_wf_r, frac_wf_f);
1258 else
1259 litex_clk_calc_duty_normal(*divider, high_duty, edge,
1260 high_time, low_time,
1261 frac_wf_r, frac_wf_f);
1262 } else {
1263
1264 litex_clk_calc_freq_normal(hw, rate, divider, frac_en,
1265 no_cnt, fract_cnt);
1266
1267 litex_clk_calc_duty_normal(*divider, high_duty, edge,
1268 high_time, low_time,
1269 frac_wf_r, frac_wf_f);
1270 }
1271 }
1272
1273 /* Returns rate of given CLKOUT, parent_rate ignored */
1274 unsigned long litex_clk_recalc_rate(struct clk_hw *hw,
1275 unsigned long parent_rate)
1276 {
1277 u32 multiplier, divider, clkout_div, fract_cnt;
1278
1279 LITEX_UNUSED(parent_rate);
1280
1281 litex_clk_get_global_divider(hw, &divider, &multiplier);
1282 litex_clk_get_clkout_divider(hw, &clkout_div, &fract_cnt);
1283 return litex_clk_calc_rate(hw, multiplier, divider, clkout_div,
1284 fract_cnt);
1285 }
1286
1287 int litex_clk_check_rate_range(struct clk_hw *hw, unsigned long rate)
1288 {
1289 u32 f_max, f_min, gf;
1290
1291 gf = litex_clk_get_real_global_frequency(hw);
1292 f_max = gf / 2;
1293 f_min = gf / MAX_DIVIDER;
1294 /* margin of 1kHz */
1295 if ((rate > f_max + KHZ) | (rate < f_min - KHZ))
1296 return -EINVAL;
1297
1298 return 0;
1299 }
1300
1301 /* Returns closest available clock rate in Hz, parent_rate ignored */
1302 long litex_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1303 unsigned long *parent_rate)
1304 {
1305 struct litex_clk_clkout *l_clkout = clk_hw_to_litex_clk_clkout(hw);
1306 u32 divider, fract_cnt, g_divider, g_multiplier;
1307 u8 frac_wf_r, frac_wf_f, frac_en, no_cnt,
1308 edge, high_time, low_time, clkout_nr;
1309
1310 if (litex_clk_check_rate_range(hw, rate))
1311 return -EINVAL;
1312
1313 LITEX_UNUSED(parent_rate);
1314 clkout_nr = l_clkout->id;
1315
1316 litex_clk_calc_dividers(hw, rate, clkout_nr, &divider, &fract_cnt,
1317 &frac_wf_r, &frac_wf_f, &frac_en,
1318 &no_cnt, &edge, &high_time, &low_time);
1319 litex_clk_get_global_divider(hw, &g_divider, &g_multiplier);
1320
1321 return litex_clk_calc_rate(hw, g_multiplier, g_divider, divider,
1322 fract_cnt);
1323 }
1324
1325 /* Set closest available clock rate in Hz, parent_rate ignored */
1326 int litex_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1327 unsigned long parent_rate)
1328 {
1329 struct litex_clk_clkout *l_clkout = clk_hw_to_litex_clk_clkout(hw);
1330 u16 bitset1, bitset2;
1331 u32 divider, fract_cnt;
1332 u8 frac_wf_r, frac_wf_f, frac_en, no_cnt,
1333 edge, high_time, low_time, clkout_nr;
1334 int ret;
1335
1336 LITEX_UNUSED(parent_rate);
1337 clkout_nr = l_clkout->id;
1338
1339 pr_debug("set_rate: %lu", rate);
1340 if (litex_clk_check_rate_range(hw, rate)) {
1341 pr_err("CLKOUT%d: cannot set %luHz, frequency not in available range",
1342 clkout_nr, rate);
1343 return -EINVAL;
1344 }
1345
1346 litex_clk_calc_dividers(hw, rate, clkout_nr, &divider, &fract_cnt,
1347 &frac_wf_r, &frac_wf_f, &frac_en, &no_cnt,
1348 &edge, &high_time, &low_time);
1349
1350 bitset1 = (high_time << HIGH_TIME_POS) |
1351 (low_time << LOW_TIME_POS);
1352
1353 bitset2 = (fract_cnt << FRAC_POS) |
1354 (frac_en << FRAC_EN_POS) |
1355 (frac_wf_r << FRAC_WF_R_POS) |
1356 (edge << EDGE_POS) |
1357 (no_cnt << NO_CNT_POS);
1358 if (frac_en != 0) {
1359 u32 phase_mux, delay_time, phase_mux_f,
1360 phase_offset, period_offset;
1361
1362 phase_offset = 0;
1363 litex_clk_calc_phase_fract(hw, divider, fract_cnt, phase_offset,
1364 &phase_mux, &delay_time,
1365 &phase_mux_f, &period_offset);
1366
1367 bitset1 |= (phase_mux << PHASE_MUX_POS);
1368 bitset2 |= (delay_time << DELAY_TIME_POS);
1369
1370 if (frac_wf_f > 0 || phase_mux_f > 0) {
1371 u16 clkout5_reg2_bitset = 0;
1372
1373 clkout5_reg2_bitset = (phase_mux_f << PHASE_MUX_F_POS) |
1374 (frac_wf_f << FRAC_WF_F_POS);
1375
1376 ret = litex_clk_change_value(hw, CLKOUT5_FRAC_MASK,
1377 clkout5_reg2_bitset, CLKOUT5_REG2);
1378 if (ret != 0)
1379 return ret;
1380 }
1381 }
1382
1383 pr_debug("SET RATE: divider:%d fract_cnt:%d frac_wf_r:%d frac_wf_f:%d frac_en:%d no_cnt:%d edge:%d high_time:%d low_time:%d bitset1: 0x%x bitset2: 0x%x",
1384 divider, fract_cnt, frac_wf_r, frac_wf_f, frac_en,
1385 no_cnt, edge, high_time, low_time, bitset1, bitset2);
1386
1387 return litex_clk_set_clock(hw, clkout_nr, REG1_FREQ_MASK, bitset1,
1388 REG2_FREQ_MASK, bitset2);
1389 }
1390
1391 /* Prepare clock output */
1392 int litex_clk_prepare(struct clk_hw *hw)
1393 {
1394 struct litex_clk_clkout *l_clkout;
1395 struct clk_duty duty;
1396 u32 freq, phase;
1397
1398 l_clkout = clk_hw_to_litex_clk_clkout(hw);
1399 freq = l_clkout->default_freq;
1400 phase = l_clkout->default_phase;
1401 duty.num = l_clkout->default_duty_num;
1402 duty.den = l_clkout->default_duty_den;
1403
1404 litex_clk_set_rate(hw, freq, 0);
1405 litex_clk_set_duty_cycle(hw, &duty);
1406 litex_clk_set_phase(hw, phase);
1407 return 0;
1408 }
1409
1410 /* Unrepare clock output */
1411 void litex_clk_unprepare(struct clk_hw *hw)
1412 {
1413 struct clk_duty duty;
1414
1415 duty.num = 1;
1416 duty.den = 2;
1417 litex_clk_set_rate(hw, 100000000, 0);
1418 litex_clk_set_duty_cycle(hw, &duty);
1419 litex_clk_set_phase(hw, 0);
1420 }
1421
1422 /* Enable Clock Control MMCM module */
1423 int litex_clk_enable(struct clk_hw *hw)
1424 {
1425 litex_clk_assert_reg(hw, DRP_RESET);
1426 return 0;
1427 }
1428
1429 /* Disable Clock Control MMCM module */
1430 void litex_clk_disable(struct clk_hw *hw)
1431 {
1432 litex_clk_deassert_reg(hw, DRP_RESET);
1433 }
1434
1435 /* Set default clock value from device tree for given clkout*/
1436 static int litex_clk_set_def_clkout(struct clk_hw *hw, u32 freq, u32 phase,
1437 struct clk_duty *duty)
1438 {
1439 int ret;
1440
1441 ret = litex_clk_set_rate(hw, freq, 0);
1442 if (ret != 0)
1443 return ret;
1444 ret = litex_clk_set_duty_cycle(hw, duty);
1445 if (ret != 0)
1446 return ret;
1447 ret = litex_clk_set_phase(hw, phase);
1448 if (ret != 0)
1449 return ret;
1450 return 0;
1451 }
1452
1453 static const struct clk_ops litex_clk_ops = {
1454 .prepare = litex_clk_prepare,
1455 .unprepare = litex_clk_unprepare,
1456 .enable = litex_clk_enable,
1457 .disable = litex_clk_disable,
1458 .recalc_rate = litex_clk_recalc_rate,
1459 .round_rate = litex_clk_round_rate,
1460 .set_rate = litex_clk_set_rate,
1461 .get_phase = litex_clk_get_phase,
1462 .set_phase = litex_clk_set_phase,
1463 .get_duty_cycle = litex_clk_get_duty_cycle,
1464 .set_duty_cycle = litex_clk_set_duty_cycle,
1465 };
1466
1467 static const struct of_device_id litex_of_match[] = {
1468 {.compatible = "litex,clk"},
1469 {},
1470 };
1471
1472 MODULE_DEVICE_TABLE(of, litex_of_match);
1473
1474 static int litex_clk_read_clkout_dts(struct device_node *child,
1475 struct litex_clk_clkout *clkout)
1476 {
1477 int ret;
1478 u32 dt_num, dt_freq, dt_phase, dt_duty_num,
1479 dt_duty_den, f_max, f_min, gf;
1480
1481 gf = litex_clk_get_expctd_global_frequency(clkout->sys_clk_freq);
1482 f_max = gf / 2;
1483 f_min = gf / MAX_DIVIDER;
1484
1485 ret = of_property_read_u32(child, "reg", &dt_num);
1486 if (ret != 0)
1487 return -ret;
1488
1489 if (dt_num > CLKOUT_MAX) {
1490 pr_err("%s: Invalid CLKOUT index!", child->name);
1491 return -EINVAL;
1492 }
1493
1494 ret = of_property_read_u32(child, "litex,clock-frequency", &dt_freq);
1495 if (ret != 0)
1496 return -ret;
1497
1498 if (dt_freq > f_max || dt_freq < f_min) {
1499 pr_err("%s: Invalid default frequency!(%d), MIN/MAX (%d/%d)Hz",
1500 child->name, dt_freq, f_min, f_max);
1501 return -EINVAL;
1502 }
1503
1504 ret = of_property_read_u32(child, "litex,clock-phase", &dt_phase);
1505 if (ret != 0)
1506 return -ret;
1507
1508 ret = of_property_read_u32(child, "litex,clock-duty-den", &dt_duty_den);
1509 if (ret != 0)
1510 return -ret;
1511
1512 ret = of_property_read_u32(child, "litex,clock-duty-num", &dt_duty_num);
1513 if (ret != 0)
1514 return -ret;
1515
1516 if (dt_duty_den <= 0 || dt_duty_num > dt_duty_den) {
1517 pr_err("%s: Invalid default duty! %d/%d", child->name,
1518 dt_duty_num, dt_duty_den);
1519 return -EINVAL;
1520 }
1521
1522 clkout->id = dt_num;
1523 clkout->default_freq = dt_freq;
1524 clkout->default_phase = dt_phase;
1525 clkout->default_duty_num = dt_duty_num;
1526 clkout->default_duty_den = dt_duty_den;
1527
1528 return 0;
1529 }
1530
1531 static int litex_clk_get_timeouts(struct device_node *node, int *dt_lock_timeout,
1532 int *dt_drdy_timeout)
1533 {
1534 int ret;
1535
1536 /* Read wait_lock timeout from device property*/
1537 ret = of_property_read_u32(node, "litex,lock-timeout", dt_lock_timeout);
1538 if (ret < 0) {
1539 pr_err("No litex,lock_timeout entry in the dts file\n");
1540 return -ENODEV;
1541 }
1542 if (*dt_lock_timeout < 1) {
1543 pr_err("LiteX CLK driver cannot wait for time bellow ca. 1ms\n");
1544 return -EINVAL;
1545 }
1546
1547 /* Read wait_drdy timeout from device property*/
1548 ret = of_property_read_u32(node, "litex,drdy-timeout", dt_drdy_timeout);
1549 if (ret < 0) {
1550 pr_err("No litex,lock_drdy entry in the dts file\n");
1551 return -ENODEV;
1552 }
1553 if (*dt_drdy_timeout < 1) {
1554 pr_err("LiteX CLK driver cannot wait for time bellow ca. 1ms\n");
1555 return -EINVAL;
1556 }
1557
1558 return 0;
1559 }
1560
1561 static int litex_clk_init_clkouts(struct device *dev,
1562 struct device_node *node,
1563 struct litex_clk_device *l_dev)
1564 {
1565 struct device_node *child_node;
1566 struct clk_hw *hw;
1567 struct clk_duty duty;
1568 u32 dt_lock_timeout, dt_drdy_timeout;
1569 int i = 0, ret;
1570
1571 ret = litex_clk_get_timeouts(node, &dt_lock_timeout, &dt_drdy_timeout);
1572 if (ret != 0)
1573 return ret;
1574
1575 for_each_child_of_node(node, child_node) {
1576 struct litex_clk_clkout *clkout;
1577 struct clk_init_data clkout_init;
1578
1579 clkout = &l_dev->clkouts[i];
1580 clkout->is_clkout = true;
1581
1582 clkout->lock_timeout = dt_lock_timeout;
1583 clkout->drdy_timeout = dt_drdy_timeout;
1584 clkout->sys_clk_freq = l_dev->sys_clk_freq;
1585
1586 ret = litex_clk_read_clkout_dts(child_node, clkout);
1587 if (ret != 0)
1588 return ret;
1589
1590 clkout_init.name = child_node->name;
1591 clkout_init.ops = &litex_clk_ops;
1592 clkout_init.num_parents = 0;
1593 clkout_init.flags = CLK_SET_RATE_UNGATE | CLK_GET_RATE_NOCACHE;
1594 clkout->clk_hw.init = &clkout_init;
1595 clkout->base = l_dev->base;
1596
1597 duty.num = clkout->default_duty_num;
1598 duty.den = clkout->default_duty_den;
1599
1600 /* set global divider and multiplier once */
1601 if (i == 0) {
1602 hw = &l_dev->clkouts[i].clk_hw;
1603 litex_clk_enable(hw);
1604 ret = litex_clk_set_dm(hw);
1605 litex_clk_disable(hw);
1606 if (ret != 0)
1607 return ret;
1608 }
1609
1610 ret = litex_clk_set_def_clkout(&clkout->clk_hw,
1611 clkout->default_freq,
1612 clkout->default_phase, &duty);
1613 ret = devm_clk_hw_register(dev, &clkout->clk_hw);
1614 if (ret != 0) {
1615 pr_err("devm_clk_hw_register failure, %s ret: %d\n",
1616 child_node->name, ret);
1617 return ret;
1618 }
1619
1620 ret = of_clk_add_hw_provider(child_node, of_clk_hw_simple_get,
1621 &clkout->clk_hw);
1622 if (ret != 0)
1623 return ret;
1624 i++;
1625 }
1626 return 0;
1627 }
1628
1629 static int litex_clk_read_global_dts(struct device *dev,
1630 struct device_node *node,
1631 struct litex_clk_device *l_dev)
1632 {
1633 struct device_node *child_node;
1634 struct litex_clk_clkout *l_clkout;
1635 u32 dt_nclkout, dt_lock_timeout, dt_drdy_timeout, dt_sys_clk_freq;
1636 int i = 0, ret;
1637
1638 ret = of_property_read_u32(node, "litex,sys-clock-frequency",
1639 &dt_sys_clk_freq);
1640 if (ret < 0) {
1641 pr_err("No clock-frequency entry in the dts file\n");
1642 return -ENODEV;
1643 }
1644 l_dev->sys_clk_freq = dt_sys_clk_freq;
1645
1646 /* Read cnt of CLKOUTs from device property*/
1647 ret = of_property_read_u32(node, "litex,nclkout", &dt_nclkout);
1648 if (ret < 0) {
1649 pr_err("No litex,nclkout entry in the dts file\n");
1650 return -ENODEV;
1651 }
1652 if (dt_nclkout > CLKOUT_MAX) {
1653 pr_err("LiteX CLK driver cannot use more than %d clock outputs\n",
1654 CLKOUT_MAX);
1655 return -EINVAL;
1656 }
1657 l_dev->nclkout = dt_nclkout;
1658
1659 /* count existing CLKOUTs */
1660 for_each_child_of_node(node, child_node)
1661 i++;
1662 if (i != dt_nclkout) {
1663 pr_err("nclkout(%d) not matching actual CLKOUT count(%d)!",
1664 dt_nclkout, i);
1665 return -EINVAL;
1666 }
1667
1668 l_dev->clkouts = devm_kzalloc(dev, sizeof(*l_clkout) * i, GFP_KERNEL);
1669 if (!l_dev->clkouts) {
1670 pr_err("CLKOUT memory allocation failure!");
1671 return -ENOMEM;
1672 }
1673
1674 ret = litex_clk_get_timeouts(node, &dt_lock_timeout, &dt_drdy_timeout);
1675 if (ret != 0)
1676 return ret;
1677 l_dev->lock_timeout = dt_lock_timeout;
1678 l_dev->drdy_timeout = dt_drdy_timeout;
1679
1680 return 0;
1681 }
1682
1683 static int litex_clk_init_glob_clk(struct device *dev,
1684 struct device_node *node,
1685 struct litex_clk_device *l_dev)
1686 {
1687 struct clk_init_data init;
1688 struct clk_hw *hw;
1689 int ret;
1690
1691 init.name = node->name;
1692 init.ops = &litex_clk_ops;
1693 init.flags = CLK_SET_RATE_UNGATE;
1694
1695 hw = &l_dev->clk_hw;
1696 hw->init = &init;
1697
1698 ret = devm_clk_hw_register(dev, hw);
1699 if (ret != 0) {
1700 pr_err("devm_clk_hw_register failure, ret: %d\n", ret);
1701 return ret;
1702 }
1703
1704 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
1705 if (ret != 0) {
1706 pr_err("of_clk_add_hw_provider failure, ret: %d", ret);
1707 return ret;
1708 }
1709
1710 /* Power on MMCM module */
1711 ret = litex_clk_change_value(hw, FULL_REG_16, FULL_REG_16, POWER_REG);
1712 if (ret != 0) {
1713 pr_err("MMCM initialization failure, ret: %d", ret);
1714 return ret;
1715 }
1716
1717 return 0;
1718 }
1719
1720 static int litex_clk_probe(struct platform_device *pdev)
1721 {
1722 const struct of_device_id *id;
1723 struct device *dev;
1724 struct device_node *node;
1725 struct litex_clk_device *litex_clk_device;
1726 struct resource *res;
1727 int ret;
1728
1729 dev = &pdev->dev;
1730 node = dev->of_node;
1731 if (!node)
1732 return -ENODEV;
1733
1734 id = of_match_node(litex_of_match, node);
1735 if (!id)
1736 return -ENODEV;
1737
1738 litex_clk_device = devm_kzalloc(dev, sizeof(*litex_clk_device),
1739 GFP_KERNEL);
1740 if (IS_ERR_OR_NULL(litex_clk_device))
1741 return -ENOMEM;
1742 litex_clk_device->is_clkout = false;
1743
1744 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1745 if (IS_ERR_OR_NULL(res))
1746 return -EBUSY;
1747
1748 litex_clk_device->base = devm_of_iomap(dev, node, 0, &res->end);
1749 if (IS_ERR_OR_NULL(litex_clk_device->base))
1750 return -EIO;
1751
1752 ret = litex_clk_read_global_dts(dev, node, litex_clk_device);
1753 if (ret != 0)
1754 return ret;
1755
1756 ret = litex_clk_init_clkouts(dev, node, litex_clk_device);
1757 if (ret != 0)
1758 return ret;
1759
1760 ret = litex_clk_init_glob_clk(dev, node, litex_clk_device);
1761 if (ret != 0)
1762 return ret;
1763
1764 pr_info("litex clk control driver initialized");
1765 return 0;
1766 }
1767
1768 static int litex_clk_remove(struct platform_device *pdev)
1769 {
1770 of_clk_del_provider(pdev->dev.of_node);
1771 return 0;
1772 }
1773
1774 static struct platform_driver litex_clk_driver = {
1775 .driver = {
1776 .name = "litex-clk",
1777 .of_match_table = of_match_ptr(litex_of_match),
1778 },
1779 .probe = litex_clk_probe,
1780 .remove = litex_clk_remove,
1781 };
1782
1783 module_platform_driver(litex_clk_driver);
1784 MODULE_DESCRIPTION("LiteX clock driver");
1785 MODULE_AUTHOR("Antmicro <www.antmicro.com>");
1786 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support