drivers/clk/clk-litex.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 #define LITEX_UNUSED(var)         (void)(var)
   3
   4 /* Common values */
   5 #define NS_IN_SEC               1000000000
   6 #define FULL_BYTE               0xFF
   7 #define KHZ                     1000
   8
   9 /* MMCM specific numbers */
  10 #define CLKOUT_MAX              7
  11 #define DELAY_TIME_MAX          63
  12 #define PHASE_MUX_MAX           7
  13 #define HIGH_LOW_TIME_SAFE_MAX  62
  14 #define HIGH_LOW_TIME_REG_MAX   63
  15 #define MAX_DIVIDER             126
  16 #define MAX_DIVIDER_F           126000
  17 #define MIN_DIVIDER             2
  18 #define MIN_DIVIDER_F           2000
  19 #define PHASE_MUX_RES_FACTOR    8
  20 /* Fractional divider resolution multiplied by 1000 to keep precision */
  21 #define FRACT_DIV_RES           125
  22 /* Minimal value when div is odd and fract is on */
  23 #define ODD_AND_FRAC            9
  24 /* Odd div and no frac or even div and enabled fract max value */
  25 #define EVEN_AND_FRAC           8
  26
  27 /* DRP registers index */
  28 /* Additional register */
  29 #define MMCM                    0
  30 /* DRP registers */
  31 #define DRP_RESET               0
  32 #define DRP_READ                1
  33 #define DRP_WRITE               2
  34 #define DRP_DRDY                3
  35 #define DRP_ADR                 4
  36 #define DRP_DAT_W               5
  37 #define DRP_DAT_R               6
  38 #define DRP_LOCKED              7
  39
  40 /* Register space offsets */
  41 #define DRP_OF_RESET            0x0
  42 #define DRP_OF_LOCKED           0x4
  43 #define DRP_OF_READ             0x8
  44 #define DRP_OF_WRITE            0xc
  45 #define DRP_OF_DRDY             0x10
  46 #define DRP_OF_ADR              0x14
  47 #define DRP_OF_DAT_W            0x18
  48 #define DRP_OF_DAT_R            0x20
  49
  50 /* Register sizes */
  51 #define DRP_SIZE_RESET          0x1
  52 #define DRP_SIZE_READ           0x1
  53 #define DRP_SIZE_WRITE          0x1
  54 #define DRP_SIZE_DRDY           0x1
  55 #define DRP_SIZE_ADR            0x1
  56 #define DRP_SIZE_DAT_W          0x2
  57 #define DRP_SIZE_DAT_R          0x2
  58 #define DRP_SIZE_LOCKED         0x1
  59
  60 /* Register values */
  61 #define GLOB_DIV_VAL            0x41
  62 #define GLOB_MUL_VAL            0x82
  63 #define FULL_REG_16             0xFFFF
  64 #define KEEP_REG_16             FULL_REG_16
  65 #define KEEP_IN_MUL             0xF000
  66 #define KEEP_IN_DIV             0xE000
  67 #define ZERO_REG                0x0
  68 #define REG1_MASK               0x1000
  69 #define REG2_MASK               0x8000
  70 #define REG1_BITSET             0x41
  71 #define REG2_BITSET             0x40
  72 #define CLKOUT5_FRAC_MASK       0xC3FF
  73 #define CLKOUT5_FRAC_MASK_F     0xFBFF
  74 #define CLKOUT5_FRAC_MASK_P     0xC7FF
  75 #define REG1_FREQ_MASK          0xF000
  76 #define REG2_FREQ_MASK          0x803F
  77 #define REG1_DUTY_MASK          0xF000
  78 #define REG2_DUTY_MASK          0xFF7F
  79 #define REG1_PHASE_MASK         0x1FFF
  80 #define REG2_PHASE_MASK         0xFCC0
  81 #define REG2_PHASE_F_MASK       0x80C0
  82 #define FILT_MASK               0x9900
  83 #define LOCK1_MASK              0x03FF
  84 #define LOCK23_MASK             0x7FFF
  85 /* Control bits extraction masks */
  86 #define HL_TIME_MASK            0x3F
  87 #define FRAC_MASK               0x7
  88 #define EDGE_MASK               0x1
  89 #define NO_CNT_MASK             0x1
  90 #define FRAC_EN_MASK            0x1
  91 #define PHASE_MUX_MASK          0x7
  92 #define PHASE_MUX_F_MASK        0x7
  93 #define F_FRAC_MASK             0xF8
  94 #define TWO_LSBITS              0x3
  95
  96 /* Bit groups start position in DRP registers */
  97 #define HIGH_TIME_POS           6
  98 #define LOW_TIME_POS            0
  99 #define PHASE_MUX_POS           13
 100 #define PHASE_MUX_F_POS         11
 101 #define FRAC_POS                12
 102 #define FRAC_EN_POS             11
 103 #define FRAC_WF_R_POS           10
 104 #define FRAC_WF_F_POS           10
 105 #define EDGE_POS                7
 106 #define NO_CNT_POS              6
 107 #define DELAY_TIME_POS          0
 108
 109 /* MMCM Register addresses */
 110 #define POWER_REG               0x28
 111 #define DIV_REG                 0x16
 112 #define LOCK_REG1               0x18
 113 #define LOCK_REG2               0x19
 114 #define LOCK_REG3               0x1A
 115 #define FILT_REG1               0x4E
 116 #define FILT_REG2               0x4F
 117 #define CLKOUT0_REG1            0x08
 118 #define CLKOUT0_REG2            0x09
 119 #define CLKOUT1_REG1            0x0A
 120 #define CLKOUT1_REG2            0x0B
 121 #define CLKOUT2_REG1            0x0C
 122 #define CLKOUT2_REG2            0x0D
 123 #define CLKOUT3_REG1            0x0E
 124 #define CLKOUT3_REG2            0x0F
 125 #define CLKOUT4_REG1            0x10
 126 #define CLKOUT4_REG2            0x11
 127 #define CLKOUT5_REG1            0x06
 128 #define CLKOUT5_REG2            0x07
 129 #define CLKOUT6_REG1            0x12
 130 #define CLKOUT6_REG2            0x13
 131 #define CLKFBOUT_REG1           0x14
 132 #define CLKFBOUT_REG2           0x15