1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Owen Chen <owen.chen@mediatek.com>
7 #include <linux/clk-provider.h>
8 #include <linux/platform_device.h>
13 #include <dt-bindings/clock/mt6765-clk.h>
15 static const struct mtk_gate_regs venc_cg_regs
= {
21 #define GATE_VENC(_id, _name, _parent, _shift) { \
24 .parent_name = _parent, \
25 .regs = &venc_cg_regs, \
27 .ops = &mtk_clk_gate_ops_setclr_inv, \
30 static const struct mtk_gate venc_clks
[] = {
31 GATE_VENC(CLK_VENC_SET0_LARB
, "venc_set0_larb", "mm_ck", 0),
32 GATE_VENC(CLK_VENC_SET1_VENC
, "venc_set1_venc", "mm_ck", 4),
33 GATE_VENC(CLK_VENC_SET2_JPGENC
, "jpgenc", "mm_ck", 8),
34 GATE_VENC(CLK_VENC_SET3_VDEC
, "venc_set3_vdec", "mm_ck", 12),
37 static int clk_mt6765_vcodec_probe(struct platform_device
*pdev
)
39 struct clk_onecell_data
*clk_data
;
41 struct device_node
*node
= pdev
->dev
.of_node
;
43 clk_data
= mtk_alloc_clk_data(CLK_VENC_NR_CLK
);
45 mtk_clk_register_gates(node
, venc_clks
,
46 ARRAY_SIZE(venc_clks
), clk_data
);
48 r
= of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
51 pr_err("%s(): could not register clock provider: %d\n",
57 static const struct of_device_id of_match_clk_mt6765_vcodec
[] = {
58 { .compatible
= "mediatek,mt6765-vcodecsys", },
62 static struct platform_driver clk_mt6765_vcodec_drv
= {
63 .probe
= clk_mt6765_vcodec_probe
,
65 .name
= "clk-mt6765-vcodec",
66 .of_match_table
= of_match_clk_mt6765_vcodec
,
70 builtin_platform_driver(clk_mt6765_vcodec_drv
);