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WIP FPC-III support
[linux/fpc-iii.git] / drivers / clk / meson / axg.c
blob0e44695b8772defee1aa35b6c8647fe52fe6e720
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AmLogic Meson-AXG Clock Controller Driver
4 *
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
7 *
8 * Copyright (c) 2017 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 */
11
12 #include <linux/clk-provider.h>
13 #include <linux/init.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/module.h>
17
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
21 #include "axg.h"
22 #include "meson-eeclk.h"
23
24 static DEFINE_SPINLOCK(meson_clk_lock);
25
26 static struct clk_regmap axg_fixed_pll_dco = {
27 .data = &(struct meson_clk_pll_data){
28 .en = {
29 .reg_off = HHI_MPLL_CNTL,
30 .shift = 30,
31 .width = 1,
32 },
33 .m = {
34 .reg_off = HHI_MPLL_CNTL,
35 .shift = 0,
36 .width = 9,
37 },
38 .n = {
39 .reg_off = HHI_MPLL_CNTL,
40 .shift = 9,
41 .width = 5,
42 },
43 .frac = {
44 .reg_off = HHI_MPLL_CNTL2,
45 .shift = 0,
46 .width = 12,
47 },
48 .l = {
49 .reg_off = HHI_MPLL_CNTL,
50 .shift = 31,
51 .width = 1,
52 },
53 .rst = {
54 .reg_off = HHI_MPLL_CNTL,
55 .shift = 29,
56 .width = 1,
57 },
58 },
59 .hw.init = &(struct clk_init_data){
60 .name = "fixed_pll_dco",
61 .ops = &meson_clk_pll_ro_ops,
62 .parent_data = &(const struct clk_parent_data) {
63 .fw_name = "xtal",
64 },
65 .num_parents = 1,
66 },
67 };
68
69 static struct clk_regmap axg_fixed_pll = {
70 .data = &(struct clk_regmap_div_data){
71 .offset = HHI_MPLL_CNTL,
72 .shift = 16,
73 .width = 2,
74 .flags = CLK_DIVIDER_POWER_OF_TWO,
75 },
76 .hw.init = &(struct clk_init_data){
77 .name = "fixed_pll",
78 .ops = &clk_regmap_divider_ro_ops,
79 .parent_hws = (const struct clk_hw *[]) {
80 &axg_fixed_pll_dco.hw
81 },
82 .num_parents = 1,
83 /*
84 * This clock won't ever change at runtime so
85 * CLK_SET_RATE_PARENT is not required
86 */
87 },
88 };
89
90 static struct clk_regmap axg_sys_pll_dco = {
91 .data = &(struct meson_clk_pll_data){
92 .en = {
93 .reg_off = HHI_SYS_PLL_CNTL,
94 .shift = 30,
95 .width = 1,
96 },
97 .m = {
98 .reg_off = HHI_SYS_PLL_CNTL,
99 .shift = 0,
100 .width = 9,
101 },
102 .n = {
103 .reg_off = HHI_SYS_PLL_CNTL,
104 .shift = 9,
105 .width = 5,
106 },
107 .l = {
108 .reg_off = HHI_SYS_PLL_CNTL,
109 .shift = 31,
110 .width = 1,
111 },
112 .rst = {
113 .reg_off = HHI_SYS_PLL_CNTL,
114 .shift = 29,
115 .width = 1,
116 },
117 },
118 .hw.init = &(struct clk_init_data){
119 .name = "sys_pll_dco",
120 .ops = &meson_clk_pll_ro_ops,
121 .parent_data = &(const struct clk_parent_data) {
122 .fw_name = "xtal",
123 },
124 .num_parents = 1,
125 },
126 };
127
128 static struct clk_regmap axg_sys_pll = {
129 .data = &(struct clk_regmap_div_data){
130 .offset = HHI_SYS_PLL_CNTL,
131 .shift = 16,
132 .width = 2,
133 .flags = CLK_DIVIDER_POWER_OF_TWO,
134 },
135 .hw.init = &(struct clk_init_data){
136 .name = "sys_pll",
137 .ops = &clk_regmap_divider_ro_ops,
138 .parent_hws = (const struct clk_hw *[]) {
139 &axg_sys_pll_dco.hw
140 },
141 .num_parents = 1,
142 .flags = CLK_SET_RATE_PARENT,
143 },
144 };
145
146 static const struct pll_params_table axg_gp0_pll_params_table[] = {
147 PLL_PARAMS(40, 1),
148 PLL_PARAMS(41, 1),
149 PLL_PARAMS(42, 1),
150 PLL_PARAMS(43, 1),
151 PLL_PARAMS(44, 1),
152 PLL_PARAMS(45, 1),
153 PLL_PARAMS(46, 1),
154 PLL_PARAMS(47, 1),
155 PLL_PARAMS(48, 1),
156 PLL_PARAMS(49, 1),
157 PLL_PARAMS(50, 1),
158 PLL_PARAMS(51, 1),
159 PLL_PARAMS(52, 1),
160 PLL_PARAMS(53, 1),
161 PLL_PARAMS(54, 1),
162 PLL_PARAMS(55, 1),
163 PLL_PARAMS(56, 1),
164 PLL_PARAMS(57, 1),
165 PLL_PARAMS(58, 1),
166 PLL_PARAMS(59, 1),
167 PLL_PARAMS(60, 1),
168 PLL_PARAMS(61, 1),
169 PLL_PARAMS(62, 1),
170 PLL_PARAMS(63, 1),
171 PLL_PARAMS(64, 1),
172 PLL_PARAMS(65, 1),
173 PLL_PARAMS(66, 1),
174 PLL_PARAMS(67, 1),
175 PLL_PARAMS(68, 1),
176 { /* sentinel */ },
177 };
178
179 static const struct reg_sequence axg_gp0_init_regs[] = {
180 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
181 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
182 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
183 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
184 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
185 };
186
187 static struct clk_regmap axg_gp0_pll_dco = {
188 .data = &(struct meson_clk_pll_data){
189 .en = {
190 .reg_off = HHI_GP0_PLL_CNTL,
191 .shift = 30,
192 .width = 1,
193 },
194 .m = {
195 .reg_off = HHI_GP0_PLL_CNTL,
196 .shift = 0,
197 .width = 9,
198 },
199 .n = {
200 .reg_off = HHI_GP0_PLL_CNTL,
201 .shift = 9,
202 .width = 5,
203 },
204 .frac = {
205 .reg_off = HHI_GP0_PLL_CNTL1,
206 .shift = 0,
207 .width = 10,
208 },
209 .l = {
210 .reg_off = HHI_GP0_PLL_CNTL,
211 .shift = 31,
212 .width = 1,
213 },
214 .rst = {
215 .reg_off = HHI_GP0_PLL_CNTL,
216 .shift = 29,
217 .width = 1,
218 },
219 .table = axg_gp0_pll_params_table,
220 .init_regs = axg_gp0_init_regs,
221 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
222 },
223 .hw.init = &(struct clk_init_data){
224 .name = "gp0_pll_dco",
225 .ops = &meson_clk_pll_ops,
226 .parent_data = &(const struct clk_parent_data) {
227 .fw_name = "xtal",
228 },
229 .num_parents = 1,
230 },
231 };
232
233 static struct clk_regmap axg_gp0_pll = {
234 .data = &(struct clk_regmap_div_data){
235 .offset = HHI_GP0_PLL_CNTL,
236 .shift = 16,
237 .width = 2,
238 .flags = CLK_DIVIDER_POWER_OF_TWO,
239 },
240 .hw.init = &(struct clk_init_data){
241 .name = "gp0_pll",
242 .ops = &clk_regmap_divider_ops,
243 .parent_hws = (const struct clk_hw *[]) {
244 &axg_gp0_pll_dco.hw
245 },
246 .num_parents = 1,
247 .flags = CLK_SET_RATE_PARENT,
248 },
249 };
250
251 static const struct reg_sequence axg_hifi_init_regs[] = {
252 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
253 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
254 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
255 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
256 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
257 };
258
259 static struct clk_regmap axg_hifi_pll_dco = {
260 .data = &(struct meson_clk_pll_data){
261 .en = {
262 .reg_off = HHI_HIFI_PLL_CNTL,
263 .shift = 30,
264 .width = 1,
265 },
266 .m = {
267 .reg_off = HHI_HIFI_PLL_CNTL,
268 .shift = 0,
269 .width = 9,
270 },
271 .n = {
272 .reg_off = HHI_HIFI_PLL_CNTL,
273 .shift = 9,
274 .width = 5,
275 },
276 .frac = {
277 .reg_off = HHI_HIFI_PLL_CNTL5,
278 .shift = 0,
279 .width = 13,
280 },
281 .l = {
282 .reg_off = HHI_HIFI_PLL_CNTL,
283 .shift = 31,
284 .width = 1,
285 },
286 .rst = {
287 .reg_off = HHI_HIFI_PLL_CNTL,
288 .shift = 29,
289 .width = 1,
290 },
291 .table = axg_gp0_pll_params_table,
292 .init_regs = axg_hifi_init_regs,
293 .init_count = ARRAY_SIZE(axg_hifi_init_regs),
294 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
295 },
296 .hw.init = &(struct clk_init_data){
297 .name = "hifi_pll_dco",
298 .ops = &meson_clk_pll_ops,
299 .parent_data = &(const struct clk_parent_data) {
300 .fw_name = "xtal",
301 },
302 .num_parents = 1,
303 },
304 };
305
306 static struct clk_regmap axg_hifi_pll = {
307 .data = &(struct clk_regmap_div_data){
308 .offset = HHI_HIFI_PLL_CNTL,
309 .shift = 16,
310 .width = 2,
311 .flags = CLK_DIVIDER_POWER_OF_TWO,
312 },
313 .hw.init = &(struct clk_init_data){
314 .name = "hifi_pll",
315 .ops = &clk_regmap_divider_ops,
316 .parent_hws = (const struct clk_hw *[]) {
317 &axg_hifi_pll_dco.hw
318 },
319 .num_parents = 1,
320 .flags = CLK_SET_RATE_PARENT,
321 },
322 };
323
324 static struct clk_fixed_factor axg_fclk_div2_div = {
325 .mult = 1,
326 .div = 2,
327 .hw.init = &(struct clk_init_data){
328 .name = "fclk_div2_div",
329 .ops = &clk_fixed_factor_ops,
330 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
331 .num_parents = 1,
332 },
333 };
334
335 static struct clk_regmap axg_fclk_div2 = {
336 .data = &(struct clk_regmap_gate_data){
337 .offset = HHI_MPLL_CNTL6,
338 .bit_idx = 27,
339 },
340 .hw.init = &(struct clk_init_data){
341 .name = "fclk_div2",
342 .ops = &clk_regmap_gate_ops,
343 .parent_hws = (const struct clk_hw *[]) {
344 &axg_fclk_div2_div.hw
345 },
346 .num_parents = 1,
347 .flags = CLK_IS_CRITICAL,
348 },
349 };
350
351 static struct clk_fixed_factor axg_fclk_div3_div = {
352 .mult = 1,
353 .div = 3,
354 .hw.init = &(struct clk_init_data){
355 .name = "fclk_div3_div",
356 .ops = &clk_fixed_factor_ops,
357 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
358 .num_parents = 1,
359 },
360 };
361
362 static struct clk_regmap axg_fclk_div3 = {
363 .data = &(struct clk_regmap_gate_data){
364 .offset = HHI_MPLL_CNTL6,
365 .bit_idx = 28,
366 },
367 .hw.init = &(struct clk_init_data){
368 .name = "fclk_div3",
369 .ops = &clk_regmap_gate_ops,
370 .parent_hws = (const struct clk_hw *[]) {
371 &axg_fclk_div3_div.hw
372 },
373 .num_parents = 1,
374 /*
375 * FIXME:
376 * This clock, as fdiv2, is used by the SCPI FW and is required
377 * by the platform to operate correctly.
378 * Until the following condition are met, we need this clock to
379 * be marked as critical:
380 * a) The SCPI generic driver claims and enable all the clocks
381 * it needs
382 * b) CCF has a clock hand-off mechanism to make the sure the
383 * clock stays on until the proper driver comes along
384 */
385 .flags = CLK_IS_CRITICAL,
386 },
387 };
388
389 static struct clk_fixed_factor axg_fclk_div4_div = {
390 .mult = 1,
391 .div = 4,
392 .hw.init = &(struct clk_init_data){
393 .name = "fclk_div4_div",
394 .ops = &clk_fixed_factor_ops,
395 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
396 .num_parents = 1,
397 },
398 };
399
400 static struct clk_regmap axg_fclk_div4 = {
401 .data = &(struct clk_regmap_gate_data){
402 .offset = HHI_MPLL_CNTL6,
403 .bit_idx = 29,
404 },
405 .hw.init = &(struct clk_init_data){
406 .name = "fclk_div4",
407 .ops = &clk_regmap_gate_ops,
408 .parent_hws = (const struct clk_hw *[]) {
409 &axg_fclk_div4_div.hw
410 },
411 .num_parents = 1,
412 },
413 };
414
415 static struct clk_fixed_factor axg_fclk_div5_div = {
416 .mult = 1,
417 .div = 5,
418 .hw.init = &(struct clk_init_data){
419 .name = "fclk_div5_div",
420 .ops = &clk_fixed_factor_ops,
421 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
422 .num_parents = 1,
423 },
424 };
425
426 static struct clk_regmap axg_fclk_div5 = {
427 .data = &(struct clk_regmap_gate_data){
428 .offset = HHI_MPLL_CNTL6,
429 .bit_idx = 30,
430 },
431 .hw.init = &(struct clk_init_data){
432 .name = "fclk_div5",
433 .ops = &clk_regmap_gate_ops,
434 .parent_hws = (const struct clk_hw *[]) {
435 &axg_fclk_div5_div.hw
436 },
437 .num_parents = 1,
438 },
439 };
440
441 static struct clk_fixed_factor axg_fclk_div7_div = {
442 .mult = 1,
443 .div = 7,
444 .hw.init = &(struct clk_init_data){
445 .name = "fclk_div7_div",
446 .ops = &clk_fixed_factor_ops,
447 .parent_hws = (const struct clk_hw *[]) {
448 &axg_fixed_pll.hw
449 },
450 .num_parents = 1,
451 },
452 };
453
454 static struct clk_regmap axg_fclk_div7 = {
455 .data = &(struct clk_regmap_gate_data){
456 .offset = HHI_MPLL_CNTL6,
457 .bit_idx = 31,
458 },
459 .hw.init = &(struct clk_init_data){
460 .name = "fclk_div7",
461 .ops = &clk_regmap_gate_ops,
462 .parent_hws = (const struct clk_hw *[]) {
463 &axg_fclk_div7_div.hw
464 },
465 .num_parents = 1,
466 },
467 };
468
469 static struct clk_regmap axg_mpll_prediv = {
470 .data = &(struct clk_regmap_div_data){
471 .offset = HHI_MPLL_CNTL5,
472 .shift = 12,
473 .width = 1,
474 },
475 .hw.init = &(struct clk_init_data){
476 .name = "mpll_prediv",
477 .ops = &clk_regmap_divider_ro_ops,
478 .parent_hws = (const struct clk_hw *[]) {
479 &axg_fixed_pll.hw
480 },
481 .num_parents = 1,
482 },
483 };
484
485 static struct clk_regmap axg_mpll0_div = {
486 .data = &(struct meson_clk_mpll_data){
487 .sdm = {
488 .reg_off = HHI_MPLL_CNTL7,
489 .shift = 0,
490 .width = 14,
491 },
492 .sdm_en = {
493 .reg_off = HHI_MPLL_CNTL7,
494 .shift = 15,
495 .width = 1,
496 },
497 .n2 = {
498 .reg_off = HHI_MPLL_CNTL7,
499 .shift = 16,
500 .width = 9,
501 },
502 .misc = {
503 .reg_off = HHI_PLL_TOP_MISC,
504 .shift = 0,
505 .width = 1,
506 },
507 .lock = &meson_clk_lock,
508 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
509 },
510 .hw.init = &(struct clk_init_data){
511 .name = "mpll0_div",
512 .ops = &meson_clk_mpll_ops,
513 .parent_hws = (const struct clk_hw *[]) {
514 &axg_mpll_prediv.hw
515 },
516 .num_parents = 1,
517 },
518 };
519
520 static struct clk_regmap axg_mpll0 = {
521 .data = &(struct clk_regmap_gate_data){
522 .offset = HHI_MPLL_CNTL7,
523 .bit_idx = 14,
524 },
525 .hw.init = &(struct clk_init_data){
526 .name = "mpll0",
527 .ops = &clk_regmap_gate_ops,
528 .parent_hws = (const struct clk_hw *[]) {
529 &axg_mpll0_div.hw
530 },
531 .num_parents = 1,
532 .flags = CLK_SET_RATE_PARENT,
533 },
534 };
535
536 static struct clk_regmap axg_mpll1_div = {
537 .data = &(struct meson_clk_mpll_data){
538 .sdm = {
539 .reg_off = HHI_MPLL_CNTL8,
540 .shift = 0,
541 .width = 14,
542 },
543 .sdm_en = {
544 .reg_off = HHI_MPLL_CNTL8,
545 .shift = 15,
546 .width = 1,
547 },
548 .n2 = {
549 .reg_off = HHI_MPLL_CNTL8,
550 .shift = 16,
551 .width = 9,
552 },
553 .misc = {
554 .reg_off = HHI_PLL_TOP_MISC,
555 .shift = 1,
556 .width = 1,
557 },
558 .lock = &meson_clk_lock,
559 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
560 },
561 .hw.init = &(struct clk_init_data){
562 .name = "mpll1_div",
563 .ops = &meson_clk_mpll_ops,
564 .parent_hws = (const struct clk_hw *[]) {
565 &axg_mpll_prediv.hw
566 },
567 .num_parents = 1,
568 },
569 };
570
571 static struct clk_regmap axg_mpll1 = {
572 .data = &(struct clk_regmap_gate_data){
573 .offset = HHI_MPLL_CNTL8,
574 .bit_idx = 14,
575 },
576 .hw.init = &(struct clk_init_data){
577 .name = "mpll1",
578 .ops = &clk_regmap_gate_ops,
579 .parent_hws = (const struct clk_hw *[]) {
580 &axg_mpll1_div.hw
581 },
582 .num_parents = 1,
583 .flags = CLK_SET_RATE_PARENT,
584 },
585 };
586
587 static struct clk_regmap axg_mpll2_div = {
588 .data = &(struct meson_clk_mpll_data){
589 .sdm = {
590 .reg_off = HHI_MPLL_CNTL9,
591 .shift = 0,
592 .width = 14,
593 },
594 .sdm_en = {
595 .reg_off = HHI_MPLL_CNTL9,
596 .shift = 15,
597 .width = 1,
598 },
599 .n2 = {
600 .reg_off = HHI_MPLL_CNTL9,
601 .shift = 16,
602 .width = 9,
603 },
604 .ssen = {
605 .reg_off = HHI_MPLL_CNTL,
606 .shift = 25,
607 .width = 1,
608 },
609 .misc = {
610 .reg_off = HHI_PLL_TOP_MISC,
611 .shift = 2,
612 .width = 1,
613 },
614 .lock = &meson_clk_lock,
615 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
616 },
617 .hw.init = &(struct clk_init_data){
618 .name = "mpll2_div",
619 .ops = &meson_clk_mpll_ops,
620 .parent_hws = (const struct clk_hw *[]) {
621 &axg_mpll_prediv.hw
622 },
623 .num_parents = 1,
624 },
625 };
626
627 static struct clk_regmap axg_mpll2 = {
628 .data = &(struct clk_regmap_gate_data){
629 .offset = HHI_MPLL_CNTL9,
630 .bit_idx = 14,
631 },
632 .hw.init = &(struct clk_init_data){
633 .name = "mpll2",
634 .ops = &clk_regmap_gate_ops,
635 .parent_hws = (const struct clk_hw *[]) {
636 &axg_mpll2_div.hw
637 },
638 .num_parents = 1,
639 .flags = CLK_SET_RATE_PARENT,
640 },
641 };
642
643 static struct clk_regmap axg_mpll3_div = {
644 .data = &(struct meson_clk_mpll_data){
645 .sdm = {
646 .reg_off = HHI_MPLL3_CNTL0,
647 .shift = 12,
648 .width = 14,
649 },
650 .sdm_en = {
651 .reg_off = HHI_MPLL3_CNTL0,
652 .shift = 11,
653 .width = 1,
654 },
655 .n2 = {
656 .reg_off = HHI_MPLL3_CNTL0,
657 .shift = 2,
658 .width = 9,
659 },
660 .misc = {
661 .reg_off = HHI_PLL_TOP_MISC,
662 .shift = 3,
663 .width = 1,
664 },
665 .lock = &meson_clk_lock,
666 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
667 },
668 .hw.init = &(struct clk_init_data){
669 .name = "mpll3_div",
670 .ops = &meson_clk_mpll_ops,
671 .parent_hws = (const struct clk_hw *[]) {
672 &axg_mpll_prediv.hw
673 },
674 .num_parents = 1,
675 },
676 };
677
678 static struct clk_regmap axg_mpll3 = {
679 .data = &(struct clk_regmap_gate_data){
680 .offset = HHI_MPLL3_CNTL0,
681 .bit_idx = 0,
682 },
683 .hw.init = &(struct clk_init_data){
684 .name = "mpll3",
685 .ops = &clk_regmap_gate_ops,
686 .parent_hws = (const struct clk_hw *[]) {
687 &axg_mpll3_div.hw
688 },
689 .num_parents = 1,
690 .flags = CLK_SET_RATE_PARENT,
691 },
692 };
693
694 static const struct pll_params_table axg_pcie_pll_params_table[] = {
695 {
696 .m = 200,
697 .n = 3,
698 },
699 { /* sentinel */ },
700 };
701
702 static const struct reg_sequence axg_pcie_init_regs[] = {
703 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
704 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
705 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
706 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d },
707 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 },
708 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 },
709 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
710 };
711
712 static struct clk_regmap axg_pcie_pll_dco = {
713 .data = &(struct meson_clk_pll_data){
714 .en = {
715 .reg_off = HHI_PCIE_PLL_CNTL,
716 .shift = 30,
717 .width = 1,
718 },
719 .m = {
720 .reg_off = HHI_PCIE_PLL_CNTL,
721 .shift = 0,
722 .width = 9,
723 },
724 .n = {
725 .reg_off = HHI_PCIE_PLL_CNTL,
726 .shift = 9,
727 .width = 5,
728 },
729 .frac = {
730 .reg_off = HHI_PCIE_PLL_CNTL1,
731 .shift = 0,
732 .width = 12,
733 },
734 .l = {
735 .reg_off = HHI_PCIE_PLL_CNTL,
736 .shift = 31,
737 .width = 1,
738 },
739 .rst = {
740 .reg_off = HHI_PCIE_PLL_CNTL,
741 .shift = 29,
742 .width = 1,
743 },
744 .table = axg_pcie_pll_params_table,
745 .init_regs = axg_pcie_init_regs,
746 .init_count = ARRAY_SIZE(axg_pcie_init_regs),
747 },
748 .hw.init = &(struct clk_init_data){
749 .name = "pcie_pll_dco",
750 .ops = &meson_clk_pll_ops,
751 .parent_data = &(const struct clk_parent_data) {
752 .fw_name = "xtal",
753 },
754 .num_parents = 1,
755 },
756 };
757
758 static struct clk_regmap axg_pcie_pll_od = {
759 .data = &(struct clk_regmap_div_data){
760 .offset = HHI_PCIE_PLL_CNTL,
761 .shift = 16,
762 .width = 2,
763 .flags = CLK_DIVIDER_POWER_OF_TWO,
764 },
765 .hw.init = &(struct clk_init_data){
766 .name = "pcie_pll_od",
767 .ops = &clk_regmap_divider_ops,
768 .parent_hws = (const struct clk_hw *[]) {
769 &axg_pcie_pll_dco.hw
770 },
771 .num_parents = 1,
772 .flags = CLK_SET_RATE_PARENT,
773 },
774 };
775
776 static struct clk_regmap axg_pcie_pll = {
777 .data = &(struct clk_regmap_div_data){
778 .offset = HHI_PCIE_PLL_CNTL6,
779 .shift = 6,
780 .width = 2,
781 .flags = CLK_DIVIDER_POWER_OF_TWO,
782 },
783 .hw.init = &(struct clk_init_data){
784 .name = "pcie_pll",
785 .ops = &clk_regmap_divider_ops,
786 .parent_hws = (const struct clk_hw *[]) {
787 &axg_pcie_pll_od.hw
788 },
789 .num_parents = 1,
790 .flags = CLK_SET_RATE_PARENT,
791 },
792 };
793
794 static struct clk_regmap axg_pcie_mux = {
795 .data = &(struct clk_regmap_mux_data){
796 .offset = HHI_PCIE_PLL_CNTL6,
797 .mask = 0x1,
798 .shift = 2,
799 /* skip the parent mpll3, reserved for debug */
800 .table = (u32[]){ 1 },
801 },
802 .hw.init = &(struct clk_init_data){
803 .name = "pcie_mux",
804 .ops = &clk_regmap_mux_ops,
805 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw },
806 .num_parents = 1,
807 .flags = CLK_SET_RATE_PARENT,
808 },
809 };
810
811 static struct clk_regmap axg_pcie_ref = {
812 .data = &(struct clk_regmap_mux_data){
813 .offset = HHI_PCIE_PLL_CNTL6,
814 .mask = 0x1,
815 .shift = 1,
816 /* skip the parent 0, reserved for debug */
817 .table = (u32[]){ 1 },
818 },
819 .hw.init = &(struct clk_init_data){
820 .name = "pcie_ref",
821 .ops = &clk_regmap_mux_ops,
822 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw },
823 .num_parents = 1,
824 .flags = CLK_SET_RATE_PARENT,
825 },
826 };
827
828 static struct clk_regmap axg_pcie_cml_en0 = {
829 .data = &(struct clk_regmap_gate_data){
830 .offset = HHI_PCIE_PLL_CNTL6,
831 .bit_idx = 4,
832 },
833 .hw.init = &(struct clk_init_data) {
834 .name = "pcie_cml_en0",
835 .ops = &clk_regmap_gate_ops,
836 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
837 .num_parents = 1,
838 .flags = CLK_SET_RATE_PARENT,
839
840 },
841 };
842
843 static struct clk_regmap axg_pcie_cml_en1 = {
844 .data = &(struct clk_regmap_gate_data){
845 .offset = HHI_PCIE_PLL_CNTL6,
846 .bit_idx = 3,
847 },
848 .hw.init = &(struct clk_init_data) {
849 .name = "pcie_cml_en1",
850 .ops = &clk_regmap_gate_ops,
851 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
852 .num_parents = 1,
853 .flags = CLK_SET_RATE_PARENT,
854 },
855 };
856
857 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
858 static const struct clk_parent_data clk81_parent_data[] = {
859 { .fw_name = "xtal", },
860 { .hw = &axg_fclk_div7.hw },
861 { .hw = &axg_mpll1.hw },
862 { .hw = &axg_mpll2.hw },
863 { .hw = &axg_fclk_div4.hw },
864 { .hw = &axg_fclk_div3.hw },
865 { .hw = &axg_fclk_div5.hw },
866 };
867
868 static struct clk_regmap axg_mpeg_clk_sel = {
869 .data = &(struct clk_regmap_mux_data){
870 .offset = HHI_MPEG_CLK_CNTL,
871 .mask = 0x7,
872 .shift = 12,
873 .table = mux_table_clk81,
874 },
875 .hw.init = &(struct clk_init_data){
876 .name = "mpeg_clk_sel",
877 .ops = &clk_regmap_mux_ro_ops,
878 .parent_data = clk81_parent_data,
879 .num_parents = ARRAY_SIZE(clk81_parent_data),
880 },
881 };
882
883 static struct clk_regmap axg_mpeg_clk_div = {
884 .data = &(struct clk_regmap_div_data){
885 .offset = HHI_MPEG_CLK_CNTL,
886 .shift = 0,
887 .width = 7,
888 },
889 .hw.init = &(struct clk_init_data){
890 .name = "mpeg_clk_div",
891 .ops = &clk_regmap_divider_ops,
892 .parent_hws = (const struct clk_hw *[]) {
893 &axg_mpeg_clk_sel.hw
894 },
895 .num_parents = 1,
896 .flags = CLK_SET_RATE_PARENT,
897 },
898 };
899
900 static struct clk_regmap axg_clk81 = {
901 .data = &(struct clk_regmap_gate_data){
902 .offset = HHI_MPEG_CLK_CNTL,
903 .bit_idx = 7,
904 },
905 .hw.init = &(struct clk_init_data){
906 .name = "clk81",
907 .ops = &clk_regmap_gate_ops,
908 .parent_hws = (const struct clk_hw *[]) {
909 &axg_mpeg_clk_div.hw
910 },
911 .num_parents = 1,
912 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
913 },
914 };
915
916 static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
917 { .fw_name = "xtal", },
918 { .hw = &axg_fclk_div2.hw },
919 { .hw = &axg_fclk_div3.hw },
920 { .hw = &axg_fclk_div5.hw },
921 { .hw = &axg_fclk_div7.hw },
922 /*
923 * Following these parent clocks, we should also have had mpll2, mpll3
924 * and gp0_pll but these clocks are too precious to be used here. All
925 * the necessary rates for MMC and NAND operation can be acheived using
926 * xtal or fclk_div clocks
927 */
928 };
929
930 /* SDcard clock */
931 static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
932 .data = &(struct clk_regmap_mux_data){
933 .offset = HHI_SD_EMMC_CLK_CNTL,
934 .mask = 0x7,
935 .shift = 25,
936 },
937 .hw.init = &(struct clk_init_data) {
938 .name = "sd_emmc_b_clk0_sel",
939 .ops = &clk_regmap_mux_ops,
940 .parent_data = axg_sd_emmc_clk0_parent_data,
941 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
942 .flags = CLK_SET_RATE_PARENT,
943 },
944 };
945
946 static struct clk_regmap axg_sd_emmc_b_clk0_div = {
947 .data = &(struct clk_regmap_div_data){
948 .offset = HHI_SD_EMMC_CLK_CNTL,
949 .shift = 16,
950 .width = 7,
951 .flags = CLK_DIVIDER_ROUND_CLOSEST,
952 },
953 .hw.init = &(struct clk_init_data) {
954 .name = "sd_emmc_b_clk0_div",
955 .ops = &clk_regmap_divider_ops,
956 .parent_hws = (const struct clk_hw *[]) {
957 &axg_sd_emmc_b_clk0_sel.hw
958 },
959 .num_parents = 1,
960 .flags = CLK_SET_RATE_PARENT,
961 },
962 };
963
964 static struct clk_regmap axg_sd_emmc_b_clk0 = {
965 .data = &(struct clk_regmap_gate_data){
966 .offset = HHI_SD_EMMC_CLK_CNTL,
967 .bit_idx = 23,
968 },
969 .hw.init = &(struct clk_init_data){
970 .name = "sd_emmc_b_clk0",
971 .ops = &clk_regmap_gate_ops,
972 .parent_hws = (const struct clk_hw *[]) {
973 &axg_sd_emmc_b_clk0_div.hw
974 },
975 .num_parents = 1,
976 .flags = CLK_SET_RATE_PARENT,
977 },
978 };
979
980 /* EMMC/NAND clock */
981 static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
982 .data = &(struct clk_regmap_mux_data){
983 .offset = HHI_NAND_CLK_CNTL,
984 .mask = 0x7,
985 .shift = 9,
986 },
987 .hw.init = &(struct clk_init_data) {
988 .name = "sd_emmc_c_clk0_sel",
989 .ops = &clk_regmap_mux_ops,
990 .parent_data = axg_sd_emmc_clk0_parent_data,
991 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
992 .flags = CLK_SET_RATE_PARENT,
993 },
994 };
995
996 static struct clk_regmap axg_sd_emmc_c_clk0_div = {
997 .data = &(struct clk_regmap_div_data){
998 .offset = HHI_NAND_CLK_CNTL,
999 .shift = 0,
1000 .width = 7,
1001 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1002 },
1003 .hw.init = &(struct clk_init_data) {
1004 .name = "sd_emmc_c_clk0_div",
1005 .ops = &clk_regmap_divider_ops,
1006 .parent_hws = (const struct clk_hw *[]) {
1007 &axg_sd_emmc_c_clk0_sel.hw
1008 },
1009 .num_parents = 1,
1010 .flags = CLK_SET_RATE_PARENT,
1011 },
1012 };
1013
1014 static struct clk_regmap axg_sd_emmc_c_clk0 = {
1015 .data = &(struct clk_regmap_gate_data){
1016 .offset = HHI_NAND_CLK_CNTL,
1017 .bit_idx = 7,
1018 },
1019 .hw.init = &(struct clk_init_data){
1020 .name = "sd_emmc_c_clk0",
1021 .ops = &clk_regmap_gate_ops,
1022 .parent_hws = (const struct clk_hw *[]) {
1023 &axg_sd_emmc_c_clk0_div.hw
1024 },
1025 .num_parents = 1,
1026 .flags = CLK_SET_RATE_PARENT,
1027 },
1028 };
1029
1030 /* VPU Clock */
1031
1032 static const struct clk_hw *axg_vpu_parent_hws[] = {
1033 &axg_fclk_div4.hw,
1034 &axg_fclk_div3.hw,
1035 &axg_fclk_div5.hw,
1036 &axg_fclk_div7.hw,
1037 };
1038
1039 static struct clk_regmap axg_vpu_0_sel = {
1040 .data = &(struct clk_regmap_mux_data){
1041 .offset = HHI_VPU_CLK_CNTL,
1042 .mask = 0x3,
1043 .shift = 9,
1044 },
1045 .hw.init = &(struct clk_init_data){
1046 .name = "vpu_0_sel",
1047 .ops = &clk_regmap_mux_ops,
1048 .parent_hws = axg_vpu_parent_hws,
1049 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1050 /* We need a specific parent for VPU clock source, let it be set in DT */
1051 .flags = CLK_SET_RATE_NO_REPARENT,
1052 },
1053 };
1054
1055 static struct clk_regmap axg_vpu_0_div = {
1056 .data = &(struct clk_regmap_div_data){
1057 .offset = HHI_VPU_CLK_CNTL,
1058 .shift = 0,
1059 .width = 7,
1060 },
1061 .hw.init = &(struct clk_init_data){
1062 .name = "vpu_0_div",
1063 .ops = &clk_regmap_divider_ops,
1064 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_sel.hw },
1065 .num_parents = 1,
1066 .flags = CLK_SET_RATE_PARENT,
1067 },
1068 };
1069
1070 static struct clk_regmap axg_vpu_0 = {
1071 .data = &(struct clk_regmap_gate_data){
1072 .offset = HHI_VPU_CLK_CNTL,
1073 .bit_idx = 8,
1074 },
1075 .hw.init = &(struct clk_init_data) {
1076 .name = "vpu_0",
1077 .ops = &clk_regmap_gate_ops,
1078 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_div.hw },
1079 .num_parents = 1,
1080 /*
1081 * We want to avoid CCF to disable the VPU clock if
1082 * display has been set by Bootloader
1083 */
1084 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1085 },
1086 };
1087
1088 static struct clk_regmap axg_vpu_1_sel = {
1089 .data = &(struct clk_regmap_mux_data){
1090 .offset = HHI_VPU_CLK_CNTL,
1091 .mask = 0x3,
1092 .shift = 25,
1093 },
1094 .hw.init = &(struct clk_init_data){
1095 .name = "vpu_1_sel",
1096 .ops = &clk_regmap_mux_ops,
1097 .parent_hws = axg_vpu_parent_hws,
1098 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1099 /* We need a specific parent for VPU clock source, let it be set in DT */
1100 .flags = CLK_SET_RATE_NO_REPARENT,
1101 },
1102 };
1103
1104 static struct clk_regmap axg_vpu_1_div = {
1105 .data = &(struct clk_regmap_div_data){
1106 .offset = HHI_VPU_CLK_CNTL,
1107 .shift = 16,
1108 .width = 7,
1109 },
1110 .hw.init = &(struct clk_init_data){
1111 .name = "vpu_1_div",
1112 .ops = &clk_regmap_divider_ops,
1113 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_sel.hw },
1114 .num_parents = 1,
1115 .flags = CLK_SET_RATE_PARENT,
1116 },
1117 };
1118
1119 static struct clk_regmap axg_vpu_1 = {
1120 .data = &(struct clk_regmap_gate_data){
1121 .offset = HHI_VPU_CLK_CNTL,
1122 .bit_idx = 24,
1123 },
1124 .hw.init = &(struct clk_init_data) {
1125 .name = "vpu_1",
1126 .ops = &clk_regmap_gate_ops,
1127 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_div.hw },
1128 .num_parents = 1,
1129 /*
1130 * We want to avoid CCF to disable the VPU clock if
1131 * display has been set by Bootloader
1132 */
1133 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1134 },
1135 };
1136
1137 static struct clk_regmap axg_vpu = {
1138 .data = &(struct clk_regmap_mux_data){
1139 .offset = HHI_VPU_CLK_CNTL,
1140 .mask = 1,
1141 .shift = 31,
1142 },
1143 .hw.init = &(struct clk_init_data){
1144 .name = "vpu",
1145 .ops = &clk_regmap_mux_ops,
1146 .parent_hws = (const struct clk_hw *[]) {
1147 &axg_vpu_0.hw,
1148 &axg_vpu_1.hw
1149 },
1150 .num_parents = 2,
1151 .flags = CLK_SET_RATE_NO_REPARENT,
1152 },
1153 };
1154
1155 /* VAPB Clock */
1156
1157 static struct clk_regmap axg_vapb_0_sel = {
1158 .data = &(struct clk_regmap_mux_data){
1159 .offset = HHI_VAPBCLK_CNTL,
1160 .mask = 0x3,
1161 .shift = 9,
1162 },
1163 .hw.init = &(struct clk_init_data){
1164 .name = "vapb_0_sel",
1165 .ops = &clk_regmap_mux_ops,
1166 .parent_hws = axg_vpu_parent_hws,
1167 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1168 .flags = CLK_SET_RATE_NO_REPARENT,
1169 },
1170 };
1171
1172 static struct clk_regmap axg_vapb_0_div = {
1173 .data = &(struct clk_regmap_div_data){
1174 .offset = HHI_VAPBCLK_CNTL,
1175 .shift = 0,
1176 .width = 7,
1177 },
1178 .hw.init = &(struct clk_init_data){
1179 .name = "vapb_0_div",
1180 .ops = &clk_regmap_divider_ops,
1181 .parent_hws = (const struct clk_hw *[]) {
1182 &axg_vapb_0_sel.hw
1183 },
1184 .num_parents = 1,
1185 .flags = CLK_SET_RATE_PARENT,
1186 },
1187 };
1188
1189 static struct clk_regmap axg_vapb_0 = {
1190 .data = &(struct clk_regmap_gate_data){
1191 .offset = HHI_VAPBCLK_CNTL,
1192 .bit_idx = 8,
1193 },
1194 .hw.init = &(struct clk_init_data) {
1195 .name = "vapb_0",
1196 .ops = &clk_regmap_gate_ops,
1197 .parent_hws = (const struct clk_hw *[]) {
1198 &axg_vapb_0_div.hw
1199 },
1200 .num_parents = 1,
1201 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1202 },
1203 };
1204
1205 static struct clk_regmap axg_vapb_1_sel = {
1206 .data = &(struct clk_regmap_mux_data){
1207 .offset = HHI_VAPBCLK_CNTL,
1208 .mask = 0x3,
1209 .shift = 25,
1210 },
1211 .hw.init = &(struct clk_init_data){
1212 .name = "vapb_1_sel",
1213 .ops = &clk_regmap_mux_ops,
1214 .parent_hws = axg_vpu_parent_hws,
1215 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1216 .flags = CLK_SET_RATE_NO_REPARENT,
1217 },
1218 };
1219
1220 static struct clk_regmap axg_vapb_1_div = {
1221 .data = &(struct clk_regmap_div_data){
1222 .offset = HHI_VAPBCLK_CNTL,
1223 .shift = 16,
1224 .width = 7,
1225 },
1226 .hw.init = &(struct clk_init_data){
1227 .name = "vapb_1_div",
1228 .ops = &clk_regmap_divider_ops,
1229 .parent_hws = (const struct clk_hw *[]) {
1230 &axg_vapb_1_sel.hw
1231 },
1232 .num_parents = 1,
1233 .flags = CLK_SET_RATE_PARENT,
1234 },
1235 };
1236
1237 static struct clk_regmap axg_vapb_1 = {
1238 .data = &(struct clk_regmap_gate_data){
1239 .offset = HHI_VAPBCLK_CNTL,
1240 .bit_idx = 24,
1241 },
1242 .hw.init = &(struct clk_init_data) {
1243 .name = "vapb_1",
1244 .ops = &clk_regmap_gate_ops,
1245 .parent_hws = (const struct clk_hw *[]) {
1246 &axg_vapb_1_div.hw
1247 },
1248 .num_parents = 1,
1249 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1250 },
1251 };
1252
1253 static struct clk_regmap axg_vapb_sel = {
1254 .data = &(struct clk_regmap_mux_data){
1255 .offset = HHI_VAPBCLK_CNTL,
1256 .mask = 1,
1257 .shift = 31,
1258 },
1259 .hw.init = &(struct clk_init_data){
1260 .name = "vapb_sel",
1261 .ops = &clk_regmap_mux_ops,
1262 .parent_hws = (const struct clk_hw *[]) {
1263 &axg_vapb_0.hw,
1264 &axg_vapb_1.hw
1265 },
1266 .num_parents = 2,
1267 .flags = CLK_SET_RATE_NO_REPARENT,
1268 },
1269 };
1270
1271 static struct clk_regmap axg_vapb = {
1272 .data = &(struct clk_regmap_gate_data){
1273 .offset = HHI_VAPBCLK_CNTL,
1274 .bit_idx = 30,
1275 },
1276 .hw.init = &(struct clk_init_data) {
1277 .name = "vapb",
1278 .ops = &clk_regmap_gate_ops,
1279 .parent_hws = (const struct clk_hw *[]) { &axg_vapb_sel.hw },
1280 .num_parents = 1,
1281 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1282 },
1283 };
1284
1285 /* Video Clocks */
1286
1287 static const struct clk_hw *axg_vclk_parent_hws[] = {
1288 &axg_gp0_pll.hw,
1289 &axg_fclk_div4.hw,
1290 &axg_fclk_div3.hw,
1291 &axg_fclk_div5.hw,
1292 &axg_fclk_div2.hw,
1293 &axg_fclk_div7.hw,
1294 &axg_mpll1.hw,
1295 };
1296
1297 static struct clk_regmap axg_vclk_sel = {
1298 .data = &(struct clk_regmap_mux_data){
1299 .offset = HHI_VID_CLK_CNTL,
1300 .mask = 0x7,
1301 .shift = 16,
1302 },
1303 .hw.init = &(struct clk_init_data){
1304 .name = "vclk_sel",
1305 .ops = &clk_regmap_mux_ops,
1306 .parent_hws = axg_vclk_parent_hws,
1307 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws),
1308 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1309 },
1310 };
1311
1312 static struct clk_regmap axg_vclk2_sel = {
1313 .data = &(struct clk_regmap_mux_data){
1314 .offset = HHI_VIID_CLK_CNTL,
1315 .mask = 0x7,
1316 .shift = 16,
1317 },
1318 .hw.init = &(struct clk_init_data){
1319 .name = "vclk2_sel",
1320 .ops = &clk_regmap_mux_ops,
1321 .parent_hws = axg_vclk_parent_hws,
1322 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws),
1323 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1324 },
1325 };
1326
1327 static struct clk_regmap axg_vclk_input = {
1328 .data = &(struct clk_regmap_gate_data){
1329 .offset = HHI_VID_CLK_DIV,
1330 .bit_idx = 16,
1331 },
1332 .hw.init = &(struct clk_init_data) {
1333 .name = "vclk_input",
1334 .ops = &clk_regmap_gate_ops,
1335 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_sel.hw },
1336 .num_parents = 1,
1337 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1338 },
1339 };
1340
1341 static struct clk_regmap axg_vclk2_input = {
1342 .data = &(struct clk_regmap_gate_data){
1343 .offset = HHI_VIID_CLK_DIV,
1344 .bit_idx = 16,
1345 },
1346 .hw.init = &(struct clk_init_data) {
1347 .name = "vclk2_input",
1348 .ops = &clk_regmap_gate_ops,
1349 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_sel.hw },
1350 .num_parents = 1,
1351 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1352 },
1353 };
1354
1355 static struct clk_regmap axg_vclk_div = {
1356 .data = &(struct clk_regmap_div_data){
1357 .offset = HHI_VID_CLK_DIV,
1358 .shift = 0,
1359 .width = 8,
1360 },
1361 .hw.init = &(struct clk_init_data){
1362 .name = "vclk_div",
1363 .ops = &clk_regmap_divider_ops,
1364 .parent_hws = (const struct clk_hw *[]) {
1365 &axg_vclk_input.hw
1366 },
1367 .num_parents = 1,
1368 .flags = CLK_GET_RATE_NOCACHE,
1369 },
1370 };
1371
1372 static struct clk_regmap axg_vclk2_div = {
1373 .data = &(struct clk_regmap_div_data){
1374 .offset = HHI_VIID_CLK_DIV,
1375 .shift = 0,
1376 .width = 8,
1377 },
1378 .hw.init = &(struct clk_init_data){
1379 .name = "vclk2_div",
1380 .ops = &clk_regmap_divider_ops,
1381 .parent_hws = (const struct clk_hw *[]) {
1382 &axg_vclk2_input.hw
1383 },
1384 .num_parents = 1,
1385 .flags = CLK_GET_RATE_NOCACHE,
1386 },
1387 };
1388
1389 static struct clk_regmap axg_vclk = {
1390 .data = &(struct clk_regmap_gate_data){
1391 .offset = HHI_VID_CLK_CNTL,
1392 .bit_idx = 19,
1393 },
1394 .hw.init = &(struct clk_init_data) {
1395 .name = "vclk",
1396 .ops = &clk_regmap_gate_ops,
1397 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_div.hw },
1398 .num_parents = 1,
1399 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1400 },
1401 };
1402
1403 static struct clk_regmap axg_vclk2 = {
1404 .data = &(struct clk_regmap_gate_data){
1405 .offset = HHI_VIID_CLK_CNTL,
1406 .bit_idx = 19,
1407 },
1408 .hw.init = &(struct clk_init_data) {
1409 .name = "vclk2",
1410 .ops = &clk_regmap_gate_ops,
1411 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_div.hw },
1412 .num_parents = 1,
1413 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1414 },
1415 };
1416
1417 static struct clk_regmap axg_vclk_div1 = {
1418 .data = &(struct clk_regmap_gate_data){
1419 .offset = HHI_VID_CLK_CNTL,
1420 .bit_idx = 0,
1421 },
1422 .hw.init = &(struct clk_init_data) {
1423 .name = "vclk_div1",
1424 .ops = &clk_regmap_gate_ops,
1425 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1426 .num_parents = 1,
1427 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1428 },
1429 };
1430
1431 static struct clk_regmap axg_vclk_div2_en = {
1432 .data = &(struct clk_regmap_gate_data){
1433 .offset = HHI_VID_CLK_CNTL,
1434 .bit_idx = 1,
1435 },
1436 .hw.init = &(struct clk_init_data) {
1437 .name = "vclk_div2_en",
1438 .ops = &clk_regmap_gate_ops,
1439 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1440 .num_parents = 1,
1441 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1442 },
1443 };
1444
1445 static struct clk_regmap axg_vclk_div4_en = {
1446 .data = &(struct clk_regmap_gate_data){
1447 .offset = HHI_VID_CLK_CNTL,
1448 .bit_idx = 2,
1449 },
1450 .hw.init = &(struct clk_init_data) {
1451 .name = "vclk_div4_en",
1452 .ops = &clk_regmap_gate_ops,
1453 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1454 .num_parents = 1,
1455 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1456 },
1457 };
1458
1459 static struct clk_regmap axg_vclk_div6_en = {
1460 .data = &(struct clk_regmap_gate_data){
1461 .offset = HHI_VID_CLK_CNTL,
1462 .bit_idx = 3,
1463 },
1464 .hw.init = &(struct clk_init_data) {
1465 .name = "vclk_div6_en",
1466 .ops = &clk_regmap_gate_ops,
1467 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1468 .num_parents = 1,
1469 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1470 },
1471 };
1472
1473 static struct clk_regmap axg_vclk_div12_en = {
1474 .data = &(struct clk_regmap_gate_data){
1475 .offset = HHI_VID_CLK_CNTL,
1476 .bit_idx = 4,
1477 },
1478 .hw.init = &(struct clk_init_data) {
1479 .name = "vclk_div12_en",
1480 .ops = &clk_regmap_gate_ops,
1481 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1482 .num_parents = 1,
1483 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1484 },
1485 };
1486
1487 static struct clk_regmap axg_vclk2_div1 = {
1488 .data = &(struct clk_regmap_gate_data){
1489 .offset = HHI_VIID_CLK_CNTL,
1490 .bit_idx = 0,
1491 },
1492 .hw.init = &(struct clk_init_data) {
1493 .name = "vclk2_div1",
1494 .ops = &clk_regmap_gate_ops,
1495 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1496 .num_parents = 1,
1497 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1498 },
1499 };
1500
1501 static struct clk_regmap axg_vclk2_div2_en = {
1502 .data = &(struct clk_regmap_gate_data){
1503 .offset = HHI_VIID_CLK_CNTL,
1504 .bit_idx = 1,
1505 },
1506 .hw.init = &(struct clk_init_data) {
1507 .name = "vclk2_div2_en",
1508 .ops = &clk_regmap_gate_ops,
1509 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1510 .num_parents = 1,
1511 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1512 },
1513 };
1514
1515 static struct clk_regmap axg_vclk2_div4_en = {
1516 .data = &(struct clk_regmap_gate_data){
1517 .offset = HHI_VIID_CLK_CNTL,
1518 .bit_idx = 2,
1519 },
1520 .hw.init = &(struct clk_init_data) {
1521 .name = "vclk2_div4_en",
1522 .ops = &clk_regmap_gate_ops,
1523 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1524 .num_parents = 1,
1525 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1526 },
1527 };
1528
1529 static struct clk_regmap axg_vclk2_div6_en = {
1530 .data = &(struct clk_regmap_gate_data){
1531 .offset = HHI_VIID_CLK_CNTL,
1532 .bit_idx = 3,
1533 },
1534 .hw.init = &(struct clk_init_data) {
1535 .name = "vclk2_div6_en",
1536 .ops = &clk_regmap_gate_ops,
1537 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1538 .num_parents = 1,
1539 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1540 },
1541 };
1542
1543 static struct clk_regmap axg_vclk2_div12_en = {
1544 .data = &(struct clk_regmap_gate_data){
1545 .offset = HHI_VIID_CLK_CNTL,
1546 .bit_idx = 4,
1547 },
1548 .hw.init = &(struct clk_init_data) {
1549 .name = "vclk2_div12_en",
1550 .ops = &clk_regmap_gate_ops,
1551 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1552 .num_parents = 1,
1553 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1554 },
1555 };
1556
1557 static struct clk_fixed_factor axg_vclk_div2 = {
1558 .mult = 1,
1559 .div = 2,
1560 .hw.init = &(struct clk_init_data){
1561 .name = "vclk_div2",
1562 .ops = &clk_fixed_factor_ops,
1563 .parent_hws = (const struct clk_hw *[]) {
1564 &axg_vclk_div2_en.hw
1565 },
1566 .num_parents = 1,
1567 },
1568 };
1569
1570 static struct clk_fixed_factor axg_vclk_div4 = {
1571 .mult = 1,
1572 .div = 4,
1573 .hw.init = &(struct clk_init_data){
1574 .name = "vclk_div4",
1575 .ops = &clk_fixed_factor_ops,
1576 .parent_hws = (const struct clk_hw *[]) {
1577 &axg_vclk_div4_en.hw
1578 },
1579 .num_parents = 1,
1580 },
1581 };
1582
1583 static struct clk_fixed_factor axg_vclk_div6 = {
1584 .mult = 1,
1585 .div = 6,
1586 .hw.init = &(struct clk_init_data){
1587 .name = "vclk_div6",
1588 .ops = &clk_fixed_factor_ops,
1589 .parent_hws = (const struct clk_hw *[]) {
1590 &axg_vclk_div6_en.hw
1591 },
1592 .num_parents = 1,
1593 },
1594 };
1595
1596 static struct clk_fixed_factor axg_vclk_div12 = {
1597 .mult = 1,
1598 .div = 12,
1599 .hw.init = &(struct clk_init_data){
1600 .name = "vclk_div12",
1601 .ops = &clk_fixed_factor_ops,
1602 .parent_hws = (const struct clk_hw *[]) {
1603 &axg_vclk_div12_en.hw
1604 },
1605 .num_parents = 1,
1606 },
1607 };
1608
1609 static struct clk_fixed_factor axg_vclk2_div2 = {
1610 .mult = 1,
1611 .div = 2,
1612 .hw.init = &(struct clk_init_data){
1613 .name = "vclk2_div2",
1614 .ops = &clk_fixed_factor_ops,
1615 .parent_hws = (const struct clk_hw *[]) {
1616 &axg_vclk2_div2_en.hw
1617 },
1618 .num_parents = 1,
1619 },
1620 };
1621
1622 static struct clk_fixed_factor axg_vclk2_div4 = {
1623 .mult = 1,
1624 .div = 4,
1625 .hw.init = &(struct clk_init_data){
1626 .name = "vclk2_div4",
1627 .ops = &clk_fixed_factor_ops,
1628 .parent_hws = (const struct clk_hw *[]) {
1629 &axg_vclk2_div4_en.hw
1630 },
1631 .num_parents = 1,
1632 },
1633 };
1634
1635 static struct clk_fixed_factor axg_vclk2_div6 = {
1636 .mult = 1,
1637 .div = 6,
1638 .hw.init = &(struct clk_init_data){
1639 .name = "vclk2_div6",
1640 .ops = &clk_fixed_factor_ops,
1641 .parent_hws = (const struct clk_hw *[]) {
1642 &axg_vclk2_div6_en.hw
1643 },
1644 .num_parents = 1,
1645 },
1646 };
1647
1648 static struct clk_fixed_factor axg_vclk2_div12 = {
1649 .mult = 1,
1650 .div = 12,
1651 .hw.init = &(struct clk_init_data){
1652 .name = "vclk2_div12",
1653 .ops = &clk_fixed_factor_ops,
1654 .parent_hws = (const struct clk_hw *[]) {
1655 &axg_vclk2_div12_en.hw
1656 },
1657 .num_parents = 1,
1658 },
1659 };
1660
1661 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1662 static const struct clk_hw *axg_cts_parent_hws[] = {
1663 &axg_vclk_div1.hw,
1664 &axg_vclk_div2.hw,
1665 &axg_vclk_div4.hw,
1666 &axg_vclk_div6.hw,
1667 &axg_vclk_div12.hw,
1668 &axg_vclk2_div1.hw,
1669 &axg_vclk2_div2.hw,
1670 &axg_vclk2_div4.hw,
1671 &axg_vclk2_div6.hw,
1672 &axg_vclk2_div12.hw,
1673 };
1674
1675 static struct clk_regmap axg_cts_encl_sel = {
1676 .data = &(struct clk_regmap_mux_data){
1677 .offset = HHI_VIID_CLK_DIV,
1678 .mask = 0xf,
1679 .shift = 12,
1680 .table = mux_table_cts_sel,
1681 },
1682 .hw.init = &(struct clk_init_data){
1683 .name = "cts_encl_sel",
1684 .ops = &clk_regmap_mux_ops,
1685 .parent_hws = axg_cts_parent_hws,
1686 .num_parents = ARRAY_SIZE(axg_cts_parent_hws),
1687 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1688 },
1689 };
1690
1691 static struct clk_regmap axg_cts_encl = {
1692 .data = &(struct clk_regmap_gate_data){
1693 .offset = HHI_VID_CLK_CNTL2,
1694 .bit_idx = 3,
1695 },
1696 .hw.init = &(struct clk_init_data) {
1697 .name = "cts_encl",
1698 .ops = &clk_regmap_gate_ops,
1699 .parent_hws = (const struct clk_hw *[]) {
1700 &axg_cts_encl_sel.hw
1701 },
1702 .num_parents = 1,
1703 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1704 },
1705 };
1706
1707 /* MIPI DSI Host Clock */
1708
1709 static u32 mux_table_axg_vdin_meas[] = { 0, 1, 2, 3, 6, 7 };
1710 static const struct clk_parent_data axg_vdin_meas_parent_data[] = {
1711 { .fw_name = "xtal", },
1712 { .hw = &axg_fclk_div4.hw },
1713 { .hw = &axg_fclk_div3.hw },
1714 { .hw = &axg_fclk_div5.hw },
1715 { .hw = &axg_fclk_div2.hw },
1716 { .hw = &axg_fclk_div7.hw },
1717 };
1718
1719 static struct clk_regmap axg_vdin_meas_sel = {
1720 .data = &(struct clk_regmap_mux_data){
1721 .offset = HHI_VDIN_MEAS_CLK_CNTL,
1722 .mask = 0x7,
1723 .shift = 21,
1724 .flags = CLK_MUX_ROUND_CLOSEST,
1725 .table = mux_table_axg_vdin_meas,
1726 },
1727 .hw.init = &(struct clk_init_data){
1728 .name = "vdin_meas_sel",
1729 .ops = &clk_regmap_mux_ops,
1730 .parent_data = axg_vdin_meas_parent_data,
1731 .num_parents = ARRAY_SIZE(axg_vdin_meas_parent_data),
1732 .flags = CLK_SET_RATE_PARENT,
1733 },
1734 };
1735
1736 static struct clk_regmap axg_vdin_meas_div = {
1737 .data = &(struct clk_regmap_div_data){
1738 .offset = HHI_VDIN_MEAS_CLK_CNTL,
1739 .shift = 12,
1740 .width = 7,
1741 },
1742 .hw.init = &(struct clk_init_data){
1743 .name = "vdin_meas_div",
1744 .ops = &clk_regmap_divider_ops,
1745 .parent_hws = (const struct clk_hw *[]) {
1746 &axg_vdin_meas_sel.hw },
1747 .num_parents = 1,
1748 .flags = CLK_SET_RATE_PARENT,
1749 },
1750 };
1751
1752 static struct clk_regmap axg_vdin_meas = {
1753 .data = &(struct clk_regmap_gate_data){
1754 .offset = HHI_VDIN_MEAS_CLK_CNTL,
1755 .bit_idx = 20,
1756 },
1757 .hw.init = &(struct clk_init_data) {
1758 .name = "vdin_meas",
1759 .ops = &clk_regmap_gate_ops,
1760 .parent_hws = (const struct clk_hw *[]) {
1761 &axg_vdin_meas_div.hw },
1762 .num_parents = 1,
1763 .flags = CLK_SET_RATE_PARENT,
1764 },
1765 };
1766
1767 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
1768 9, 10, 11, 13, 14, };
1769 static const struct clk_parent_data gen_clk_parent_data[] = {
1770 { .fw_name = "xtal", },
1771 { .hw = &axg_hifi_pll.hw },
1772 { .hw = &axg_mpll0.hw },
1773 { .hw = &axg_mpll1.hw },
1774 { .hw = &axg_mpll2.hw },
1775 { .hw = &axg_mpll3.hw },
1776 { .hw = &axg_fclk_div4.hw },
1777 { .hw = &axg_fclk_div3.hw },
1778 { .hw = &axg_fclk_div5.hw },
1779 { .hw = &axg_fclk_div7.hw },
1780 { .hw = &axg_gp0_pll.hw },
1781 };
1782
1783 static struct clk_regmap axg_gen_clk_sel = {
1784 .data = &(struct clk_regmap_mux_data){
1785 .offset = HHI_GEN_CLK_CNTL,
1786 .mask = 0xf,
1787 .shift = 12,
1788 .table = mux_table_gen_clk,
1789 },
1790 .hw.init = &(struct clk_init_data){
1791 .name = "gen_clk_sel",
1792 .ops = &clk_regmap_mux_ops,
1793 /*
1794 * bits 15:12 selects from 14 possible parents:
1795 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
1796 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
1797 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
1798 */
1799 .parent_data = gen_clk_parent_data,
1800 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
1801 },
1802 };
1803
1804 static struct clk_regmap axg_gen_clk_div = {
1805 .data = &(struct clk_regmap_div_data){
1806 .offset = HHI_GEN_CLK_CNTL,
1807 .shift = 0,
1808 .width = 11,
1809 },
1810 .hw.init = &(struct clk_init_data){
1811 .name = "gen_clk_div",
1812 .ops = &clk_regmap_divider_ops,
1813 .parent_hws = (const struct clk_hw *[]) {
1814 &axg_gen_clk_sel.hw
1815 },
1816 .num_parents = 1,
1817 .flags = CLK_SET_RATE_PARENT,
1818 },
1819 };
1820
1821 static struct clk_regmap axg_gen_clk = {
1822 .data = &(struct clk_regmap_gate_data){
1823 .offset = HHI_GEN_CLK_CNTL,
1824 .bit_idx = 7,
1825 },
1826 .hw.init = &(struct clk_init_data){
1827 .name = "gen_clk",
1828 .ops = &clk_regmap_gate_ops,
1829 .parent_hws = (const struct clk_hw *[]) {
1830 &axg_gen_clk_div.hw
1831 },
1832 .num_parents = 1,
1833 .flags = CLK_SET_RATE_PARENT,
1834 },
1835 };
1836
1837 #define MESON_GATE(_name, _reg, _bit) \
1838 MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
1839
1840 /* Everything Else (EE) domain gates */
1841 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
1842 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
1843 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
1844 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
1845 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
1846 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
1847 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
1848 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
1849 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
1850 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
1851 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
1852 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
1853 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
1854 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
1855 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
1856 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
1857 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
1858 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
1859 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
1860 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
1861
1862 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
1863 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
1864 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
1865 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
1866 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
1867 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
1868 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
1869 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
1870 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
1871 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
1872 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
1873
1874 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1875 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1876 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
1877 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
1878 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
1879 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
1880 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1881 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
1882 static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
1883
1884 /* Always On (AO) domain gates */
1885
1886 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
1887 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
1888 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
1889 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
1890 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
1891
1892 /* Array of all clocks provided by this provider */
1893
1894 static struct clk_hw_onecell_data axg_hw_onecell_data = {
1895 .hws = {
1896 [CLKID_SYS_PLL] = &axg_sys_pll.hw,
1897 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
1898 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
1899 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
1900 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
1901 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
1902 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
1903 [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
1904 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
1905 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
1906 [CLKID_CLK81] = &axg_clk81.hw,
1907 [CLKID_MPLL0] = &axg_mpll0.hw,
1908 [CLKID_MPLL1] = &axg_mpll1.hw,
1909 [CLKID_MPLL2] = &axg_mpll2.hw,
1910 [CLKID_MPLL3] = &axg_mpll3.hw,
1911 [CLKID_DDR] = &axg_ddr.hw,
1912 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
1913 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
1914 [CLKID_ISA] = &axg_isa.hw,
1915 [CLKID_PL301] = &axg_pl301.hw,
1916 [CLKID_PERIPHS] = &axg_periphs.hw,
1917 [CLKID_SPICC0] = &axg_spicc_0.hw,
1918 [CLKID_I2C] = &axg_i2c.hw,
1919 [CLKID_RNG0] = &axg_rng0.hw,
1920 [CLKID_UART0] = &axg_uart0.hw,
1921 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
1922 [CLKID_SPICC1] = &axg_spicc_1.hw,
1923 [CLKID_PCIE_A] = &axg_pcie_a.hw,
1924 [CLKID_PCIE_B] = &axg_pcie_b.hw,
1925 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
1926 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
1927 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
1928 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
1929 [CLKID_DMA] = &axg_dma.hw,
1930 [CLKID_SPI] = &axg_spi.hw,
1931 [CLKID_AUDIO] = &axg_audio.hw,
1932 [CLKID_ETH] = &axg_eth_core.hw,
1933 [CLKID_UART1] = &axg_uart1.hw,
1934 [CLKID_G2D] = &axg_g2d.hw,
1935 [CLKID_USB0] = &axg_usb0.hw,
1936 [CLKID_USB1] = &axg_usb1.hw,
1937 [CLKID_RESET] = &axg_reset.hw,
1938 [CLKID_USB] = &axg_usb_general.hw,
1939 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
1940 [CLKID_EFUSE] = &axg_efuse.hw,
1941 [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
1942 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
1943 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
1944 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
1945 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
1946 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
1947 [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
1948 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
1949 [CLKID_GIC] = &axg_gic.hw,
1950 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
1951 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
1952 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
1953 [CLKID_AO_IFACE] = &axg_ao_iface.hw,
1954 [CLKID_AO_I2C] = &axg_ao_i2c.hw,
1955 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
1956 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
1957 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
1958 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
1959 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
1960 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
1961 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
1962 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
1963 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
1964 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
1965 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
1966 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
1967 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
1968 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
1969 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
1970 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
1971 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
1972 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
1973 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
1974 [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
1975 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
1976 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
1977 [CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw,
1978 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
1979 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
1980 [CLKID_GEN_CLK] = &axg_gen_clk.hw,
1981 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
1982 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
1983 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
1984 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
1985 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
1986 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
1987 [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
1988 [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
1989 [CLKID_VPU_0] = &axg_vpu_0.hw,
1990 [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
1991 [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
1992 [CLKID_VPU_1] = &axg_vpu_1.hw,
1993 [CLKID_VPU] = &axg_vpu.hw,
1994 [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
1995 [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
1996 [CLKID_VAPB_0] = &axg_vapb_0.hw,
1997 [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
1998 [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
1999 [CLKID_VAPB_1] = &axg_vapb_1.hw,
2000 [CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
2001 [CLKID_VAPB] = &axg_vapb.hw,
2002 [CLKID_VCLK] = &axg_vclk.hw,
2003 [CLKID_VCLK2] = &axg_vclk2.hw,
2004 [CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
2005 [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
2006 [CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
2007 [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
2008 [CLKID_VCLK_DIV] = &axg_vclk_div.hw,
2009 [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
2010 [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
2011 [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
2012 [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
2013 [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
2014 [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
2015 [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
2016 [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
2017 [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
2018 [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
2019 [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
2020 [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
2021 [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
2022 [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
2023 [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
2024 [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
2025 [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
2026 [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
2027 [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
2028 [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
2029 [CLKID_CTS_ENCL] = &axg_cts_encl.hw,
2030 [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
2031 [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
2032 [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
2033 [NR_CLKS] = NULL,
2034 },
2035 .num = NR_CLKS,
2036 };
2037
2038 /* Convenience table to populate regmap in .probe */
2039 static struct clk_regmap *const axg_clk_regmaps[] = {
2040 &axg_clk81,
2041 &axg_ddr,
2042 &axg_audio_locker,
2043 &axg_mipi_dsi_host,
2044 &axg_isa,
2045 &axg_pl301,
2046 &axg_periphs,
2047 &axg_spicc_0,
2048 &axg_i2c,
2049 &axg_rng0,
2050 &axg_uart0,
2051 &axg_mipi_dsi_phy,
2052 &axg_spicc_1,
2053 &axg_pcie_a,
2054 &axg_pcie_b,
2055 &axg_hiu_reg,
2056 &axg_assist_misc,
2057 &axg_emmc_b,
2058 &axg_emmc_c,
2059 &axg_dma,
2060 &axg_spi,
2061 &axg_audio,
2062 &axg_eth_core,
2063 &axg_uart1,
2064 &axg_g2d,
2065 &axg_usb0,
2066 &axg_usb1,
2067 &axg_reset,
2068 &axg_usb_general,
2069 &axg_ahb_arb0,
2070 &axg_efuse,
2071 &axg_boot_rom,
2072 &axg_ahb_data_bus,
2073 &axg_ahb_ctrl_bus,
2074 &axg_usb1_to_ddr,
2075 &axg_usb0_to_ddr,
2076 &axg_mmc_pclk,
2077 &axg_vpu_intr,
2078 &axg_sec_ahb_ahb3_bridge,
2079 &axg_gic,
2080 &axg_ao_media_cpu,
2081 &axg_ao_ahb_sram,
2082 &axg_ao_ahb_bus,
2083 &axg_ao_iface,
2084 &axg_ao_i2c,
2085 &axg_sd_emmc_b_clk0,
2086 &axg_sd_emmc_c_clk0,
2087 &axg_mpeg_clk_div,
2088 &axg_sd_emmc_b_clk0_div,
2089 &axg_sd_emmc_c_clk0_div,
2090 &axg_mpeg_clk_sel,
2091 &axg_sd_emmc_b_clk0_sel,
2092 &axg_sd_emmc_c_clk0_sel,
2093 &axg_mpll0,
2094 &axg_mpll1,
2095 &axg_mpll2,
2096 &axg_mpll3,
2097 &axg_mpll0_div,
2098 &axg_mpll1_div,
2099 &axg_mpll2_div,
2100 &axg_mpll3_div,
2101 &axg_fixed_pll,
2102 &axg_sys_pll,
2103 &axg_gp0_pll,
2104 &axg_hifi_pll,
2105 &axg_mpll_prediv,
2106 &axg_fclk_div2,
2107 &axg_fclk_div3,
2108 &axg_fclk_div4,
2109 &axg_fclk_div5,
2110 &axg_fclk_div7,
2111 &axg_pcie_pll_dco,
2112 &axg_pcie_pll_od,
2113 &axg_pcie_pll,
2114 &axg_pcie_mux,
2115 &axg_pcie_ref,
2116 &axg_pcie_cml_en0,
2117 &axg_pcie_cml_en1,
2118 &axg_mipi_enable,
2119 &axg_gen_clk_sel,
2120 &axg_gen_clk_div,
2121 &axg_gen_clk,
2122 &axg_fixed_pll_dco,
2123 &axg_sys_pll_dco,
2124 &axg_gp0_pll_dco,
2125 &axg_hifi_pll_dco,
2126 &axg_pcie_pll_dco,
2127 &axg_pcie_pll_od,
2128 &axg_vpu_0_div,
2129 &axg_vpu_0_sel,
2130 &axg_vpu_0,
2131 &axg_vpu_1_div,
2132 &axg_vpu_1_sel,
2133 &axg_vpu_1,
2134 &axg_vpu,
2135 &axg_vapb_0_div,
2136 &axg_vapb_0_sel,
2137 &axg_vapb_0,
2138 &axg_vapb_1_div,
2139 &axg_vapb_1_sel,
2140 &axg_vapb_1,
2141 &axg_vapb_sel,
2142 &axg_vapb,
2143 &axg_vclk,
2144 &axg_vclk2,
2145 &axg_vclk_sel,
2146 &axg_vclk2_sel,
2147 &axg_vclk_input,
2148 &axg_vclk2_input,
2149 &axg_vclk_div,
2150 &axg_vclk2_div,
2151 &axg_vclk_div2_en,
2152 &axg_vclk_div4_en,
2153 &axg_vclk_div6_en,
2154 &axg_vclk_div12_en,
2155 &axg_vclk2_div2_en,
2156 &axg_vclk2_div4_en,
2157 &axg_vclk2_div6_en,
2158 &axg_vclk2_div12_en,
2159 &axg_cts_encl_sel,
2160 &axg_cts_encl,
2161 &axg_vdin_meas_sel,
2162 &axg_vdin_meas_div,
2163 &axg_vdin_meas,
2164 };
2165
2166 static const struct meson_eeclkc_data axg_clkc_data = {
2167 .regmap_clks = axg_clk_regmaps,
2168 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
2169 .hw_onecell_data = &axg_hw_onecell_data,
2170 };
2171
2172
2173 static const struct of_device_id clkc_match_table[] = {
2174 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
2175 {}
2176 };
2177 MODULE_DEVICE_TABLE(of, clkc_match_table);
2178
2179 static struct platform_driver axg_driver = {
2180 .probe = meson_eeclkc_probe,
2181 .driver = {
2182 .name = "axg-clkc",
2183 .of_match_table = clkc_match_table,
2184 },
2185 };
2186
2187 module_platform_driver(axg_driver);
2188 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support