drivers/clk/samsung/clk-exynos-audss.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   4  * Author: Padmavathi Venna <padma.v@samsung.com>
   5  *
   6  * Common Clock Framework support for Audio Subsystem Clock Controller.
   7 */
   8
   9 #include <linux/slab.h>
  10 #include <linux/io.h>
  11 #include <linux/clk.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_device.h>
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18
  19 #include <dt-bindings/clock/exynos-audss-clk.h>
  20
  21 static DEFINE_SPINLOCK(lock);
  22 static void __iomem *reg_base;
  23 static struct clk_hw_onecell_data *clk_data;
  24 /*
  25  * On Exynos5420 this will be a clock which has to be enabled before any
  26  * access to audss registers. Typically a child of EPLL.
  27  *
  28  * On other platforms this will be -ENODEV.
  29  */
  30 static struct clk *epll;
  31
  32 #define ASS_CLK_SRC 0x0
  33 #define ASS_CLK_DIV 0x4
  34 #define ASS_CLK_GATE 0x8
  35
  36 static unsigned long reg_save[][2] = {
  37         { ASS_CLK_SRC,  0 },
  38         { ASS_CLK_DIV,  0 },
  39         { ASS_CLK_GATE, 0 },
  40 };
  41
  42 static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)
  43 {
  44         int i;
  45
  46         for (i = 0; i < ARRAY_SIZE(reg_save); i++)
  47                 reg_save[i][1] = readl(reg_base + reg_save[i][0]);
  48
  49         return 0;
  50 }
  51
  52 static int __maybe_unused exynos_audss_clk_resume(struct device *dev)
  53 {
  54         int i;
  55
  56         for (i = 0; i < ARRAY_SIZE(reg_save); i++)
  57                 writel(reg_save[i][1], reg_base + reg_save[i][0]);
  58
  59         return 0;
  60 }
  61
  62 struct exynos_audss_clk_drvdata {
  63         unsigned int has_adma_clk:1;
  64         unsigned int has_mst_clk:1;
  65         unsigned int enable_epll:1;
  66         unsigned int num_clks;
  67 };
  68
  69 static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
  70         .num_clks       = EXYNOS_AUDSS_MAX_CLKS - 1,
  71         .enable_epll    = 1,
  72 };
  73
  74 static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
  75         .num_clks       = EXYNOS_AUDSS_MAX_CLKS - 1,
  76         .has_mst_clk    = 1,
  77 };
  78
  79 static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
  80         .num_clks       = EXYNOS_AUDSS_MAX_CLKS,
  81         .has_adma_clk   = 1,
  82         .enable_epll    = 1,
  83 };
  84
  85 static const struct of_device_id exynos_audss_clk_of_match[] = {
  86         {
  87                 .compatible     = "samsung,exynos4210-audss-clock",
  88                 .data           = &exynos4210_drvdata,
  89         }, {
  90                 .compatible     = "samsung,exynos5250-audss-clock",
  91                 .data           = &exynos4210_drvdata,
  92         }, {
  93                 .compatible     = "samsung,exynos5410-audss-clock",
  94                 .data           = &exynos5410_drvdata,
  95         }, {
  96                 .compatible     = "samsung,exynos5420-audss-clock",
  97                 .data           = &exynos5420_drvdata,
  98         },
  99         { },
 100 };
 101 MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
 102
 103 static void exynos_audss_clk_teardown(void)
 104 {
 105         int i;
 106
 107         for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
 108                 if (!IS_ERR(clk_data->hws[i]))
 109                         clk_hw_unregister_mux(clk_data->hws[i]);
 110         }
 111
 112         for (; i < EXYNOS_SRP_CLK; i++) {
 113                 if (!IS_ERR(clk_data->hws[i]))
 114                         clk_hw_unregister_divider(clk_data->hws[i]);
 115         }
 116
 117         for (; i < clk_data->num; i++) {
 118                 if (!IS_ERR(clk_data->hws[i]))
 119                         clk_hw_unregister_gate(clk_data->hws[i]);
 120         }
 121 }
 122
 123 /* register exynos_audss clocks */
 124 static int exynos_audss_clk_probe(struct platform_device *pdev)
 125 {
 126         const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
 127         const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
 128         const char *sclk_pcm_p = "sclk_pcm0";
 129         struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
 130         const struct exynos_audss_clk_drvdata *variant;
 131         struct clk_hw **clk_table;
 132         struct resource *res;
 133         struct device *dev = &pdev->dev;
 134         int i, ret = 0;
 135
 136         variant = of_device_get_match_data(&pdev->dev);
 137         if (!variant)
 138                 return -EINVAL;
 139
 140         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 141         reg_base = devm_ioremap_resource(dev, res);
 142         if (IS_ERR(reg_base))
 143                 return PTR_ERR(reg_base);
 144
 145         epll = ERR_PTR(-ENODEV);
 146
 147         clk_data = devm_kzalloc(dev,
 148                                 struct_size(clk_data, hws,
 149                                             EXYNOS_AUDSS_MAX_CLKS),
 150                                 GFP_KERNEL);
 151         if (!clk_data)
 152                 return -ENOMEM;
 153
 154         clk_data->num = variant->num_clks;
 155         clk_table = clk_data->hws;
 156
 157         pll_ref = devm_clk_get(dev, "pll_ref");
 158         pll_in = devm_clk_get(dev, "pll_in");
 159         if (!IS_ERR(pll_ref))
 160                 mout_audss_p[0] = __clk_get_name(pll_ref);
 161         if (!IS_ERR(pll_in)) {
 162                 mout_audss_p[1] = __clk_get_name(pll_in);
 163
 164                 if (variant->enable_epll) {
 165                         epll = pll_in;
 166
 167                         ret = clk_prepare_enable(epll);
 168                         if (ret) {
 169                                 dev_err(dev,
 170                                         "failed to prepare the epll clock\n");
 171                                 return ret;
 172                         }
 173                 }
 174         }
 175
 176         /*
 177          * Enable runtime PM here to allow the clock core using runtime PM
 178          * for the registered clocks. Additionally, we increase the runtime
 179          * PM usage count before registering the clocks, to prevent the
 180          * clock core from runtime suspending the device.
 181          */
 182         pm_runtime_get_noresume(dev);
 183         pm_runtime_set_active(dev);
 184         pm_runtime_enable(dev);
 185
 186         clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
 187                                 mout_audss_p, ARRAY_SIZE(mout_audss_p),
 188                                 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
 189                                 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
 190
 191         cdclk = devm_clk_get(dev, "cdclk");
 192         sclk_audio = devm_clk_get(dev, "sclk_audio");
 193         if (!IS_ERR(cdclk))
 194                 mout_i2s_p[1] = __clk_get_name(cdclk);
 195         if (!IS_ERR(sclk_audio))
 196                 mout_i2s_p[2] = __clk_get_name(sclk_audio);
 197         clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
 198                                 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
 199                                 CLK_SET_RATE_NO_REPARENT,
 200                                 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
 201
 202         clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
 203                                 "mout_audss", CLK_SET_RATE_PARENT,
 204                                 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
 205
 206         clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
 207                                 "dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
 208                                 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
 209
 210         clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
 211                                 "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
 212                                 &lock);
 213
 214         clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
 215                                 "dout_srp", CLK_SET_RATE_PARENT,
 216                                 reg_base + ASS_CLK_GATE, 0, 0, &lock);
 217
 218         clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
 219                                 "dout_aud_bus", CLK_SET_RATE_PARENT,
 220                                 reg_base + ASS_CLK_GATE, 2, 0, &lock);
 221
 222         clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
 223                                 "dout_i2s", CLK_SET_RATE_PARENT,
 224                                 reg_base + ASS_CLK_GATE, 3, 0, &lock);
 225
 226         clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
 227                                  "sclk_pcm", CLK_SET_RATE_PARENT,
 228                                 reg_base + ASS_CLK_GATE, 4, 0, &lock);
 229
 230         sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in");
 231         if (!IS_ERR(sclk_pcm_in))
 232                 sclk_pcm_p = __clk_get_name(sclk_pcm_in);
 233         clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
 234                                 sclk_pcm_p, CLK_SET_RATE_PARENT,
 235                                 reg_base + ASS_CLK_GATE, 5, 0, &lock);
 236
 237         if (variant->has_adma_clk) {
 238                 clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
 239                                 "dout_srp", CLK_SET_RATE_PARENT,
 240                                 reg_base + ASS_CLK_GATE, 9, 0, &lock);
 241         }
 242
 243         for (i = 0; i < clk_data->num; i++) {
 244                 if (IS_ERR(clk_table[i])) {
 245                         dev_err(dev, "failed to register clock %d\n", i);
 246                         ret = PTR_ERR(clk_table[i]);
 247                         goto unregister;
 248                 }
 249         }
 250
 251         ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
 252                                      clk_data);
 253         if (ret) {
 254                 dev_err(dev, "failed to add clock provider\n");
 255                 goto unregister;
 256         }
 257
 258         pm_runtime_put_sync(dev);
 259
 260         return 0;
 261
 262 unregister:
 263         exynos_audss_clk_teardown();
 264         pm_runtime_put_sync(dev);
 265         pm_runtime_disable(dev);
 266
 267         if (!IS_ERR(epll))
 268                 clk_disable_unprepare(epll);
 269
 270         return ret;
 271 }
 272
 273 static int exynos_audss_clk_remove(struct platform_device *pdev)
 274 {
 275         of_clk_del_provider(pdev->dev.of_node);
 276
 277         exynos_audss_clk_teardown();
 278         pm_runtime_disable(&pdev->dev);
 279
 280         if (!IS_ERR(epll))
 281                 clk_disable_unprepare(epll);
 282
 283         return 0;
 284 }
 285
 286 static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
 287         SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume,
 288                            NULL)
 289         SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 290                                      pm_runtime_force_resume)
 291 };
 292
 293 static struct platform_driver exynos_audss_clk_driver = {
 294         .driver = {
 295                 .name = "exynos-audss-clk",
 296                 .of_match_table = exynos_audss_clk_of_match,
 297                 .pm = &exynos_audss_clk_pm_ops,
 298         },
 299         .probe = exynos_audss_clk_probe,
 300         .remove = exynos_audss_clk_remove,
 301 };
 302
 303 module_platform_driver(exynos_audss_clk_driver);
 304
 305 MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
 306 MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
 307 MODULE_LICENSE("GPL v2");
 308 MODULE_ALIAS("platform:exynos-audss-clk");