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WIP FPC-III support
[linux/fpc-iii.git] / drivers / clk / samsung / clk-exynos4.c
blobbf13e29a655c727402939a6be2a406831f0078b2
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * Copyright (c) 2013 Linaro Ltd.
5 * Author: Thomas Abraham <thomas.ab@samsung.com>
6 *
7 * Common Clock Framework support for all Exynos4 SoCs.
8 */
9
10 #include <dt-bindings/clock/exynos4.h>
11 #include <linux/slab.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/io.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17
18 #include "clk.h"
19 #include "clk-cpu.h"
20
21 /* Exynos4 clock controller register offsets */
22 #define SRC_LEFTBUS 0x4200
23 #define DIV_LEFTBUS 0x4500
24 #define GATE_IP_LEFTBUS 0x4800
25 #define E4X12_GATE_IP_IMAGE 0x4930
26 #define CLKOUT_CMU_LEFTBUS 0x4a00
27 #define SRC_RIGHTBUS 0x8200
28 #define DIV_RIGHTBUS 0x8500
29 #define GATE_IP_RIGHTBUS 0x8800
30 #define E4X12_GATE_IP_PERIR 0x8960
31 #define CLKOUT_CMU_RIGHTBUS 0x8a00
32 #define EPLL_LOCK 0xc010
33 #define VPLL_LOCK 0xc020
34 #define EPLL_CON0 0xc110
35 #define EPLL_CON1 0xc114
36 #define EPLL_CON2 0xc118
37 #define VPLL_CON0 0xc120
38 #define VPLL_CON1 0xc124
39 #define VPLL_CON2 0xc128
40 #define SRC_TOP0 0xc210
41 #define SRC_TOP1 0xc214
42 #define SRC_CAM 0xc220
43 #define SRC_TV 0xc224
44 #define SRC_MFC 0xc228
45 #define SRC_G3D 0xc22c
46 #define E4210_SRC_IMAGE 0xc230
47 #define SRC_LCD0 0xc234
48 #define E4210_SRC_LCD1 0xc238
49 #define E4X12_SRC_ISP 0xc238
50 #define SRC_MAUDIO 0xc23c
51 #define SRC_FSYS 0xc240
52 #define SRC_PERIL0 0xc250
53 #define SRC_PERIL1 0xc254
54 #define E4X12_SRC_CAM1 0xc258
55 #define SRC_MASK_TOP 0xc310
56 #define SRC_MASK_CAM 0xc320
57 #define SRC_MASK_TV 0xc324
58 #define SRC_MASK_LCD0 0xc334
59 #define E4210_SRC_MASK_LCD1 0xc338
60 #define E4X12_SRC_MASK_ISP 0xc338
61 #define SRC_MASK_MAUDIO 0xc33c
62 #define SRC_MASK_FSYS 0xc340
63 #define SRC_MASK_PERIL0 0xc350
64 #define SRC_MASK_PERIL1 0xc354
65 #define DIV_TOP 0xc510
66 #define DIV_CAM 0xc520
67 #define DIV_TV 0xc524
68 #define DIV_MFC 0xc528
69 #define DIV_G3D 0xc52c
70 #define DIV_IMAGE 0xc530
71 #define DIV_LCD0 0xc534
72 #define E4210_DIV_LCD1 0xc538
73 #define E4X12_DIV_ISP 0xc538
74 #define DIV_MAUDIO 0xc53c
75 #define DIV_FSYS0 0xc540
76 #define DIV_FSYS1 0xc544
77 #define DIV_FSYS2 0xc548
78 #define DIV_FSYS3 0xc54c
79 #define DIV_PERIL0 0xc550
80 #define DIV_PERIL1 0xc554
81 #define DIV_PERIL2 0xc558
82 #define DIV_PERIL3 0xc55c
83 #define DIV_PERIL4 0xc560
84 #define DIV_PERIL5 0xc564
85 #define E4X12_DIV_CAM1 0xc568
86 #define E4X12_GATE_BUS_FSYS1 0xc744
87 #define GATE_SCLK_CAM 0xc820
88 #define GATE_IP_CAM 0xc920
89 #define GATE_IP_TV 0xc924
90 #define GATE_IP_MFC 0xc928
91 #define GATE_IP_G3D 0xc92c
92 #define E4210_GATE_IP_IMAGE 0xc930
93 #define GATE_IP_LCD0 0xc934
94 #define E4210_GATE_IP_LCD1 0xc938
95 #define E4X12_GATE_IP_ISP 0xc938
96 #define E4X12_GATE_IP_MAUDIO 0xc93c
97 #define GATE_IP_FSYS 0xc940
98 #define GATE_IP_GPS 0xc94c
99 #define GATE_IP_PERIL 0xc950
100 #define E4210_GATE_IP_PERIR 0xc960
101 #define GATE_BLOCK 0xc970
102 #define CLKOUT_CMU_TOP 0xca00
103 #define E4X12_MPLL_LOCK 0x10008
104 #define E4X12_MPLL_CON0 0x10108
105 #define SRC_DMC 0x10200
106 #define SRC_MASK_DMC 0x10300
107 #define DIV_DMC0 0x10500
108 #define DIV_DMC1 0x10504
109 #define GATE_IP_DMC 0x10900
110 #define CLKOUT_CMU_DMC 0x10a00
111 #define APLL_LOCK 0x14000
112 #define E4210_MPLL_LOCK 0x14008
113 #define APLL_CON0 0x14100
114 #define E4210_MPLL_CON0 0x14108
115 #define SRC_CPU 0x14200
116 #define DIV_CPU0 0x14500
117 #define DIV_CPU1 0x14504
118 #define GATE_SCLK_CPU 0x14800
119 #define GATE_IP_CPU 0x14900
120 #define CLKOUT_CMU_CPU 0x14a00
121 #define PWR_CTRL1 0x15020
122 #define E4X12_PWR_CTRL2 0x15024
123
124 /* Below definitions are used for PWR_CTRL settings */
125 #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
126 #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
127 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
128 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
129 #define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
130 #define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
131 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
132 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
133 #define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
134 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
135 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
136 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
137
138 /* the exynos4 soc type */
139 enum exynos4_soc {
140 EXYNOS4210,
141 EXYNOS4X12,
142 };
143
144 /* list of PLLs to be registered */
145 enum exynos4_plls {
146 apll, mpll, epll, vpll,
147 nr_plls /* number of PLLs */
148 };
149
150 static void __iomem *reg_base;
151 static enum exynos4_soc exynos4_soc;
152
153 /*
154 * list of controller registers to be saved and restored during a
155 * suspend/resume cycle.
156 */
157 static const unsigned long exynos4210_clk_save[] __initconst = {
158 E4210_SRC_IMAGE,
159 E4210_SRC_LCD1,
160 E4210_SRC_MASK_LCD1,
161 E4210_DIV_LCD1,
162 E4210_GATE_IP_IMAGE,
163 E4210_GATE_IP_LCD1,
164 E4210_GATE_IP_PERIR,
165 E4210_MPLL_CON0,
166 PWR_CTRL1,
167 };
168
169 static const unsigned long exynos4x12_clk_save[] __initconst = {
170 E4X12_GATE_IP_IMAGE,
171 E4X12_GATE_IP_PERIR,
172 E4X12_SRC_CAM1,
173 E4X12_DIV_ISP,
174 E4X12_DIV_CAM1,
175 E4X12_MPLL_CON0,
176 PWR_CTRL1,
177 E4X12_PWR_CTRL2,
178 };
179
180 static const unsigned long exynos4_clk_regs[] __initconst = {
181 EPLL_LOCK,
182 VPLL_LOCK,
183 EPLL_CON0,
184 EPLL_CON1,
185 EPLL_CON2,
186 VPLL_CON0,
187 VPLL_CON1,
188 VPLL_CON2,
189 SRC_LEFTBUS,
190 DIV_LEFTBUS,
191 GATE_IP_LEFTBUS,
192 SRC_RIGHTBUS,
193 DIV_RIGHTBUS,
194 GATE_IP_RIGHTBUS,
195 SRC_TOP0,
196 SRC_TOP1,
197 SRC_CAM,
198 SRC_TV,
199 SRC_MFC,
200 SRC_G3D,
201 SRC_LCD0,
202 SRC_MAUDIO,
203 SRC_FSYS,
204 SRC_PERIL0,
205 SRC_PERIL1,
206 SRC_MASK_TOP,
207 SRC_MASK_CAM,
208 SRC_MASK_TV,
209 SRC_MASK_LCD0,
210 SRC_MASK_MAUDIO,
211 SRC_MASK_FSYS,
212 SRC_MASK_PERIL0,
213 SRC_MASK_PERIL1,
214 DIV_TOP,
215 DIV_CAM,
216 DIV_TV,
217 DIV_MFC,
218 DIV_G3D,
219 DIV_IMAGE,
220 DIV_LCD0,
221 DIV_MAUDIO,
222 DIV_FSYS0,
223 DIV_FSYS1,
224 DIV_FSYS2,
225 DIV_FSYS3,
226 DIV_PERIL0,
227 DIV_PERIL1,
228 DIV_PERIL2,
229 DIV_PERIL3,
230 DIV_PERIL4,
231 DIV_PERIL5,
232 GATE_SCLK_CAM,
233 GATE_IP_CAM,
234 GATE_IP_TV,
235 GATE_IP_MFC,
236 GATE_IP_G3D,
237 GATE_IP_LCD0,
238 GATE_IP_FSYS,
239 GATE_IP_GPS,
240 GATE_IP_PERIL,
241 GATE_BLOCK,
242 SRC_MASK_DMC,
243 SRC_DMC,
244 DIV_DMC0,
245 DIV_DMC1,
246 GATE_IP_DMC,
247 APLL_CON0,
248 SRC_CPU,
249 DIV_CPU0,
250 DIV_CPU1,
251 GATE_SCLK_CPU,
252 GATE_IP_CPU,
253 CLKOUT_CMU_LEFTBUS,
254 CLKOUT_CMU_RIGHTBUS,
255 CLKOUT_CMU_TOP,
256 CLKOUT_CMU_DMC,
257 CLKOUT_CMU_CPU,
258 };
259
260 static const struct samsung_clk_reg_dump src_mask_suspend[] = {
261 { .offset = VPLL_CON0, .value = 0x80600302, },
262 { .offset = EPLL_CON0, .value = 0x806F0302, },
263 { .offset = SRC_MASK_TOP, .value = 0x00000001, },
264 { .offset = SRC_MASK_CAM, .value = 0x11111111, },
265 { .offset = SRC_MASK_TV, .value = 0x00000111, },
266 { .offset = SRC_MASK_LCD0, .value = 0x00001111, },
267 { .offset = SRC_MASK_MAUDIO, .value = 0x00000001, },
268 { .offset = SRC_MASK_FSYS, .value = 0x01011111, },
269 { .offset = SRC_MASK_PERIL0, .value = 0x01111111, },
270 { .offset = SRC_MASK_PERIL1, .value = 0x01110111, },
271 { .offset = SRC_MASK_DMC, .value = 0x00010000, },
272 };
273
274 static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
275 { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, },
276 };
277
278 /* list of all parent clock list */
279 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
280 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
281 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
282 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
283 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
284 PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
285 PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
286 PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
287 PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
288 PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
289 PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
290 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
291 "spdif_extclk", };
292 PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
293 PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
294
295 /* Exynos 4210-specific parent groups */
296 PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
297 PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", };
298 PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
299 PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
300 "sclk_usbphy0", "none", "sclk_hdmiphy",
301 "sclk_mpll", "sclk_epll", "sclk_vpll", };
302 PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
303 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
304 "sclk_epll", "sclk_vpll" };
305 PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
306 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
307 "sclk_epll", "sclk_vpll", };
308 PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
309 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
310 "sclk_epll", "sclk_vpll", };
311 PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
312 PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
313 PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
314 "sclk_usbphy1", "sclk_hdmiphy", "none",
315 "sclk_epll", "sclk_vpll" };
316 PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
317 "div_gdl", "div_gpl" };
318 PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
319 "div_gdr", "div_gpr" };
320 PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
321 "sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
322 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
323 "aclk160", "aclk133", "aclk200", "aclk100",
324 "sclk_mfc", "sclk_g3d", "sclk_g2d",
325 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
326 "s_rxbyteclkhs0_4l" };
327 PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
328 "div_dphy", "none", "div_pwi" };
329 PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
330 "none", "arm_clk_div_2", "div_corem0",
331 "div_corem1", "div_corem0", "div_atb",
332 "div_periph", "div_pclk_dbg", "div_hpm" };
333
334 /* Exynos 4x12-specific parent groups */
335 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
336 PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
337 PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", };
338 PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", };
339 PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
340 PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
341 "none", "sclk_hdmiphy", "mout_mpll_user_t",
342 "sclk_epll", "sclk_vpll", };
343 PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
344 "sclk_usbphy0", "xxti", "xusbxti",
345 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
346 PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
347 "sclk_usbphy0", "xxti", "xusbxti",
348 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
349 PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
350 "sclk_usbphy0", "xxti", "xusbxti",
351 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
352 PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
353 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
354 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
355 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
356 PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
357 "none", "sclk_hdmiphy", "sclk_mpll",
358 "sclk_epll", "sclk_vpll" };
359 PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
360 "div_gdl", "div_gpl" };
361 PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
362 "div_gdr", "div_gpr" };
363 PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
364 "sclk_usbphy0", "none", "sclk_hdmiphy",
365 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
366 "aclk160", "aclk133", "aclk200", "aclk100",
367 "sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
368 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
369 "s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
370 "rx_half_byte_clk_csis1", "div_jpeg",
371 "sclk_pwm_isp", "sclk_spi0_isp",
372 "sclk_spi1_isp", "sclk_uart_isp",
373 "sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
374 "sclk_pcm0" };
375 PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
376 "div_dmc", "div_dphy", "fout_mpll_div_2",
377 "div_pwi", "none", "div_c2c", "div_c2c_aclk" };
378 PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
379 "arm_clk_div_2", "div_corem0", "div_corem1",
380 "div_cores", "div_atb", "div_periph",
381 "div_pclk_dbg", "div_hpm" };
382
383 /* fixed rate clocks generated outside the soc */
384 static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
385 FRATE(CLK_XXTI, "xxti", NULL, 0, 0),
386 FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0),
387 };
388
389 /* fixed rate clocks generated inside the soc */
390 static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = {
391 FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),
392 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
393 FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),
394 };
395
396 static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = {
397 FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),
398 };
399
400 static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = {
401 FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
402 FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
403 FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
404 FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
405 };
406
407 static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = {
408 FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
409 };
410
411 static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = {
412 FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
413 FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
414 FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
415 FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
416 };
417
418 /* list of mux clocks supported in all exynos4 soc's */
419 static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
420 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
421 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
422 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
423 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
424 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
425 MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
426 CLK_SET_RATE_PARENT, 0),
427 MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
428 CLK_SET_RATE_PARENT, 0),
429 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
430 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
431 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
432 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
433
434 MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
435 MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
436 };
437
438 /* list of mux clocks supported in exynos4210 soc */
439 static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
440 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
441 };
442
443 static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
444 MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
445 MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
446 CLKOUT_CMU_LEFTBUS, 0, 5),
447
448 MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
449 MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
450 CLKOUT_CMU_RIGHTBUS, 0, 5),
451
452 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
453 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
454 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
455 MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
456 MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
457 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
458 MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
459 MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
460 MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
461 MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
462 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
463 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
464 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
465 MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
466 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
467 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
468 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
469 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
470 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
471 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
472 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
473 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
474 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
475 MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
476 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
477 CLK_SET_RATE_PARENT, 0),
478 MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
479 MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
480 MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
481 MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
482 MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
483 MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
484 MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
485 MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
486 MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
487 MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
488 MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
489 MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
490 MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
491 MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
492 MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
493 MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
494 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
495 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
496 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
497 MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
498
499 MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
500 MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
501
502 MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
503 };
504
505 /* list of mux clocks supported in exynos4x12 soc */
506 static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = {
507 MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
508 MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
509 MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
510 CLKOUT_CMU_LEFTBUS, 0, 5),
511
512 MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
513 MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
514 MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
515 CLKOUT_CMU_RIGHTBUS, 0, 5),
516
517 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
518 SRC_CPU, 24, 1),
519 MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
520
521 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
522 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
523 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
524 SRC_TOP1, 12, 1),
525 MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
526 SRC_TOP1, 16, 1),
527 MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
528 MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
529 mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
530 MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
531 MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
532 MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
533 MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
534 MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
535 MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
536 MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
537 MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
538 MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
539 MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
540 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
541 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
542 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
543 MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
544 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
545 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
546 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
547 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
548 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
549 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
550 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
551 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
552 MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
553 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
554 CLK_SET_RATE_PARENT, 0),
555 MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
556 MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
557 MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
558 MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
559 MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
560 MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
561 MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
562 MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
563 MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
564 MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
565 MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
566 MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
567 MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
568 MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
569 MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
570 MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
571 MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
572 MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
573 MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
574 MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
575 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
576 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
577 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
578 MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
579
580 MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
581 MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
582 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
583 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
584 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
585 MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
586 };
587
588 /* list of divider clocks supported in all exynos4 soc's */
589 static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
590 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
591 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
592 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
593 CLKOUT_CMU_LEFTBUS, 8, 6),
594
595 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
596 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
597 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
598 CLKOUT_CMU_RIGHTBUS, 8, 6),
599
600 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
601 DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
602 DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
603 DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
604 DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
605 DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
606 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
607 DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
608 DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
609 DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
610
611 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
612 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
613 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
614 DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
615 DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
616 DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
617 DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
618 DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
619 DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
620 DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
621 DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
622 DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
623 DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
624 DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
625 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
626 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
627 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
628 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
629 DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
630 DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
631 DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
632 DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
633 DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
634 DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
635 DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
636 DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
637 DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
638 DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
639 DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
640 DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
641 CLK_SET_RATE_PARENT, 0),
642 DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
643 DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
644 DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
645 DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
646 DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
647 DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
648 DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
649 DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
650 DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
651 DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
652 DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
653 DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
654 DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
655 DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
656 DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
657 CLK_SET_RATE_PARENT, 0),
658 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
659 CLK_SET_RATE_PARENT, 0),
660 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
661 CLK_SET_RATE_PARENT, 0),
662 DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
663 CLK_SET_RATE_PARENT, 0),
664 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
665 CLK_SET_RATE_PARENT, 0),
666 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
667
668 DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
669 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
670 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
671 DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
672 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
673 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
674 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
675 DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
676 };
677
678 /* list of divider clocks supported in exynos4210 soc */
679 static const struct samsung_div_clock exynos4210_div_clks[] __initconst = {
680 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
681 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
682 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
683 DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
684 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
685 DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
686 CLK_SET_RATE_PARENT, 0),
687 };
688
689 /* list of divider clocks supported in exynos4x12 soc */
690 static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
691 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
692 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
693 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
694 DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
695 DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
696 DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
697 DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
698 DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
699 DIV_TOP, 24, 3),
700 DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
701 DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
702 DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
703 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
704 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
705 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
706 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
707 DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
708 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
709 };
710
711 /* list of gate clocks supported in all exynos4 soc's */
712 static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
713 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
714 GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
715 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
716 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
717 0),
718 GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
719 GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
720 GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
721 GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
722 GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
723 GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
724 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
725 0),
726 GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
727 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
728 GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
729 GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
730 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
731 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
732 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
733 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
734 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
735 GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
736 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
737 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
738 CLK_SET_RATE_PARENT, 0),
739 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
740 CLK_SET_RATE_PARENT, 0),
741 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
742 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
743 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
744 CLK_SET_RATE_PARENT, 0),
745 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
746 CLK_SET_RATE_PARENT, 0),
747 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
748 GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
749 GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
750 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
751 GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
752 GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
753 GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
754 CLK_SET_RATE_PARENT, 0),
755 GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
756 CLK_SET_RATE_PARENT, 0),
757 GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
758 CLK_SET_RATE_PARENT, 0),
759 GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
760 CLK_SET_RATE_PARENT, 0),
761 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
762 CLK_SET_RATE_PARENT, 0),
763 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
764 CLK_SET_RATE_PARENT, 0),
765 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
766 CLK_SET_RATE_PARENT, 0),
767 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
768 CLK_SET_RATE_PARENT, 0),
769 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
770 CLK_SET_RATE_PARENT, 0),
771 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
772 CLK_SET_RATE_PARENT, 0),
773 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
774 CLK_SET_RATE_PARENT, 0),
775 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
776 CLK_SET_RATE_PARENT, 0),
777 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
778 CLK_SET_RATE_PARENT, 0),
779 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
780 CLK_SET_RATE_PARENT, 0),
781 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
782 CLK_SET_RATE_PARENT, 0),
783 GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
784 CLK_SET_RATE_PARENT, 0),
785 GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
786 CLK_SET_RATE_PARENT, 0),
787 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
788 CLK_SET_RATE_PARENT, 0),
789 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
790 CLK_SET_RATE_PARENT, 0),
791 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
792 CLK_SET_RATE_PARENT, 0),
793 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
794 CLK_SET_RATE_PARENT, 0),
795 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
796 0, 0),
797 GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
798 0, 0),
799 GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
800 0, 0),
801 GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
802 0, 0),
803 GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
804 0, 0),
805 GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
806 0, 0),
807 GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
808 0, 0),
809 GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
810 0, 0),
811 GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
812 0, 0),
813 GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
814 0, 0),
815 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
816 0, 0),
817 GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
818 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
819 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
820 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
821 0, 0),
822 GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
823 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
824 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
825 0, 0),
826 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
827 0, 0),
828 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
829 GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
830 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
831 0, 0),
832 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
833 0, 0),
834 GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
835 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
836 0, 0),
837 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
838 0, 0),
839 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
840 0, 0),
841 GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
842 0, 0),
843 GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
844 0, 0),
845 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
846 0, 0),
847 GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
848 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
849 0, 0),
850 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
851 0, 0),
852 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
853 0, 0),
854 GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
855 0, 0),
856 GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
857 0, 0),
858 GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
859 0, 0),
860 GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
861 0, 0),
862 GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
863 0, 0),
864 GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
865 0, 0),
866 GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
867 0, 0),
868 GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
869 0, 0),
870 GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
871 0, 0),
872 GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
873 0, 0),
874 GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
875 0, 0),
876 GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
877 0, 0),
878 GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
879 0, 0),
880 GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
881 0, 0),
882 GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
883 0, 0),
884 GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
885 0, 0),
886 GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
887 0, 0),
888 GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
889 0, 0),
890 GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
891 0, 0),
892 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
893 0, 0),
894 GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
895 GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
896 GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
897 GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
898 GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
899
900 GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
901 CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
902 GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
903 CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
904 GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
905 CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
906 GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
907 CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
908 GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
909 CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
910 };
911
912 /* list of gate clocks supported in exynos4210 soc */
913 static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = {
914 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
915 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
916 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
917 GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
918 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
919 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
920 0),
921 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
922 0),
923 GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
924 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
925 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
926 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
927 GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
928 GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
929 GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
930 GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
931 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
932 CLK_IGNORE_UNUSED, 0),
933 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
934 0),
935 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
936 E4210_GATE_IP_IMAGE, 4, 0, 0),
937 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
938 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
939 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
940 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
941 GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
942 GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
943 GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
944 0, 0),
945 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
946 0, 0),
947 GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
948 0, 0),
949 GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
950 0, 0),
951 GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
952 0, 0),
953 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
954 CLK_SET_RATE_PARENT, 0),
955 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
956 0),
957 };
958
959 /* list of gate clocks supported in exynos4x12 soc */
960 static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
961 GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0),
962 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
963 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
964 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
965 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
966 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
967 0),
968 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
969 0),
970 GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
971 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
972 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
973 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
974 CLK_IGNORE_UNUSED, 0),
975 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
976 0),
977 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
978 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
979 GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
980 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
981 GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
982 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
983 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
984 E4X12_GATE_IP_IMAGE, 4, 0, 0),
985 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
986 0, 0),
987 GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
988 0, 0),
989 GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
990 GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",
991 E4X12_GATE_IP_ISP, 0, 0, 0),
992 GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",
993 E4X12_GATE_IP_ISP, 1, 0, 0),
994 GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",
995 E4X12_GATE_IP_ISP, 2, 0, 0),
996 GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",
997 E4X12_GATE_IP_ISP, 3, 0, 0),
998 GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
999 GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
1000 0, 0),
1001 GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
1002 0, 0),
1003 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
1004 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
1005 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
1006 0),
1007 };
1008
1009 /*
1010 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
1011 * resides in chipid register space, outside of the clock controller memory
1012 * mapped space. So to determine the parent of fin_pll clock, the chipid
1013 * controller is first remapped and the value of XOM[0] bit is read to
1014 * determine the parent clock.
1015 */
1016 static unsigned long __init exynos4_get_xom(void)
1017 {
1018 unsigned long xom = 0;
1019 void __iomem *chipid_base;
1020 struct device_node *np;
1021
1022 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
1023 if (np) {
1024 chipid_base = of_iomap(np, 0);
1025
1026 if (chipid_base)
1027 xom = readl(chipid_base + 8);
1028
1029 iounmap(chipid_base);
1030 of_node_put(np);
1031 }
1032
1033 return xom;
1034 }
1035
1036 static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
1037 {
1038 struct samsung_fixed_rate_clock fclk;
1039 struct clk *clk;
1040 unsigned long finpll_f = 24000000;
1041 char *parent_name;
1042 unsigned int xom = exynos4_get_xom();
1043
1044 parent_name = xom & 1 ? "xusbxti" : "xxti";
1045 clk = clk_get(NULL, parent_name);
1046 if (IS_ERR(clk)) {
1047 pr_err("%s: failed to lookup parent clock %s, assuming "
1048 "fin_pll clock frequency is 24MHz\n", __func__,
1049 parent_name);
1050 } else {
1051 finpll_f = clk_get_rate(clk);
1052 }
1053
1054 fclk.id = CLK_FIN_PLL;
1055 fclk.name = "fin_pll";
1056 fclk.parent_name = NULL;
1057 fclk.flags = 0;
1058 fclk.fixed_rate = finpll_f;
1059 samsung_clk_register_fixed_rate(ctx, &fclk, 1);
1060
1061 }
1062
1063 static const struct of_device_id ext_clk_match[] __initconst = {
1064 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
1065 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
1066 {},
1067 };
1068
1069 /* PLLs PMS values */
1070 static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {
1071 PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
1072 PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
1073 PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
1074 PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
1075 PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
1076 PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
1077 PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
1078 PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
1079 PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
1080 { /* sentinel */ }
1081 };
1082
1083 static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {
1084 PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
1085 PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0),
1086 PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1, 0, 0),
1087 PLL_4600_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710, 1),
1088 PLL_4600_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762, 1),
1089 PLL_4600_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961, 0),
1090 PLL_4600_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381, 0),
1091 { /* sentinel */ }
1092 };
1093
1094 static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {
1095 PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0),
1096 PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1, 1, 1),
1097 PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1),
1098 PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0),
1099 PLL_4650_RATE(24 * MHZ, 55360351, 53, 3, 3, 2417, 0, 17, 0),
1100 { /* sentinel */ }
1101 };
1102
1103 static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
1104 PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
1105 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1106 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1107 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1108 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1109 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
1110 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
1111 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
1112 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
1113 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
1114 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
1115 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
1116 PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
1117 PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
1118 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
1119 PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
1120 { /* sentinel */ }
1121 };
1122
1123 static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
1124 PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),
1125 PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0),
1126 PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),
1127 PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0),
1128 PLL_36XX_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710),
1129 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762),
1130 PLL_36XX_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961),
1131 PLL_36XX_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381),
1132 { /* sentinel */ }
1133 };
1134
1135 static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {
1136 PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384),
1137 PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1, 0),
1138 PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2, 0),
1139 PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2, 0),
1140 PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
1141 PLL_36XX_RATE(24 * MHZ, 106031250, 53, 3, 2, 1024),
1142 PLL_36XX_RATE(24 * MHZ, 53015625, 53, 3, 3, 1024),
1143 { /* sentinel */ }
1144 };
1145
1146 static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
1147 [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1148 APLL_LOCK, APLL_CON0, NULL),
1149 [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1150 E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),
1151 [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1152 EPLL_LOCK, EPLL_CON0, NULL),
1153 [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
1154 VPLL_LOCK, VPLL_CON0, NULL),
1155 };
1156
1157 static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1158 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1159 APLL_LOCK, APLL_CON0, NULL),
1160 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1161 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
1162 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1163 EPLL_LOCK, EPLL_CON0, NULL),
1164 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
1165 VPLL_LOCK, VPLL_CON0, NULL),
1166 };
1167
1168 static void __init exynos4x12_core_down_clock(void)
1169 {
1170 unsigned int tmp;
1171
1172 /*
1173 * Enable arm clock down (in idle) and set arm divider
1174 * ratios in WFI/WFE state.
1175 */
1176 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
1177 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
1178 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
1179 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
1180 /* On Exynos4412 enable it also on core 2 and 3 */
1181 if (num_possible_cpus() == 4)
1182 tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
1183 PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
1184 writel_relaxed(tmp, reg_base + PWR_CTRL1);
1185
1186 /*
1187 * Disable the clock up feature in case it was enabled by bootloader.
1188 */
1189 writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
1190 }
1191
1192 #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \
1193 (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
1194 ((periph) << 12) | ((corem1) << 8) | ((corem0) << 4))
1195 #define E4210_CPU_DIV1(hpm, copy) \
1196 (((hpm) << 4) | ((copy) << 0))
1197
1198 static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
1199 { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
1200 { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
1201 { 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1202 { 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1203 { 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1204 { 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
1205 { 0 },
1206 };
1207
1208 #define E4412_CPU_DIV1(cores, hpm, copy) \
1209 (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
1210
1211 static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
1212 { 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), },
1213 { 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
1214 { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
1215 { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
1216 { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
1217 { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
1218 { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
1219 { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
1220 { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
1221 { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
1222 { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
1223 { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
1224 { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
1225 { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
1226 { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
1227 { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
1228 { 0 },
1229 };
1230
1231 /* register exynos4 clocks */
1232 static void __init exynos4_clk_init(struct device_node *np,
1233 enum exynos4_soc soc)
1234 {
1235 struct samsung_clk_provider *ctx;
1236 struct clk_hw **hws;
1237
1238 exynos4_soc = soc;
1239
1240 reg_base = of_iomap(np, 0);
1241 if (!reg_base)
1242 panic("%s: failed to map registers\n", __func__);
1243
1244 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1245 hws = ctx->clk_data.hws;
1246
1247 samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
1248 ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
1249 ext_clk_match);
1250
1251 exynos4_clk_register_finpll(ctx);
1252
1253 if (exynos4_soc == EXYNOS4210) {
1254 samsung_clk_register_mux(ctx, exynos4210_mux_early,
1255 ARRAY_SIZE(exynos4210_mux_early));
1256
1257 if (_get_rate("fin_pll") == 24000000) {
1258 exynos4210_plls[apll].rate_table =
1259 exynos4210_apll_rates;
1260 exynos4210_plls[epll].rate_table =
1261 exynos4210_epll_rates;
1262 }
1263
1264 if (_get_rate("mout_vpllsrc") == 24000000)
1265 exynos4210_plls[vpll].rate_table =
1266 exynos4210_vpll_rates;
1267
1268 samsung_clk_register_pll(ctx, exynos4210_plls,
1269 ARRAY_SIZE(exynos4210_plls), reg_base);
1270 } else {
1271 if (_get_rate("fin_pll") == 24000000) {
1272 exynos4x12_plls[apll].rate_table =
1273 exynos4x12_apll_rates;
1274 exynos4x12_plls[epll].rate_table =
1275 exynos4x12_epll_rates;
1276 exynos4x12_plls[vpll].rate_table =
1277 exynos4x12_vpll_rates;
1278 }
1279
1280 samsung_clk_register_pll(ctx, exynos4x12_plls,
1281 ARRAY_SIZE(exynos4x12_plls), reg_base);
1282 }
1283
1284 samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
1285 ARRAY_SIZE(exynos4_fixed_rate_clks));
1286 samsung_clk_register_mux(ctx, exynos4_mux_clks,
1287 ARRAY_SIZE(exynos4_mux_clks));
1288 samsung_clk_register_div(ctx, exynos4_div_clks,
1289 ARRAY_SIZE(exynos4_div_clks));
1290 samsung_clk_register_gate(ctx, exynos4_gate_clks,
1291 ARRAY_SIZE(exynos4_gate_clks));
1292 samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
1293 ARRAY_SIZE(exynos4_fixed_factor_clks));
1294
1295 if (exynos4_soc == EXYNOS4210) {
1296 samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
1297 ARRAY_SIZE(exynos4210_fixed_rate_clks));
1298 samsung_clk_register_mux(ctx, exynos4210_mux_clks,
1299 ARRAY_SIZE(exynos4210_mux_clks));
1300 samsung_clk_register_div(ctx, exynos4210_div_clks,
1301 ARRAY_SIZE(exynos4210_div_clks));
1302 samsung_clk_register_gate(ctx, exynos4210_gate_clks,
1303 ARRAY_SIZE(exynos4210_gate_clks));
1304 samsung_clk_register_fixed_factor(ctx,
1305 exynos4210_fixed_factor_clks,
1306 ARRAY_SIZE(exynos4210_fixed_factor_clks));
1307 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1308 hws[CLK_MOUT_APLL], hws[CLK_SCLK_MPLL], 0x14200,
1309 e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
1310 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1311 } else {
1312 samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1313 ARRAY_SIZE(exynos4x12_mux_clks));
1314 samsung_clk_register_div(ctx, exynos4x12_div_clks,
1315 ARRAY_SIZE(exynos4x12_div_clks));
1316 samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
1317 ARRAY_SIZE(exynos4x12_gate_clks));
1318 samsung_clk_register_fixed_factor(ctx,
1319 exynos4x12_fixed_factor_clks,
1320 ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1321
1322 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1323 hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C], 0x14200,
1324 e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
1325 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1326 }
1327
1328 if (soc == EXYNOS4X12)
1329 exynos4x12_core_down_clock();
1330
1331 samsung_clk_extended_sleep_init(reg_base,
1332 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1333 src_mask_suspend, ARRAY_SIZE(src_mask_suspend));
1334 if (exynos4_soc == EXYNOS4210)
1335 samsung_clk_extended_sleep_init(reg_base,
1336 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save),
1337 src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210));
1338 else
1339 samsung_clk_sleep_init(reg_base, exynos4x12_clk_save,
1340 ARRAY_SIZE(exynos4x12_clk_save));
1341
1342 samsung_clk_of_add_provider(np, ctx);
1343
1344 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1345 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
1346 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
1347 _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
1348 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
1349 _get_rate("div_core2"));
1350 }
1351
1352
1353 static void __init exynos4210_clk_init(struct device_node *np)
1354 {
1355 exynos4_clk_init(np, EXYNOS4210);
1356 }
1357 CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
1358
1359 static void __init exynos4412_clk_init(struct device_node *np)
1360 {
1361 exynos4_clk_init(np, EXYNOS4X12);
1362 }
1363 CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);
Linux with added FPC-III support