drivers/clk/socfpga/stratix10-clk.h

   1 /* SPDX-License-Identifier:    GPL-2.0 */
   2 /*
   3  * Copyright (C) 2017, Intel Corporation
   4  */
   5
   6 #ifndef __STRATIX10_CLK_H
   7 #define __STRATIX10_CLK_H
   8
   9 struct stratix10_clock_data {
  10         struct clk_onecell_data clk_data;
  11         void __iomem            *base;
  12 };
  13
  14 struct stratix10_pll_clock {
  15         unsigned int            id;
  16         const char              *name;
  17         const struct clk_parent_data    *parent_data;
  18         u8                      num_parents;
  19         unsigned long           flags;
  20         unsigned long           offset;
  21 };
  22
  23 struct stratix10_perip_c_clock {
  24         unsigned int            id;
  25         const char              *name;
  26         const char              *parent_name;
  27         const struct clk_parent_data    *parent_data;
  28         u8                      num_parents;
  29         unsigned long           flags;
  30         unsigned long           offset;
  31 };
  32
  33 struct stratix10_perip_cnt_clock {
  34         unsigned int            id;
  35         const char              *name;
  36         const char              *parent_name;
  37         const struct clk_parent_data    *parent_data;
  38         u8                      num_parents;
  39         unsigned long           flags;
  40         unsigned long           offset;
  41         u8                      fixed_divider;
  42         unsigned long           bypass_reg;
  43         unsigned long           bypass_shift;
  44 };
  45
  46 struct stratix10_gate_clock {
  47         unsigned int            id;
  48         const char              *name;
  49         const char              *parent_name;
  50         const struct clk_parent_data    *parent_data;
  51         u8                      num_parents;
  52         unsigned long           flags;
  53         unsigned long           gate_reg;
  54         u8                      gate_idx;
  55         unsigned long           div_reg;
  56         u8                      div_offset;
  57         u8                      div_width;
  58         unsigned long           bypass_reg;
  59         u8                      bypass_shift;
  60         u8                      fixed_div;
  61 };
  62
  63 struct clk *s10_register_pll(const struct stratix10_pll_clock *,
  64                              void __iomem *);
  65 struct clk *agilex_register_pll(const struct stratix10_pll_clock *,
  66                                 void __iomem *);
  67 struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
  68                                 void __iomem *);
  69 struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
  70                                     void __iomem *);
  71 struct clk *s10_register_gate(const struct stratix10_gate_clock *,
  72                               void __iomem *);
  73 #endif  /* __STRATIX10_CLK_H */