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WIP FPC-III support
[linux/fpc-iii.git] / drivers / clk / tegra / clk-pll.c
blobc5cc0a2dac6ff880de18824553701c9d06c5ee5e
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/slab.h>
7 #include <linux/io.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12
13 #include "clk.h"
14
15 #define PLL_BASE_BYPASS BIT(31)
16 #define PLL_BASE_ENABLE BIT(30)
17 #define PLL_BASE_REF_ENABLE BIT(29)
18 #define PLL_BASE_OVERRIDE BIT(28)
19
20 #define PLL_BASE_DIVP_SHIFT 20
21 #define PLL_BASE_DIVP_WIDTH 3
22 #define PLL_BASE_DIVN_SHIFT 8
23 #define PLL_BASE_DIVN_WIDTH 10
24 #define PLL_BASE_DIVM_SHIFT 0
25 #define PLL_BASE_DIVM_WIDTH 5
26 #define PLLU_POST_DIVP_MASK 0x1
27
28 #define PLL_MISC_DCCON_SHIFT 20
29 #define PLL_MISC_CPCON_SHIFT 8
30 #define PLL_MISC_CPCON_WIDTH 4
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
32 #define PLL_MISC_LFCON_SHIFT 4
33 #define PLL_MISC_LFCON_WIDTH 4
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
35 #define PLL_MISC_VCOCON_SHIFT 0
36 #define PLL_MISC_VCOCON_WIDTH 4
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
38
39 #define OUT_OF_TABLE_CPCON 8
40
41 #define PMC_PLLP_WB0_OVERRIDE 0xf8
42 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
43 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
44
45 #define PLL_POST_LOCK_DELAY 50
46
47 #define PLLDU_LFCON_SET_DIVN 600
48
49 #define PLLE_BASE_DIVCML_SHIFT 24
50 #define PLLE_BASE_DIVCML_MASK 0xf
51 #define PLLE_BASE_DIVP_SHIFT 16
52 #define PLLE_BASE_DIVP_WIDTH 6
53 #define PLLE_BASE_DIVN_SHIFT 8
54 #define PLLE_BASE_DIVN_WIDTH 8
55 #define PLLE_BASE_DIVM_SHIFT 0
56 #define PLLE_BASE_DIVM_WIDTH 8
57 #define PLLE_BASE_ENABLE BIT(31)
58
59 #define PLLE_MISC_SETUP_BASE_SHIFT 16
60 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
61 #define PLLE_MISC_LOCK_ENABLE BIT(9)
62 #define PLLE_MISC_READY BIT(15)
63 #define PLLE_MISC_SETUP_EX_SHIFT 2
64 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
65 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
66 PLLE_MISC_SETUP_EX_MASK)
67 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
68
69 #define PLLE_SS_CTRL 0x68
70 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
71 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
72 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
73 #define PLLE_SS_CNTL_CENTER BIT(14)
74 #define PLLE_SS_CNTL_INVERT BIT(15)
75 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
76 PLLE_SS_CNTL_SSC_BYP)
77 #define PLLE_SS_MAX_MASK 0x1ff
78 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
79 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
80 #define PLLE_SS_INC_MASK (0xff << 16)
81 #define PLLE_SS_INC_VAL (0x1 << 16)
82 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
83 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
84 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
85 #define PLLE_SS_COEFFICIENTS_MASK \
86 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
87 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
88 (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
89 PLLE_SS_INCINTRV_VAL_TEGRA114)
90 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
91 (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
92 PLLE_SS_INCINTRV_VAL_TEGRA210)
93
94 #define PLLE_AUX_PLLP_SEL BIT(2)
95 #define PLLE_AUX_USE_LOCKDET BIT(3)
96 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
97 #define PLLE_AUX_SS_SWCTL BIT(6)
98 #define PLLE_AUX_SEQ_ENABLE BIT(24)
99 #define PLLE_AUX_SEQ_START_STATE BIT(25)
100 #define PLLE_AUX_PLLRE_SEL BIT(28)
101 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
102
103 #define XUSBIO_PLL_CFG0 0x51c
104 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
105 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
106 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
107 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
108 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
109
110 #define SATA_PLL_CFG0 0x490
111 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
112 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
113 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
114 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
115
116 #define PLLE_MISC_PLLE_PTS BIT(8)
117 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
118 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
119 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
120 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
121 #define PLLE_MISC_VREG_CTRL_SHIFT 2
122 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
123
124 #define PLLCX_MISC_STROBE BIT(31)
125 #define PLLCX_MISC_RESET BIT(30)
126 #define PLLCX_MISC_SDM_DIV_SHIFT 28
127 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
128 #define PLLCX_MISC_FILT_DIV_SHIFT 26
129 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
130 #define PLLCX_MISC_ALPHA_SHIFT 18
131 #define PLLCX_MISC_DIV_LOW_RANGE \
132 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
133 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
134 #define PLLCX_MISC_DIV_HIGH_RANGE \
135 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
136 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
137 #define PLLCX_MISC_COEF_LOW_RANGE \
138 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
139 #define PLLCX_MISC_KA_SHIFT 2
140 #define PLLCX_MISC_KB_SHIFT 9
141 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
142 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
143 PLLCX_MISC_DIV_LOW_RANGE | \
144 PLLCX_MISC_RESET)
145 #define PLLCX_MISC1_DEFAULT 0x000d2308
146 #define PLLCX_MISC2_DEFAULT 0x30211200
147 #define PLLCX_MISC3_DEFAULT 0x200
148
149 #define PMC_SATA_PWRGT 0x1ac
150 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
151 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
152
153 #define PLLSS_MISC_KCP 0
154 #define PLLSS_MISC_KVCO 0
155 #define PLLSS_MISC_SETUP 0
156 #define PLLSS_EN_SDM 0
157 #define PLLSS_EN_SSC 0
158 #define PLLSS_EN_DITHER2 0
159 #define PLLSS_EN_DITHER 1
160 #define PLLSS_SDM_RESET 0
161 #define PLLSS_CLAMP 0
162 #define PLLSS_SDM_SSC_MAX 0
163 #define PLLSS_SDM_SSC_MIN 0
164 #define PLLSS_SDM_SSC_STEP 0
165 #define PLLSS_SDM_DIN 0
166 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
167 (PLLSS_MISC_KVCO << 24) | \
168 PLLSS_MISC_SETUP)
169 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
170 (PLLSS_EN_SSC << 30) | \
171 (PLLSS_EN_DITHER2 << 29) | \
172 (PLLSS_EN_DITHER << 28) | \
173 (PLLSS_SDM_RESET) << 27 | \
174 (PLLSS_CLAMP << 22))
175 #define PLLSS_CTRL1_DEFAULT \
176 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
177 #define PLLSS_CTRL2_DEFAULT \
178 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
179 #define PLLSS_LOCK_OVERRIDE BIT(24)
180 #define PLLSS_REF_SRC_SEL_SHIFT 25
181 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
182
183 #define UTMIP_PLL_CFG1 0x484
184 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
185 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
186 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
187 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
188 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
189 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
190 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
191
192 #define UTMIP_PLL_CFG2 0x488
193 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
194 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
195 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
196 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
197 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
198 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
199 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
200 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
201 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
202 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
203 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
204
205 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
206 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
208 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
209 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
210 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
211 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
212 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
213 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
214
215 #define PLLU_HW_PWRDN_CFG0 0x530
216 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
217 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
218 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
219 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
220 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
221 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
222
223 #define XUSB_PLL_CFG0 0x534
224 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
225 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
226
227 #define PLLU_BASE_CLKENABLE_USB BIT(21)
228 #define PLLU_BASE_OVERRIDE BIT(24)
229
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
236
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
240 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
243
244 #define mask(w) ((1 << (w)) - 1)
245 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
246 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
247 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
248 mask(p->params->div_nmp->divp_width))
249 #define sdm_din_mask(p) p->params->sdm_din_mask
250 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
251
252 #define divm_shift(p) (p)->params->div_nmp->divm_shift
253 #define divn_shift(p) (p)->params->div_nmp->divn_shift
254 #define divp_shift(p) (p)->params->div_nmp->divp_shift
255
256 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
257 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
258 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
259
260 #define divm_max(p) (divm_mask(p))
261 #define divn_max(p) (divn_mask(p))
262 #define divp_max(p) (1 << (divp_mask(p)))
263
264 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
265 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
266
267 static struct div_nmp default_nmp = {
268 .divn_shift = PLL_BASE_DIVN_SHIFT,
269 .divn_width = PLL_BASE_DIVN_WIDTH,
270 .divm_shift = PLL_BASE_DIVM_SHIFT,
271 .divm_width = PLL_BASE_DIVM_WIDTH,
272 .divp_shift = PLL_BASE_DIVP_SHIFT,
273 .divp_width = PLL_BASE_DIVP_WIDTH,
274 };
275
276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
277 {
278 u32 val;
279
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
281 return;
282
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
284 return;
285
286 val = pll_readl_misc(pll);
287 val |= BIT(pll->params->lock_enable_bit_idx);
288 pll_writel_misc(val, pll);
289 }
290
291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
292 {
293 int i;
294 u32 val, lock_mask;
295 void __iomem *lock_addr;
296
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
298 udelay(pll->params->lock_delay);
299 return 0;
300 }
301
302 lock_addr = pll->clk_base;
303 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
304 lock_addr += pll->params->misc_reg;
305 else
306 lock_addr += pll->params->base_reg;
307
308 lock_mask = pll->params->lock_mask;
309
310 for (i = 0; i < pll->params->lock_delay; i++) {
311 val = readl_relaxed(lock_addr);
312 if ((val & lock_mask) == lock_mask) {
313 udelay(PLL_POST_LOCK_DELAY);
314 return 0;
315 }
316 udelay(2); /* timeout = 2 * lock time */
317 }
318
319 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
320 clk_hw_get_name(&pll->hw));
321
322 return -1;
323 }
324
325 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
326 {
327 return clk_pll_wait_for_lock(pll);
328 }
329
330 static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll)
331 {
332 u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
333
334 return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) &&
335 !(val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE);
336 }
337
338 static int clk_pll_is_enabled(struct clk_hw *hw)
339 {
340 struct tegra_clk_pll *pll = to_clk_pll(hw);
341 u32 val;
342
343 /*
344 * Power Management Controller (PMC) can override the PLLM clock
345 * settings, including the enable-state. The PLLM is enabled when
346 * PLLM's CaR state is ON and when PLLM isn't gated by PMC.
347 */
348 if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll))
349 return 0;
350
351 val = pll_readl_base(pll);
352
353 return val & PLL_BASE_ENABLE ? 1 : 0;
354 }
355
356 static void _clk_pll_enable(struct clk_hw *hw)
357 {
358 struct tegra_clk_pll *pll = to_clk_pll(hw);
359 u32 val;
360
361 if (pll->params->iddq_reg) {
362 val = pll_readl(pll->params->iddq_reg, pll);
363 val &= ~BIT(pll->params->iddq_bit_idx);
364 pll_writel(val, pll->params->iddq_reg, pll);
365 udelay(5);
366 }
367
368 if (pll->params->reset_reg) {
369 val = pll_readl(pll->params->reset_reg, pll);
370 val &= ~BIT(pll->params->reset_bit_idx);
371 pll_writel(val, pll->params->reset_reg, pll);
372 }
373
374 clk_pll_enable_lock(pll);
375
376 val = pll_readl_base(pll);
377 if (pll->params->flags & TEGRA_PLL_BYPASS)
378 val &= ~PLL_BASE_BYPASS;
379 val |= PLL_BASE_ENABLE;
380 pll_writel_base(val, pll);
381
382 if (pll->params->flags & TEGRA_PLLM) {
383 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
384 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
385 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
386 }
387 }
388
389 static void _clk_pll_disable(struct clk_hw *hw)
390 {
391 struct tegra_clk_pll *pll = to_clk_pll(hw);
392 u32 val;
393
394 val = pll_readl_base(pll);
395 if (pll->params->flags & TEGRA_PLL_BYPASS)
396 val &= ~PLL_BASE_BYPASS;
397 val &= ~PLL_BASE_ENABLE;
398 pll_writel_base(val, pll);
399
400 if (pll->params->flags & TEGRA_PLLM) {
401 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
402 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
403 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
404 }
405
406 if (pll->params->reset_reg) {
407 val = pll_readl(pll->params->reset_reg, pll);
408 val |= BIT(pll->params->reset_bit_idx);
409 pll_writel(val, pll->params->reset_reg, pll);
410 }
411
412 if (pll->params->iddq_reg) {
413 val = pll_readl(pll->params->iddq_reg, pll);
414 val |= BIT(pll->params->iddq_bit_idx);
415 pll_writel(val, pll->params->iddq_reg, pll);
416 udelay(2);
417 }
418 }
419
420 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
421 {
422 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
424
425 val |= pll->params->ssc_ctrl_en_mask;
426 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
427 }
428 }
429
430 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
431 {
432 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
433 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
434
435 val &= ~pll->params->ssc_ctrl_en_mask;
436 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
437 }
438 }
439
440 static int clk_pll_enable(struct clk_hw *hw)
441 {
442 struct tegra_clk_pll *pll = to_clk_pll(hw);
443 unsigned long flags = 0;
444 int ret;
445
446 if (clk_pll_is_enabled(hw))
447 return 0;
448
449 if (pll->lock)
450 spin_lock_irqsave(pll->lock, flags);
451
452 _clk_pll_enable(hw);
453
454 ret = clk_pll_wait_for_lock(pll);
455
456 pll_clk_start_ss(pll);
457
458 if (pll->lock)
459 spin_unlock_irqrestore(pll->lock, flags);
460
461 return ret;
462 }
463
464 static void clk_pll_disable(struct clk_hw *hw)
465 {
466 struct tegra_clk_pll *pll = to_clk_pll(hw);
467 unsigned long flags = 0;
468
469 if (pll->lock)
470 spin_lock_irqsave(pll->lock, flags);
471
472 pll_clk_stop_ss(pll);
473
474 _clk_pll_disable(hw);
475
476 if (pll->lock)
477 spin_unlock_irqrestore(pll->lock, flags);
478 }
479
480 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
481 {
482 struct tegra_clk_pll *pll = to_clk_pll(hw);
483 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
484
485 if (p_tohw) {
486 while (p_tohw->pdiv) {
487 if (p_div <= p_tohw->pdiv)
488 return p_tohw->hw_val;
489 p_tohw++;
490 }
491 return -EINVAL;
492 }
493 return -EINVAL;
494 }
495
496 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
497 {
498 return _p_div_to_hw(&pll->hw, p_div);
499 }
500
501 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
502 {
503 struct tegra_clk_pll *pll = to_clk_pll(hw);
504 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
505
506 if (p_tohw) {
507 while (p_tohw->pdiv) {
508 if (p_div_hw == p_tohw->hw_val)
509 return p_tohw->pdiv;
510 p_tohw++;
511 }
512 return -EINVAL;
513 }
514
515 return 1 << p_div_hw;
516 }
517
518 static int _get_table_rate(struct clk_hw *hw,
519 struct tegra_clk_pll_freq_table *cfg,
520 unsigned long rate, unsigned long parent_rate)
521 {
522 struct tegra_clk_pll *pll = to_clk_pll(hw);
523 struct tegra_clk_pll_freq_table *sel;
524 int p;
525
526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
527 if (sel->input_rate == parent_rate &&
528 sel->output_rate == rate)
529 break;
530
531 if (sel->input_rate == 0)
532 return -EINVAL;
533
534 if (pll->params->pdiv_tohw) {
535 p = _p_div_to_hw(hw, sel->p);
536 if (p < 0)
537 return p;
538 } else {
539 p = ilog2(sel->p);
540 }
541
542 cfg->input_rate = sel->input_rate;
543 cfg->output_rate = sel->output_rate;
544 cfg->m = sel->m;
545 cfg->n = sel->n;
546 cfg->p = p;
547 cfg->cpcon = sel->cpcon;
548 cfg->sdm_data = sel->sdm_data;
549
550 return 0;
551 }
552
553 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
554 unsigned long rate, unsigned long parent_rate)
555 {
556 struct tegra_clk_pll *pll = to_clk_pll(hw);
557 unsigned long cfreq;
558 u32 p_div = 0;
559 int ret;
560
561 switch (parent_rate) {
562 case 12000000:
563 case 26000000:
564 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
565 break;
566 case 13000000:
567 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
568 break;
569 case 16800000:
570 case 19200000:
571 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
572 break;
573 case 9600000:
574 case 28800000:
575 /*
576 * PLL_P_OUT1 rate is not listed in PLLA table
577 */
578 cfreq = parent_rate / (parent_rate / 1000000);
579 break;
580 default:
581 pr_err("%s Unexpected reference rate %lu\n",
582 __func__, parent_rate);
583 BUG();
584 }
585
586 /* Raise VCO to guarantee 0.5% accuracy */
587 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
588 cfg->output_rate <<= 1)
589 p_div++;
590
591 cfg->m = parent_rate / cfreq;
592 cfg->n = cfg->output_rate / cfreq;
593 cfg->cpcon = OUT_OF_TABLE_CPCON;
594
595 if (cfg->m == 0 || cfg->m > divm_max(pll) ||
596 cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
597 cfg->output_rate > pll->params->vco_max) {
598 return -EINVAL;
599 }
600
601 cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
602 cfg->output_rate >>= p_div;
603
604 if (pll->params->pdiv_tohw) {
605 ret = _p_div_to_hw(hw, 1 << p_div);
606 if (ret < 0)
607 return ret;
608 else
609 cfg->p = ret;
610 } else
611 cfg->p = p_div;
612
613 return 0;
614 }
615
616 /*
617 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
618 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
619 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
620 * to indicate that SDM is disabled.
621 *
622 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
623 */
624 static void clk_pll_set_sdm_data(struct clk_hw *hw,
625 struct tegra_clk_pll_freq_table *cfg)
626 {
627 struct tegra_clk_pll *pll = to_clk_pll(hw);
628 u32 val;
629 bool enabled;
630
631 if (!pll->params->sdm_din_reg)
632 return;
633
634 if (cfg->sdm_data) {
635 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
636 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
637 pll_writel_sdm_din(val, pll);
638 }
639
640 val = pll_readl_sdm_ctrl(pll);
641 enabled = (val & sdm_en_mask(pll));
642
643 if (cfg->sdm_data == 0 && enabled)
644 val &= ~pll->params->sdm_ctrl_en_mask;
645
646 if (cfg->sdm_data != 0 && !enabled)
647 val |= pll->params->sdm_ctrl_en_mask;
648
649 pll_writel_sdm_ctrl(val, pll);
650 }
651
652 static void _update_pll_mnp(struct tegra_clk_pll *pll,
653 struct tegra_clk_pll_freq_table *cfg)
654 {
655 u32 val;
656 struct tegra_clk_pll_params *params = pll->params;
657 struct div_nmp *div_nmp = params->div_nmp;
658
659 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
660 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
661 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
662 val = pll_override_readl(params->pmc_divp_reg, pll);
663 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
664 val |= cfg->p << div_nmp->override_divp_shift;
665 pll_override_writel(val, params->pmc_divp_reg, pll);
666
667 val = pll_override_readl(params->pmc_divnm_reg, pll);
668 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
669 (divn_mask(pll) << div_nmp->override_divn_shift));
670 val |= (cfg->m << div_nmp->override_divm_shift) |
671 (cfg->n << div_nmp->override_divn_shift);
672 pll_override_writel(val, params->pmc_divnm_reg, pll);
673 } else {
674 val = pll_readl_base(pll);
675
676 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
677 divp_mask_shifted(pll));
678
679 val |= (cfg->m << divm_shift(pll)) |
680 (cfg->n << divn_shift(pll)) |
681 (cfg->p << divp_shift(pll));
682
683 pll_writel_base(val, pll);
684
685 clk_pll_set_sdm_data(&pll->hw, cfg);
686 }
687 }
688
689 static void _get_pll_mnp(struct tegra_clk_pll *pll,
690 struct tegra_clk_pll_freq_table *cfg)
691 {
692 u32 val;
693 struct tegra_clk_pll_params *params = pll->params;
694 struct div_nmp *div_nmp = params->div_nmp;
695
696 *cfg = (struct tegra_clk_pll_freq_table) { };
697
698 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
699 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
700 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
701 val = pll_override_readl(params->pmc_divp_reg, pll);
702 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
703
704 val = pll_override_readl(params->pmc_divnm_reg, pll);
705 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
706 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
707 } else {
708 val = pll_readl_base(pll);
709
710 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
711 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
712 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
713
714 if (pll->params->sdm_din_reg) {
715 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
716 val = pll_readl_sdm_din(pll);
717 val &= sdm_din_mask(pll);
718 cfg->sdm_data = sdin_din_to_data(val);
719 }
720 }
721 }
722 }
723
724 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
725 struct tegra_clk_pll_freq_table *cfg,
726 unsigned long rate)
727 {
728 u32 val;
729
730 val = pll_readl_misc(pll);
731
732 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
733 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
734
735 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
736 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
737 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
738 val |= 1 << PLL_MISC_LFCON_SHIFT;
739 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
740 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
741 if (rate >= (pll->params->vco_max >> 1))
742 val |= 1 << PLL_MISC_DCCON_SHIFT;
743 }
744
745 pll_writel_misc(val, pll);
746 }
747
748 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
749 unsigned long rate)
750 {
751 struct tegra_clk_pll *pll = to_clk_pll(hw);
752 struct tegra_clk_pll_freq_table old_cfg;
753 int state, ret = 0;
754
755 state = clk_pll_is_enabled(hw);
756
757 if (state && pll->params->pre_rate_change) {
758 ret = pll->params->pre_rate_change();
759 if (WARN_ON(ret))
760 return ret;
761 }
762
763 _get_pll_mnp(pll, &old_cfg);
764
765 if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
766 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
767 ret = pll->params->dyn_ramp(pll, cfg);
768 if (!ret)
769 goto done;
770 }
771
772 if (state) {
773 pll_clk_stop_ss(pll);
774 _clk_pll_disable(hw);
775 }
776
777 if (!pll->params->defaults_set && pll->params->set_defaults)
778 pll->params->set_defaults(pll);
779
780 _update_pll_mnp(pll, cfg);
781
782 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
783 _update_pll_cpcon(pll, cfg, rate);
784
785 if (state) {
786 _clk_pll_enable(hw);
787 ret = clk_pll_wait_for_lock(pll);
788 pll_clk_start_ss(pll);
789 }
790
791 done:
792 if (state && pll->params->post_rate_change)
793 pll->params->post_rate_change();
794
795 return ret;
796 }
797
798 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
799 unsigned long parent_rate)
800 {
801 struct tegra_clk_pll *pll = to_clk_pll(hw);
802 struct tegra_clk_pll_freq_table cfg, old_cfg;
803 unsigned long flags = 0;
804 int ret = 0;
805
806 if (pll->params->flags & TEGRA_PLL_FIXED) {
807 if (rate != pll->params->fixed_rate) {
808 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
809 __func__, clk_hw_get_name(hw),
810 pll->params->fixed_rate, rate);
811 return -EINVAL;
812 }
813 return 0;
814 }
815
816 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
817 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
818 pr_err("%s: Failed to set %s rate %lu\n", __func__,
819 clk_hw_get_name(hw), rate);
820 WARN_ON(1);
821 return -EINVAL;
822 }
823 if (pll->lock)
824 spin_lock_irqsave(pll->lock, flags);
825
826 _get_pll_mnp(pll, &old_cfg);
827 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
828 cfg.p = old_cfg.p;
829
830 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
831 old_cfg.sdm_data != cfg.sdm_data)
832 ret = _program_pll(hw, &cfg, rate);
833
834 if (pll->lock)
835 spin_unlock_irqrestore(pll->lock, flags);
836
837 return ret;
838 }
839
840 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
841 unsigned long *prate)
842 {
843 struct tegra_clk_pll *pll = to_clk_pll(hw);
844 struct tegra_clk_pll_freq_table cfg;
845
846 if (pll->params->flags & TEGRA_PLL_FIXED) {
847 /* PLLM/MB are used for memory; we do not change rate */
848 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
849 return clk_hw_get_rate(hw);
850 return pll->params->fixed_rate;
851 }
852
853 if (_get_table_rate(hw, &cfg, rate, *prate) &&
854 pll->params->calc_rate(hw, &cfg, rate, *prate))
855 return -EINVAL;
856
857 return cfg.output_rate;
858 }
859
860 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
861 unsigned long parent_rate)
862 {
863 struct tegra_clk_pll *pll = to_clk_pll(hw);
864 struct tegra_clk_pll_freq_table cfg;
865 u32 val;
866 u64 rate = parent_rate;
867 int pdiv;
868
869 val = pll_readl_base(pll);
870
871 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
872 return parent_rate;
873
874 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
875 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
876 !(val & PLL_BASE_OVERRIDE)) {
877 struct tegra_clk_pll_freq_table sel;
878 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
879 parent_rate)) {
880 pr_err("Clock %s has unknown fixed frequency\n",
881 clk_hw_get_name(hw));
882 BUG();
883 }
884 return pll->params->fixed_rate;
885 }
886
887 _get_pll_mnp(pll, &cfg);
888
889 if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
890 pdiv = 1;
891 } else {
892 pdiv = _hw_to_p_div(hw, cfg.p);
893 if (pdiv < 0) {
894 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
895 clk_hw_get_name(hw), cfg.p);
896 pdiv = 1;
897 }
898 }
899
900 if (pll->params->set_gain)
901 pll->params->set_gain(&cfg);
902
903 cfg.m *= pdiv;
904
905 rate *= cfg.n;
906 do_div(rate, cfg.m);
907
908 return rate;
909 }
910
911 static int clk_plle_training(struct tegra_clk_pll *pll)
912 {
913 u32 val;
914 unsigned long timeout;
915
916 if (!pll->pmc)
917 return -ENOSYS;
918
919 /*
920 * PLLE is already disabled, and setup cleared;
921 * create falling edge on PLLE IDDQ input.
922 */
923 val = readl(pll->pmc + PMC_SATA_PWRGT);
924 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
925 writel(val, pll->pmc + PMC_SATA_PWRGT);
926
927 val = readl(pll->pmc + PMC_SATA_PWRGT);
928 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
929 writel(val, pll->pmc + PMC_SATA_PWRGT);
930
931 val = readl(pll->pmc + PMC_SATA_PWRGT);
932 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
933 writel(val, pll->pmc + PMC_SATA_PWRGT);
934
935 val = pll_readl_misc(pll);
936
937 timeout = jiffies + msecs_to_jiffies(100);
938 while (1) {
939 val = pll_readl_misc(pll);
940 if (val & PLLE_MISC_READY)
941 break;
942 if (time_after(jiffies, timeout)) {
943 pr_err("%s: timeout waiting for PLLE\n", __func__);
944 return -EBUSY;
945 }
946 udelay(300);
947 }
948
949 return 0;
950 }
951
952 static int clk_plle_enable(struct clk_hw *hw)
953 {
954 struct tegra_clk_pll *pll = to_clk_pll(hw);
955 struct tegra_clk_pll_freq_table sel;
956 unsigned long input_rate;
957 u32 val;
958 int err;
959
960 if (clk_pll_is_enabled(hw))
961 return 0;
962
963 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
964
965 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
966 return -EINVAL;
967
968 clk_pll_disable(hw);
969
970 val = pll_readl_misc(pll);
971 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
972 pll_writel_misc(val, pll);
973
974 val = pll_readl_misc(pll);
975 if (!(val & PLLE_MISC_READY)) {
976 err = clk_plle_training(pll);
977 if (err)
978 return err;
979 }
980
981 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
982 /* configure dividers */
983 val = pll_readl_base(pll);
984 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
985 divm_mask_shifted(pll));
986 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
987 val |= sel.m << divm_shift(pll);
988 val |= sel.n << divn_shift(pll);
989 val |= sel.p << divp_shift(pll);
990 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
991 pll_writel_base(val, pll);
992 }
993
994 val = pll_readl_misc(pll);
995 val |= PLLE_MISC_SETUP_VALUE;
996 val |= PLLE_MISC_LOCK_ENABLE;
997 pll_writel_misc(val, pll);
998
999 val = readl(pll->clk_base + PLLE_SS_CTRL);
1000 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1001 val |= PLLE_SS_DISABLE;
1002 writel(val, pll->clk_base + PLLE_SS_CTRL);
1003
1004 val = pll_readl_base(pll);
1005 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1006 pll_writel_base(val, pll);
1007
1008 clk_pll_wait_for_lock(pll);
1009
1010 return 0;
1011 }
1012
1013 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
1014 unsigned long parent_rate)
1015 {
1016 struct tegra_clk_pll *pll = to_clk_pll(hw);
1017 u32 val = pll_readl_base(pll);
1018 u32 divn = 0, divm = 0, divp = 0;
1019 u64 rate = parent_rate;
1020
1021 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1022 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1023 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1024 divm *= divp;
1025
1026 rate *= divn;
1027 do_div(rate, divm);
1028 return rate;
1029 }
1030
1031 static void tegra_clk_pll_restore_context(struct clk_hw *hw)
1032 {
1033 struct tegra_clk_pll *pll = to_clk_pll(hw);
1034 struct clk_hw *parent = clk_hw_get_parent(hw);
1035 unsigned long parent_rate = clk_hw_get_rate(parent);
1036 unsigned long rate = clk_hw_get_rate(hw);
1037
1038 if (clk_pll_is_enabled(hw))
1039 return;
1040
1041 if (pll->params->set_defaults)
1042 pll->params->set_defaults(pll);
1043
1044 clk_pll_set_rate(hw, rate, parent_rate);
1045
1046 if (!__clk_get_enable_count(hw->clk))
1047 clk_pll_disable(hw);
1048 else
1049 clk_pll_enable(hw);
1050 }
1051
1052 const struct clk_ops tegra_clk_pll_ops = {
1053 .is_enabled = clk_pll_is_enabled,
1054 .enable = clk_pll_enable,
1055 .disable = clk_pll_disable,
1056 .recalc_rate = clk_pll_recalc_rate,
1057 .round_rate = clk_pll_round_rate,
1058 .set_rate = clk_pll_set_rate,
1059 .restore_context = tegra_clk_pll_restore_context,
1060 };
1061
1062 const struct clk_ops tegra_clk_plle_ops = {
1063 .recalc_rate = clk_plle_recalc_rate,
1064 .is_enabled = clk_pll_is_enabled,
1065 .disable = clk_pll_disable,
1066 .enable = clk_plle_enable,
1067 };
1068
1069 /*
1070 * Structure defining the fields for USB UTMI clocks Parameters.
1071 */
1072 struct utmi_clk_param {
1073 /* Oscillator Frequency in Hz */
1074 u32 osc_frequency;
1075 /* UTMIP PLL Enable Delay Count */
1076 u8 enable_delay_count;
1077 /* UTMIP PLL Stable count */
1078 u8 stable_count;
1079 /* UTMIP PLL Active delay count */
1080 u8 active_delay_count;
1081 /* UTMIP PLL Xtal frequency count */
1082 u8 xtal_freq_count;
1083 };
1084
1085 static const struct utmi_clk_param utmi_parameters[] = {
1086 {
1087 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1088 .stable_count = 0x33, .active_delay_count = 0x05,
1089 .xtal_freq_count = 0x7f
1090 }, {
1091 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1092 .stable_count = 0x4b, .active_delay_count = 0x06,
1093 .xtal_freq_count = 0xbb
1094 }, {
1095 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1096 .stable_count = 0x2f, .active_delay_count = 0x04,
1097 .xtal_freq_count = 0x76
1098 }, {
1099 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1100 .stable_count = 0x66, .active_delay_count = 0x09,
1101 .xtal_freq_count = 0xfe
1102 }, {
1103 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1104 .stable_count = 0x41, .active_delay_count = 0x0a,
1105 .xtal_freq_count = 0xa4
1106 }, {
1107 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1108 .stable_count = 0x0, .active_delay_count = 0x6,
1109 .xtal_freq_count = 0x80
1110 },
1111 };
1112
1113 static int clk_pllu_enable(struct clk_hw *hw)
1114 {
1115 struct tegra_clk_pll *pll = to_clk_pll(hw);
1116 struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1117 struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1118 const struct utmi_clk_param *params = NULL;
1119 unsigned long flags = 0, input_rate;
1120 unsigned int i;
1121 int ret = 0;
1122 u32 value;
1123
1124 if (!osc) {
1125 pr_err("%s: failed to get OSC clock\n", __func__);
1126 return -EINVAL;
1127 }
1128
1129 input_rate = clk_hw_get_rate(osc);
1130
1131 if (pll->lock)
1132 spin_lock_irqsave(pll->lock, flags);
1133
1134 _clk_pll_enable(hw);
1135
1136 ret = clk_pll_wait_for_lock(pll);
1137 if (ret < 0)
1138 goto out;
1139
1140 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1141 if (input_rate == utmi_parameters[i].osc_frequency) {
1142 params = &utmi_parameters[i];
1143 break;
1144 }
1145 }
1146
1147 if (!params) {
1148 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1149 input_rate);
1150 ret = -EINVAL;
1151 goto out;
1152 }
1153
1154 value = pll_readl_base(pll);
1155 value &= ~PLLU_BASE_OVERRIDE;
1156 pll_writel_base(value, pll);
1157
1158 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1159 /* Program UTMIP PLL stable and active counts */
1160 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1161 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1162 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1163 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1164 /* Remove power downs from UTMIP PLL control bits */
1165 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1166 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1167 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1168 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1169
1170 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1171 /* Program UTMIP PLL delay and oscillator frequency counts */
1172 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1173 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1174 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1175 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1176 /* Remove power downs from UTMIP PLL control bits */
1177 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1178 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1179 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1180 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1181
1182 out:
1183 if (pll->lock)
1184 spin_unlock_irqrestore(pll->lock, flags);
1185
1186 return ret;
1187 }
1188
1189 static const struct clk_ops tegra_clk_pllu_ops = {
1190 .is_enabled = clk_pll_is_enabled,
1191 .enable = clk_pllu_enable,
1192 .disable = clk_pll_disable,
1193 .recalc_rate = clk_pll_recalc_rate,
1194 .round_rate = clk_pll_round_rate,
1195 .set_rate = clk_pll_set_rate,
1196 };
1197
1198 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1199 unsigned long parent_rate)
1200 {
1201 u16 mdiv = parent_rate / pll_params->cf_min;
1202
1203 if (pll_params->flags & TEGRA_MDIV_NEW)
1204 return (!pll_params->mdiv_default ? mdiv :
1205 min(mdiv, pll_params->mdiv_default));
1206
1207 if (pll_params->mdiv_default)
1208 return pll_params->mdiv_default;
1209
1210 if (parent_rate > pll_params->cf_max)
1211 return 2;
1212 else
1213 return 1;
1214 }
1215
1216 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1217 struct tegra_clk_pll_freq_table *cfg,
1218 unsigned long rate, unsigned long parent_rate)
1219 {
1220 struct tegra_clk_pll *pll = to_clk_pll(hw);
1221 unsigned int p;
1222 int p_div;
1223
1224 if (!rate)
1225 return -EINVAL;
1226
1227 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1228 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1229 cfg->output_rate = rate * p;
1230 cfg->n = cfg->output_rate * cfg->m / parent_rate;
1231 cfg->input_rate = parent_rate;
1232
1233 p_div = _p_div_to_hw(hw, p);
1234 if (p_div < 0)
1235 return p_div;
1236
1237 cfg->p = p_div;
1238
1239 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1240 return -EINVAL;
1241
1242 return 0;
1243 }
1244
1245 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1246 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1247 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1248 defined(CONFIG_ARCH_TEGRA_210_SOC)
1249
1250 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1251 {
1252 struct tegra_clk_pll *pll = to_clk_pll(hw);
1253
1254 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1255 }
1256
1257 static unsigned long _clip_vco_min(unsigned long vco_min,
1258 unsigned long parent_rate)
1259 {
1260 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1261 }
1262
1263 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1264 void __iomem *clk_base,
1265 unsigned long parent_rate)
1266 {
1267 u32 val;
1268 u32 step_a, step_b;
1269
1270 switch (parent_rate) {
1271 case 12000000:
1272 case 13000000:
1273 case 26000000:
1274 step_a = 0x2B;
1275 step_b = 0x0B;
1276 break;
1277 case 16800000:
1278 step_a = 0x1A;
1279 step_b = 0x09;
1280 break;
1281 case 19200000:
1282 step_a = 0x12;
1283 step_b = 0x08;
1284 break;
1285 default:
1286 pr_err("%s: Unexpected reference rate %lu\n",
1287 __func__, parent_rate);
1288 WARN_ON(1);
1289 return -EINVAL;
1290 }
1291
1292 val = step_a << pll_params->stepa_shift;
1293 val |= step_b << pll_params->stepb_shift;
1294 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1295
1296 return 0;
1297 }
1298
1299 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1300 struct tegra_clk_pll_freq_table *cfg,
1301 unsigned long rate, unsigned long parent_rate)
1302 {
1303 struct tegra_clk_pll *pll = to_clk_pll(hw);
1304 int err = 0;
1305
1306 err = _get_table_rate(hw, cfg, rate, parent_rate);
1307 if (err < 0)
1308 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1309 else {
1310 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1311 WARN_ON(1);
1312 err = -EINVAL;
1313 goto out;
1314 }
1315 }
1316
1317 if (cfg->p > pll->params->max_p)
1318 err = -EINVAL;
1319
1320 out:
1321 return err;
1322 }
1323
1324 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1325 unsigned long parent_rate)
1326 {
1327 struct tegra_clk_pll *pll = to_clk_pll(hw);
1328 struct tegra_clk_pll_freq_table cfg, old_cfg;
1329 unsigned long flags = 0;
1330 int ret;
1331
1332 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1333 if (ret < 0)
1334 return ret;
1335
1336 if (pll->lock)
1337 spin_lock_irqsave(pll->lock, flags);
1338
1339 _get_pll_mnp(pll, &old_cfg);
1340 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1341 cfg.p = old_cfg.p;
1342
1343 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1344 ret = _program_pll(hw, &cfg, rate);
1345
1346 if (pll->lock)
1347 spin_unlock_irqrestore(pll->lock, flags);
1348
1349 return ret;
1350 }
1351
1352 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1353 unsigned long *prate)
1354 {
1355 struct tegra_clk_pll *pll = to_clk_pll(hw);
1356 struct tegra_clk_pll_freq_table cfg;
1357 int ret, p_div;
1358 u64 output_rate = *prate;
1359
1360 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1361 if (ret < 0)
1362 return ret;
1363
1364 p_div = _hw_to_p_div(hw, cfg.p);
1365 if (p_div < 0)
1366 return p_div;
1367
1368 if (pll->params->set_gain)
1369 pll->params->set_gain(&cfg);
1370
1371 output_rate *= cfg.n;
1372 do_div(output_rate, cfg.m * p_div);
1373
1374 return output_rate;
1375 }
1376
1377 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1378 {
1379 u32 val;
1380
1381 val = pll_readl_misc(pll);
1382 val |= PLLCX_MISC_STROBE;
1383 pll_writel_misc(val, pll);
1384 udelay(2);
1385
1386 val &= ~PLLCX_MISC_STROBE;
1387 pll_writel_misc(val, pll);
1388 }
1389
1390 static int clk_pllc_enable(struct clk_hw *hw)
1391 {
1392 struct tegra_clk_pll *pll = to_clk_pll(hw);
1393 u32 val;
1394 int ret;
1395 unsigned long flags = 0;
1396
1397 if (clk_pll_is_enabled(hw))
1398 return 0;
1399
1400 if (pll->lock)
1401 spin_lock_irqsave(pll->lock, flags);
1402
1403 _clk_pll_enable(hw);
1404 udelay(2);
1405
1406 val = pll_readl_misc(pll);
1407 val &= ~PLLCX_MISC_RESET;
1408 pll_writel_misc(val, pll);
1409 udelay(2);
1410
1411 _pllcx_strobe(pll);
1412
1413 ret = clk_pll_wait_for_lock(pll);
1414
1415 if (pll->lock)
1416 spin_unlock_irqrestore(pll->lock, flags);
1417
1418 return ret;
1419 }
1420
1421 static void _clk_pllc_disable(struct clk_hw *hw)
1422 {
1423 struct tegra_clk_pll *pll = to_clk_pll(hw);
1424 u32 val;
1425
1426 _clk_pll_disable(hw);
1427
1428 val = pll_readl_misc(pll);
1429 val |= PLLCX_MISC_RESET;
1430 pll_writel_misc(val, pll);
1431 udelay(2);
1432 }
1433
1434 static void clk_pllc_disable(struct clk_hw *hw)
1435 {
1436 struct tegra_clk_pll *pll = to_clk_pll(hw);
1437 unsigned long flags = 0;
1438
1439 if (pll->lock)
1440 spin_lock_irqsave(pll->lock, flags);
1441
1442 _clk_pllc_disable(hw);
1443
1444 if (pll->lock)
1445 spin_unlock_irqrestore(pll->lock, flags);
1446 }
1447
1448 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1449 unsigned long input_rate, u32 n)
1450 {
1451 u32 val, n_threshold;
1452
1453 switch (input_rate) {
1454 case 12000000:
1455 n_threshold = 70;
1456 break;
1457 case 13000000:
1458 case 26000000:
1459 n_threshold = 71;
1460 break;
1461 case 16800000:
1462 n_threshold = 55;
1463 break;
1464 case 19200000:
1465 n_threshold = 48;
1466 break;
1467 default:
1468 pr_err("%s: Unexpected reference rate %lu\n",
1469 __func__, input_rate);
1470 return -EINVAL;
1471 }
1472
1473 val = pll_readl_misc(pll);
1474 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1475 val |= n <= n_threshold ?
1476 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1477 pll_writel_misc(val, pll);
1478
1479 return 0;
1480 }
1481
1482 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1483 unsigned long parent_rate)
1484 {
1485 struct tegra_clk_pll_freq_table cfg, old_cfg;
1486 struct tegra_clk_pll *pll = to_clk_pll(hw);
1487 unsigned long flags = 0;
1488 int state, ret = 0;
1489
1490 if (pll->lock)
1491 spin_lock_irqsave(pll->lock, flags);
1492
1493 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1494 if (ret < 0)
1495 goto out;
1496
1497 _get_pll_mnp(pll, &old_cfg);
1498
1499 if (cfg.m != old_cfg.m) {
1500 WARN_ON(1);
1501 goto out;
1502 }
1503
1504 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1505 goto out;
1506
1507 state = clk_pll_is_enabled(hw);
1508 if (state)
1509 _clk_pllc_disable(hw);
1510
1511 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1512 if (ret < 0)
1513 goto out;
1514
1515 _update_pll_mnp(pll, &cfg);
1516
1517 if (state)
1518 ret = clk_pllc_enable(hw);
1519
1520 out:
1521 if (pll->lock)
1522 spin_unlock_irqrestore(pll->lock, flags);
1523
1524 return ret;
1525 }
1526
1527 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1528 struct tegra_clk_pll_freq_table *cfg,
1529 unsigned long rate, unsigned long parent_rate)
1530 {
1531 u16 m, n;
1532 u64 output_rate = parent_rate;
1533
1534 m = _pll_fixed_mdiv(pll->params, parent_rate);
1535 n = rate * m / parent_rate;
1536
1537 output_rate *= n;
1538 do_div(output_rate, m);
1539
1540 if (cfg) {
1541 cfg->m = m;
1542 cfg->n = n;
1543 }
1544
1545 return output_rate;
1546 }
1547
1548 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1549 unsigned long parent_rate)
1550 {
1551 struct tegra_clk_pll_freq_table cfg, old_cfg;
1552 struct tegra_clk_pll *pll = to_clk_pll(hw);
1553 unsigned long flags = 0;
1554 int state, ret = 0;
1555
1556 if (pll->lock)
1557 spin_lock_irqsave(pll->lock, flags);
1558
1559 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1560 _get_pll_mnp(pll, &old_cfg);
1561 cfg.p = old_cfg.p;
1562
1563 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1564 state = clk_pll_is_enabled(hw);
1565 if (state)
1566 _clk_pll_disable(hw);
1567
1568 _update_pll_mnp(pll, &cfg);
1569
1570 if (state) {
1571 _clk_pll_enable(hw);
1572 ret = clk_pll_wait_for_lock(pll);
1573 }
1574 }
1575
1576 if (pll->lock)
1577 spin_unlock_irqrestore(pll->lock, flags);
1578
1579 return ret;
1580 }
1581
1582 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1583 unsigned long parent_rate)
1584 {
1585 struct tegra_clk_pll_freq_table cfg;
1586 struct tegra_clk_pll *pll = to_clk_pll(hw);
1587 u64 rate = parent_rate;
1588
1589 _get_pll_mnp(pll, &cfg);
1590
1591 rate *= cfg.n;
1592 do_div(rate, cfg.m);
1593
1594 return rate;
1595 }
1596
1597 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1598 unsigned long *prate)
1599 {
1600 struct tegra_clk_pll *pll = to_clk_pll(hw);
1601
1602 return _pllre_calc_rate(pll, NULL, rate, *prate);
1603 }
1604
1605 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1606 {
1607 struct tegra_clk_pll *pll = to_clk_pll(hw);
1608 struct tegra_clk_pll_freq_table sel;
1609 u32 val;
1610 int ret;
1611 unsigned long flags = 0;
1612 unsigned long input_rate;
1613
1614 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1615
1616 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1617 return -EINVAL;
1618
1619 if (pll->lock)
1620 spin_lock_irqsave(pll->lock, flags);
1621
1622 val = pll_readl_base(pll);
1623 val &= ~BIT(29); /* Disable lock override */
1624 pll_writel_base(val, pll);
1625
1626 val = pll_readl(pll->params->aux_reg, pll);
1627 val |= PLLE_AUX_ENABLE_SWCTL;
1628 val &= ~PLLE_AUX_SEQ_ENABLE;
1629 pll_writel(val, pll->params->aux_reg, pll);
1630 udelay(1);
1631
1632 val = pll_readl_misc(pll);
1633 val |= PLLE_MISC_LOCK_ENABLE;
1634 val |= PLLE_MISC_IDDQ_SW_CTRL;
1635 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1636 val |= PLLE_MISC_PLLE_PTS;
1637 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1638 pll_writel_misc(val, pll);
1639 udelay(5);
1640
1641 val = pll_readl(PLLE_SS_CTRL, pll);
1642 val |= PLLE_SS_DISABLE;
1643 pll_writel(val, PLLE_SS_CTRL, pll);
1644
1645 val = pll_readl_base(pll);
1646 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1647 divm_mask_shifted(pll));
1648 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1649 val |= sel.m << divm_shift(pll);
1650 val |= sel.n << divn_shift(pll);
1651 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1652 pll_writel_base(val, pll);
1653 udelay(1);
1654
1655 _clk_pll_enable(hw);
1656 ret = clk_pll_wait_for_lock(pll);
1657
1658 if (ret < 0)
1659 goto out;
1660
1661 val = pll_readl(PLLE_SS_CTRL, pll);
1662 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1663 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1664 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1665 pll_writel(val, PLLE_SS_CTRL, pll);
1666 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1667 pll_writel(val, PLLE_SS_CTRL, pll);
1668 udelay(1);
1669 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1670 pll_writel(val, PLLE_SS_CTRL, pll);
1671 udelay(1);
1672
1673 /* Enable HW control of XUSB brick PLL */
1674 val = pll_readl_misc(pll);
1675 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1676 pll_writel_misc(val, pll);
1677
1678 val = pll_readl(pll->params->aux_reg, pll);
1679 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1680 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1681 pll_writel(val, pll->params->aux_reg, pll);
1682 udelay(1);
1683 val |= PLLE_AUX_SEQ_ENABLE;
1684 pll_writel(val, pll->params->aux_reg, pll);
1685
1686 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1687 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1688 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1689 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1690 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1691 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1692 udelay(1);
1693 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1694 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1695
1696 /* Enable HW control of SATA PLL */
1697 val = pll_readl(SATA_PLL_CFG0, pll);
1698 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1699 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1700 val |= SATA_PLL_CFG0_SEQ_START_STATE;
1701 pll_writel(val, SATA_PLL_CFG0, pll);
1702
1703 udelay(1);
1704
1705 val = pll_readl(SATA_PLL_CFG0, pll);
1706 val |= SATA_PLL_CFG0_SEQ_ENABLE;
1707 pll_writel(val, SATA_PLL_CFG0, pll);
1708
1709 out:
1710 if (pll->lock)
1711 spin_unlock_irqrestore(pll->lock, flags);
1712
1713 return ret;
1714 }
1715
1716 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1717 {
1718 struct tegra_clk_pll *pll = to_clk_pll(hw);
1719 unsigned long flags = 0;
1720 u32 val;
1721
1722 if (pll->lock)
1723 spin_lock_irqsave(pll->lock, flags);
1724
1725 _clk_pll_disable(hw);
1726
1727 val = pll_readl_misc(pll);
1728 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1729 pll_writel_misc(val, pll);
1730 udelay(1);
1731
1732 if (pll->lock)
1733 spin_unlock_irqrestore(pll->lock, flags);
1734 }
1735
1736 static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1737 {
1738 struct tegra_clk_pll *pll = to_clk_pll(hw);
1739 const struct utmi_clk_param *params = NULL;
1740 struct clk *osc = __clk_lookup("osc");
1741 unsigned long flags = 0, input_rate;
1742 unsigned int i;
1743 int ret = 0;
1744 u32 value;
1745
1746 if (!osc) {
1747 pr_err("%s: failed to get OSC clock\n", __func__);
1748 return -EINVAL;
1749 }
1750
1751 if (clk_pll_is_enabled(hw))
1752 return 0;
1753
1754 input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1755
1756 if (pll->lock)
1757 spin_lock_irqsave(pll->lock, flags);
1758
1759 _clk_pll_enable(hw);
1760
1761 ret = clk_pll_wait_for_lock(pll);
1762 if (ret < 0)
1763 goto out;
1764
1765 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1766 if (input_rate == utmi_parameters[i].osc_frequency) {
1767 params = &utmi_parameters[i];
1768 break;
1769 }
1770 }
1771
1772 if (!params) {
1773 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1774 input_rate);
1775 ret = -EINVAL;
1776 goto out;
1777 }
1778
1779 value = pll_readl_base(pll);
1780 value &= ~PLLU_BASE_OVERRIDE;
1781 pll_writel_base(value, pll);
1782
1783 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1784 /* Program UTMIP PLL stable and active counts */
1785 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1786 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1787 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1788 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1789 /* Remove power downs from UTMIP PLL control bits */
1790 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1791 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1792 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1793 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1794
1795 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1796 /* Program UTMIP PLL delay and oscillator frequency counts */
1797 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1798 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1799 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1800 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1801 /* Remove power downs from UTMIP PLL control bits */
1802 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1803 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1804 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1805 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1806 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1807
1808 /* Setup HW control of UTMIPLL */
1809 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1810 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1811 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1812 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1813 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1814
1815 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1816 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1817 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1818 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1819
1820 udelay(1);
1821
1822 /*
1823 * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1824 * to USB2
1825 */
1826 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1827 value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1828 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1829 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1830
1831 udelay(1);
1832
1833 /* Enable HW control of UTMIPLL */
1834 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1835 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1836 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1837
1838 out:
1839 if (pll->lock)
1840 spin_unlock_irqrestore(pll->lock, flags);
1841
1842 return ret;
1843 }
1844
1845 static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
1846 {
1847 u32 val, val_aux;
1848
1849 /* ensure parent is set to pll_ref */
1850 val = pll_readl_base(pll);
1851 val_aux = pll_readl(pll->params->aux_reg, pll);
1852
1853 if (val & PLL_BASE_ENABLE) {
1854 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1855 (val_aux & PLLE_AUX_PLLP_SEL))
1856 WARN(1, "pll_e enabled with unsupported parent %s\n",
1857 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1858 "pll_re_vco");
1859 } else {
1860 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1861 pll_writel(val_aux, pll->params->aux_reg, pll);
1862 fence_udelay(1, pll->clk_base);
1863 }
1864 }
1865 #endif
1866
1867 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1868 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1869 spinlock_t *lock)
1870 {
1871 struct tegra_clk_pll *pll;
1872
1873 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1874 if (!pll)
1875 return ERR_PTR(-ENOMEM);
1876
1877 pll->clk_base = clk_base;
1878 pll->pmc = pmc;
1879
1880 pll->params = pll_params;
1881 pll->lock = lock;
1882
1883 if (!pll_params->div_nmp)
1884 pll_params->div_nmp = &default_nmp;
1885
1886 return pll;
1887 }
1888
1889 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1890 const char *name, const char *parent_name, unsigned long flags,
1891 const struct clk_ops *ops)
1892 {
1893 struct clk_init_data init;
1894
1895 init.name = name;
1896 init.ops = ops;
1897 init.flags = flags;
1898 init.parent_names = (parent_name ? &parent_name : NULL);
1899 init.num_parents = (parent_name ? 1 : 0);
1900
1901 /* Default to _calc_rate if unspecified */
1902 if (!pll->params->calc_rate) {
1903 if (pll->params->flags & TEGRA_PLLM)
1904 pll->params->calc_rate = _calc_dynamic_ramp_rate;
1905 else
1906 pll->params->calc_rate = _calc_rate;
1907 }
1908
1909 if (pll->params->set_defaults)
1910 pll->params->set_defaults(pll);
1911
1912 /* Data in .init is copied by clk_register(), so stack variable OK */
1913 pll->hw.init = &init;
1914
1915 return clk_register(NULL, &pll->hw);
1916 }
1917
1918 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1919 void __iomem *clk_base, void __iomem *pmc,
1920 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1921 spinlock_t *lock)
1922 {
1923 struct tegra_clk_pll *pll;
1924 struct clk *clk;
1925
1926 pll_params->flags |= TEGRA_PLL_BYPASS;
1927
1928 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1929 if (IS_ERR(pll))
1930 return ERR_CAST(pll);
1931
1932 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1933 &tegra_clk_pll_ops);
1934 if (IS_ERR(clk))
1935 kfree(pll);
1936
1937 return clk;
1938 }
1939
1940 static struct div_nmp pll_e_nmp = {
1941 .divn_shift = PLLE_BASE_DIVN_SHIFT,
1942 .divn_width = PLLE_BASE_DIVN_WIDTH,
1943 .divm_shift = PLLE_BASE_DIVM_SHIFT,
1944 .divm_width = PLLE_BASE_DIVM_WIDTH,
1945 .divp_shift = PLLE_BASE_DIVP_SHIFT,
1946 .divp_width = PLLE_BASE_DIVP_WIDTH,
1947 };
1948
1949 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1950 void __iomem *clk_base, void __iomem *pmc,
1951 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1952 spinlock_t *lock)
1953 {
1954 struct tegra_clk_pll *pll;
1955 struct clk *clk;
1956
1957 pll_params->flags |= TEGRA_PLL_BYPASS;
1958
1959 if (!pll_params->div_nmp)
1960 pll_params->div_nmp = &pll_e_nmp;
1961
1962 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1963 if (IS_ERR(pll))
1964 return ERR_CAST(pll);
1965
1966 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1967 &tegra_clk_plle_ops);
1968 if (IS_ERR(clk))
1969 kfree(pll);
1970
1971 return clk;
1972 }
1973
1974 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1975 void __iomem *clk_base, unsigned long flags,
1976 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1977 {
1978 struct tegra_clk_pll *pll;
1979 struct clk *clk;
1980
1981 pll_params->flags |= TEGRA_PLLU;
1982
1983 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1984 if (IS_ERR(pll))
1985 return ERR_CAST(pll);
1986
1987 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1988 &tegra_clk_pllu_ops);
1989 if (IS_ERR(clk))
1990 kfree(pll);
1991
1992 return clk;
1993 }
1994
1995 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1996 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1997 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1998 defined(CONFIG_ARCH_TEGRA_210_SOC)
1999 static const struct clk_ops tegra_clk_pllxc_ops = {
2000 .is_enabled = clk_pll_is_enabled,
2001 .enable = clk_pll_enable,
2002 .disable = clk_pll_disable,
2003 .recalc_rate = clk_pll_recalc_rate,
2004 .round_rate = clk_pll_ramp_round_rate,
2005 .set_rate = clk_pllxc_set_rate,
2006 };
2007
2008 static const struct clk_ops tegra_clk_pllc_ops = {
2009 .is_enabled = clk_pll_is_enabled,
2010 .enable = clk_pllc_enable,
2011 .disable = clk_pllc_disable,
2012 .recalc_rate = clk_pll_recalc_rate,
2013 .round_rate = clk_pll_ramp_round_rate,
2014 .set_rate = clk_pllc_set_rate,
2015 };
2016
2017 static const struct clk_ops tegra_clk_pllre_ops = {
2018 .is_enabled = clk_pll_is_enabled,
2019 .enable = clk_pll_enable,
2020 .disable = clk_pll_disable,
2021 .recalc_rate = clk_pllre_recalc_rate,
2022 .round_rate = clk_pllre_round_rate,
2023 .set_rate = clk_pllre_set_rate,
2024 };
2025
2026 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
2027 .is_enabled = clk_pll_is_enabled,
2028 .enable = clk_plle_tegra114_enable,
2029 .disable = clk_plle_tegra114_disable,
2030 .recalc_rate = clk_pll_recalc_rate,
2031 };
2032
2033 static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
2034 .is_enabled = clk_pll_is_enabled,
2035 .enable = clk_pllu_tegra114_enable,
2036 .disable = clk_pll_disable,
2037 .recalc_rate = clk_pll_recalc_rate,
2038 };
2039
2040 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
2041 void __iomem *clk_base, void __iomem *pmc,
2042 unsigned long flags,
2043 struct tegra_clk_pll_params *pll_params,
2044 spinlock_t *lock)
2045 {
2046 struct tegra_clk_pll *pll;
2047 struct clk *clk, *parent;
2048 unsigned long parent_rate;
2049 u32 val, val_iddq;
2050
2051 parent = __clk_lookup(parent_name);
2052 if (!parent) {
2053 WARN(1, "parent clk %s of %s must be registered first\n",
2054 parent_name, name);
2055 return ERR_PTR(-EINVAL);
2056 }
2057
2058 if (!pll_params->pdiv_tohw)
2059 return ERR_PTR(-EINVAL);
2060
2061 parent_rate = clk_get_rate(parent);
2062
2063 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2064
2065 if (pll_params->adjust_vco)
2066 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2067 parent_rate);
2068
2069 /*
2070 * If the pll has a set_defaults callback, it will take care of
2071 * configuring dynamic ramping and setting IDDQ in that path.
2072 */
2073 if (!pll_params->set_defaults) {
2074 int err;
2075
2076 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2077 if (err)
2078 return ERR_PTR(err);
2079
2080 val = readl_relaxed(clk_base + pll_params->base_reg);
2081 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2082
2083 if (val & PLL_BASE_ENABLE)
2084 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2085 else {
2086 val_iddq |= BIT(pll_params->iddq_bit_idx);
2087 writel_relaxed(val_iddq,
2088 clk_base + pll_params->iddq_reg);
2089 }
2090 }
2091
2092 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2093 if (IS_ERR(pll))
2094 return ERR_CAST(pll);
2095
2096 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2097 &tegra_clk_pllxc_ops);
2098 if (IS_ERR(clk))
2099 kfree(pll);
2100
2101 return clk;
2102 }
2103
2104 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2105 void __iomem *clk_base, void __iomem *pmc,
2106 unsigned long flags,
2107 struct tegra_clk_pll_params *pll_params,
2108 spinlock_t *lock, unsigned long parent_rate)
2109 {
2110 u32 val;
2111 struct tegra_clk_pll *pll;
2112 struct clk *clk;
2113
2114 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2115
2116 if (pll_params->adjust_vco)
2117 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2118 parent_rate);
2119
2120 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2121 if (IS_ERR(pll))
2122 return ERR_CAST(pll);
2123
2124 /* program minimum rate by default */
2125
2126 val = pll_readl_base(pll);
2127 if (val & PLL_BASE_ENABLE)
2128 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2129 BIT(pll_params->iddq_bit_idx));
2130 else {
2131 int m;
2132
2133 m = _pll_fixed_mdiv(pll_params, parent_rate);
2134 val = m << divm_shift(pll);
2135 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2136 pll_writel_base(val, pll);
2137 }
2138
2139 /* disable lock override */
2140
2141 val = pll_readl_misc(pll);
2142 val &= ~BIT(29);
2143 pll_writel_misc(val, pll);
2144
2145 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2146 &tegra_clk_pllre_ops);
2147 if (IS_ERR(clk))
2148 kfree(pll);
2149
2150 return clk;
2151 }
2152
2153 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2154 void __iomem *clk_base, void __iomem *pmc,
2155 unsigned long flags,
2156 struct tegra_clk_pll_params *pll_params,
2157 spinlock_t *lock)
2158 {
2159 struct tegra_clk_pll *pll;
2160 struct clk *clk, *parent;
2161 unsigned long parent_rate;
2162
2163 if (!pll_params->pdiv_tohw)
2164 return ERR_PTR(-EINVAL);
2165
2166 parent = __clk_lookup(parent_name);
2167 if (!parent) {
2168 WARN(1, "parent clk %s of %s must be registered first\n",
2169 parent_name, name);
2170 return ERR_PTR(-EINVAL);
2171 }
2172
2173 parent_rate = clk_get_rate(parent);
2174
2175 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2176
2177 if (pll_params->adjust_vco)
2178 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2179 parent_rate);
2180
2181 pll_params->flags |= TEGRA_PLL_BYPASS;
2182 pll_params->flags |= TEGRA_PLLM;
2183 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2184 if (IS_ERR(pll))
2185 return ERR_CAST(pll);
2186
2187 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2188 &tegra_clk_pll_ops);
2189 if (IS_ERR(clk))
2190 kfree(pll);
2191
2192 return clk;
2193 }
2194
2195 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2196 void __iomem *clk_base, void __iomem *pmc,
2197 unsigned long flags,
2198 struct tegra_clk_pll_params *pll_params,
2199 spinlock_t *lock)
2200 {
2201 struct clk *parent, *clk;
2202 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2203 struct tegra_clk_pll *pll;
2204 struct tegra_clk_pll_freq_table cfg;
2205 unsigned long parent_rate;
2206
2207 if (!p_tohw)
2208 return ERR_PTR(-EINVAL);
2209
2210 parent = __clk_lookup(parent_name);
2211 if (!parent) {
2212 WARN(1, "parent clk %s of %s must be registered first\n",
2213 parent_name, name);
2214 return ERR_PTR(-EINVAL);
2215 }
2216
2217 parent_rate = clk_get_rate(parent);
2218
2219 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2220
2221 pll_params->flags |= TEGRA_PLL_BYPASS;
2222 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2223 if (IS_ERR(pll))
2224 return ERR_CAST(pll);
2225
2226 /*
2227 * Most of PLLC register fields are shadowed, and can not be read
2228 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2229 * Initialize PLL to default state: disabled, reset; shadow registers
2230 * loaded with default parameters; dividers are preset for half of
2231 * minimum VCO rate (the latter assured that shadowed divider settings
2232 * are within supported range).
2233 */
2234
2235 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2236 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2237
2238 while (p_tohw->pdiv) {
2239 if (p_tohw->pdiv == 2) {
2240 cfg.p = p_tohw->hw_val;
2241 break;
2242 }
2243 p_tohw++;
2244 }
2245
2246 if (!p_tohw->pdiv) {
2247 WARN_ON(1);
2248 return ERR_PTR(-EINVAL);
2249 }
2250
2251 pll_writel_base(0, pll);
2252 _update_pll_mnp(pll, &cfg);
2253
2254 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2255 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2256 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2257 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2258
2259 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2260
2261 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2262 &tegra_clk_pllc_ops);
2263 if (IS_ERR(clk))
2264 kfree(pll);
2265
2266 return clk;
2267 }
2268
2269 struct clk *tegra_clk_register_plle_tegra114(const char *name,
2270 const char *parent_name,
2271 void __iomem *clk_base, unsigned long flags,
2272 struct tegra_clk_pll_params *pll_params,
2273 spinlock_t *lock)
2274 {
2275 struct tegra_clk_pll *pll;
2276 struct clk *clk;
2277
2278 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2279 if (IS_ERR(pll))
2280 return ERR_CAST(pll);
2281
2282 _clk_plle_tegra_init_parent(pll);
2283
2284 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2285 &tegra_clk_plle_tegra114_ops);
2286 if (IS_ERR(clk))
2287 kfree(pll);
2288
2289 return clk;
2290 }
2291
2292 struct clk *
2293 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2294 void __iomem *clk_base, unsigned long flags,
2295 struct tegra_clk_pll_params *pll_params,
2296 spinlock_t *lock)
2297 {
2298 struct tegra_clk_pll *pll;
2299 struct clk *clk;
2300
2301 pll_params->flags |= TEGRA_PLLU;
2302
2303 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2304 if (IS_ERR(pll))
2305 return ERR_CAST(pll);
2306
2307 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2308 &tegra_clk_pllu_tegra114_ops);
2309 if (IS_ERR(clk))
2310 kfree(pll);
2311
2312 return clk;
2313 }
2314 #endif
2315
2316 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
2317 static const struct clk_ops tegra_clk_pllss_ops = {
2318 .is_enabled = clk_pll_is_enabled,
2319 .enable = clk_pll_enable,
2320 .disable = clk_pll_disable,
2321 .recalc_rate = clk_pll_recalc_rate,
2322 .round_rate = clk_pll_ramp_round_rate,
2323 .set_rate = clk_pllxc_set_rate,
2324 .restore_context = tegra_clk_pll_restore_context,
2325 };
2326
2327 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2328 void __iomem *clk_base, unsigned long flags,
2329 struct tegra_clk_pll_params *pll_params,
2330 spinlock_t *lock)
2331 {
2332 struct tegra_clk_pll *pll;
2333 struct clk *clk, *parent;
2334 struct tegra_clk_pll_freq_table cfg;
2335 unsigned long parent_rate;
2336 u32 val, val_iddq;
2337 int i;
2338
2339 if (!pll_params->div_nmp)
2340 return ERR_PTR(-EINVAL);
2341
2342 parent = __clk_lookup(parent_name);
2343 if (!parent) {
2344 WARN(1, "parent clk %s of %s must be registered first\n",
2345 parent_name, name);
2346 return ERR_PTR(-EINVAL);
2347 }
2348
2349 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2350 if (IS_ERR(pll))
2351 return ERR_CAST(pll);
2352
2353 val = pll_readl_base(pll);
2354 val &= ~PLLSS_REF_SRC_SEL_MASK;
2355 pll_writel_base(val, pll);
2356
2357 parent_rate = clk_get_rate(parent);
2358
2359 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2360
2361 /* initialize PLL to minimum rate */
2362
2363 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2364 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2365
2366 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2367 ;
2368 if (!i) {
2369 kfree(pll);
2370 return ERR_PTR(-EINVAL);
2371 }
2372
2373 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2374
2375 _update_pll_mnp(pll, &cfg);
2376
2377 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2378 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2379 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2380 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2381
2382 val = pll_readl_base(pll);
2383 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2384 if (val & PLL_BASE_ENABLE) {
2385 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2386 WARN(1, "%s is on but IDDQ set\n", name);
2387 kfree(pll);
2388 return ERR_PTR(-EINVAL);
2389 }
2390 } else {
2391 val_iddq |= BIT(pll_params->iddq_bit_idx);
2392 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2393 }
2394
2395 val &= ~PLLSS_LOCK_OVERRIDE;
2396 pll_writel_base(val, pll);
2397
2398 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2399 &tegra_clk_pllss_ops);
2400
2401 if (IS_ERR(clk))
2402 kfree(pll);
2403
2404 return clk;
2405 }
2406 #endif
2407
2408 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2409 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2410 const char *parent_name, void __iomem *clk_base,
2411 void __iomem *pmc, unsigned long flags,
2412 struct tegra_clk_pll_params *pll_params,
2413 spinlock_t *lock, unsigned long parent_rate)
2414 {
2415 struct tegra_clk_pll *pll;
2416 struct clk *clk;
2417
2418 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2419
2420 if (pll_params->adjust_vco)
2421 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2422 parent_rate);
2423
2424 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2425 if (IS_ERR(pll))
2426 return ERR_CAST(pll);
2427
2428 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2429 &tegra_clk_pll_ops);
2430 if (IS_ERR(clk))
2431 kfree(pll);
2432
2433 return clk;
2434 }
2435
2436 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2437 {
2438 struct tegra_clk_pll *pll = to_clk_pll(hw);
2439 u32 val;
2440
2441 val = pll_readl_base(pll);
2442
2443 return val & PLLE_BASE_ENABLE ? 1 : 0;
2444 }
2445
2446 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2447 {
2448 struct tegra_clk_pll *pll = to_clk_pll(hw);
2449 struct tegra_clk_pll_freq_table sel;
2450 u32 val;
2451 int ret = 0;
2452 unsigned long flags = 0;
2453 unsigned long input_rate;
2454
2455 if (clk_plle_tegra210_is_enabled(hw))
2456 return 0;
2457
2458 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2459
2460 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2461 return -EINVAL;
2462
2463 if (pll->lock)
2464 spin_lock_irqsave(pll->lock, flags);
2465
2466 val = pll_readl(pll->params->aux_reg, pll);
2467 if (val & PLLE_AUX_SEQ_ENABLE)
2468 goto out;
2469
2470 val = pll_readl_base(pll);
2471 val &= ~BIT(30); /* Disable lock override */
2472 pll_writel_base(val, pll);
2473
2474 val = pll_readl_misc(pll);
2475 val |= PLLE_MISC_LOCK_ENABLE;
2476 val |= PLLE_MISC_IDDQ_SW_CTRL;
2477 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2478 val |= PLLE_MISC_PLLE_PTS;
2479 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2480 pll_writel_misc(val, pll);
2481 udelay(5);
2482
2483 val = pll_readl(PLLE_SS_CTRL, pll);
2484 val |= PLLE_SS_DISABLE;
2485 pll_writel(val, PLLE_SS_CTRL, pll);
2486
2487 val = pll_readl_base(pll);
2488 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2489 divm_mask_shifted(pll));
2490 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2491 val |= sel.m << divm_shift(pll);
2492 val |= sel.n << divn_shift(pll);
2493 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2494 pll_writel_base(val, pll);
2495 udelay(1);
2496
2497 val = pll_readl_base(pll);
2498 val |= PLLE_BASE_ENABLE;
2499 pll_writel_base(val, pll);
2500
2501 ret = clk_pll_wait_for_lock(pll);
2502
2503 if (ret < 0)
2504 goto out;
2505
2506 val = pll_readl(PLLE_SS_CTRL, pll);
2507 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2508 val &= ~PLLE_SS_COEFFICIENTS_MASK;
2509 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2510 pll_writel(val, PLLE_SS_CTRL, pll);
2511 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2512 pll_writel(val, PLLE_SS_CTRL, pll);
2513 udelay(1);
2514 val &= ~PLLE_SS_CNTL_INTERP_RESET;
2515 pll_writel(val, PLLE_SS_CTRL, pll);
2516 udelay(1);
2517
2518 val = pll_readl_misc(pll);
2519 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2520 pll_writel_misc(val, pll);
2521
2522 val = pll_readl(pll->params->aux_reg, pll);
2523 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2524 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2525 pll_writel(val, pll->params->aux_reg, pll);
2526 udelay(1);
2527 val |= PLLE_AUX_SEQ_ENABLE;
2528 pll_writel(val, pll->params->aux_reg, pll);
2529
2530 out:
2531 if (pll->lock)
2532 spin_unlock_irqrestore(pll->lock, flags);
2533
2534 return ret;
2535 }
2536
2537 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2538 {
2539 struct tegra_clk_pll *pll = to_clk_pll(hw);
2540 unsigned long flags = 0;
2541 u32 val;
2542
2543 if (pll->lock)
2544 spin_lock_irqsave(pll->lock, flags);
2545
2546 /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2547 val = pll_readl(pll->params->aux_reg, pll);
2548 if (val & PLLE_AUX_SEQ_ENABLE)
2549 goto out;
2550
2551 val = pll_readl_base(pll);
2552 val &= ~PLLE_BASE_ENABLE;
2553 pll_writel_base(val, pll);
2554
2555 val = pll_readl(pll->params->aux_reg, pll);
2556 val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2557 pll_writel(val, pll->params->aux_reg, pll);
2558
2559 val = pll_readl_misc(pll);
2560 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2561 pll_writel_misc(val, pll);
2562 udelay(1);
2563
2564 out:
2565 if (pll->lock)
2566 spin_unlock_irqrestore(pll->lock, flags);
2567 }
2568
2569 static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw)
2570 {
2571 struct tegra_clk_pll *pll = to_clk_pll(hw);
2572
2573 _clk_plle_tegra_init_parent(pll);
2574 }
2575
2576 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2577 .is_enabled = clk_plle_tegra210_is_enabled,
2578 .enable = clk_plle_tegra210_enable,
2579 .disable = clk_plle_tegra210_disable,
2580 .recalc_rate = clk_pll_recalc_rate,
2581 .restore_context = tegra_clk_plle_t210_restore_context,
2582 };
2583
2584 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2585 const char *parent_name,
2586 void __iomem *clk_base, unsigned long flags,
2587 struct tegra_clk_pll_params *pll_params,
2588 spinlock_t *lock)
2589 {
2590 struct tegra_clk_pll *pll;
2591 struct clk *clk;
2592
2593 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2594 if (IS_ERR(pll))
2595 return ERR_CAST(pll);
2596
2597 _clk_plle_tegra_init_parent(pll);
2598
2599 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2600 &tegra_clk_plle_tegra210_ops);
2601 if (IS_ERR(clk))
2602 kfree(pll);
2603
2604 return clk;
2605 }
2606
2607 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2608 const char *parent_name, void __iomem *clk_base,
2609 void __iomem *pmc, unsigned long flags,
2610 struct tegra_clk_pll_params *pll_params,
2611 spinlock_t *lock)
2612 {
2613 struct clk *parent, *clk;
2614 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2615 struct tegra_clk_pll *pll;
2616 unsigned long parent_rate;
2617
2618 if (!p_tohw)
2619 return ERR_PTR(-EINVAL);
2620
2621 parent = __clk_lookup(parent_name);
2622 if (!parent) {
2623 WARN(1, "parent clk %s of %s must be registered first\n",
2624 name, parent_name);
2625 return ERR_PTR(-EINVAL);
2626 }
2627
2628 parent_rate = clk_get_rate(parent);
2629
2630 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2631
2632 if (pll_params->adjust_vco)
2633 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2634 parent_rate);
2635
2636 pll_params->flags |= TEGRA_PLL_BYPASS;
2637 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2638 if (IS_ERR(pll))
2639 return ERR_CAST(pll);
2640
2641 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2642 &tegra_clk_pll_ops);
2643 if (IS_ERR(clk))
2644 kfree(pll);
2645
2646 return clk;
2647 }
2648
2649 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2650 const char *parent_name, void __iomem *clk_base,
2651 unsigned long flags,
2652 struct tegra_clk_pll_params *pll_params,
2653 spinlock_t *lock)
2654 {
2655 struct tegra_clk_pll *pll;
2656 struct clk *clk, *parent;
2657 unsigned long parent_rate;
2658 u32 val;
2659
2660 if (!pll_params->div_nmp)
2661 return ERR_PTR(-EINVAL);
2662
2663 parent = __clk_lookup(parent_name);
2664 if (!parent) {
2665 WARN(1, "parent clk %s of %s must be registered first\n",
2666 name, parent_name);
2667 return ERR_PTR(-EINVAL);
2668 }
2669
2670 val = readl_relaxed(clk_base + pll_params->base_reg);
2671 if (val & PLLSS_REF_SRC_SEL_MASK) {
2672 WARN(1, "not supported reference clock for %s\n", name);
2673 return ERR_PTR(-EINVAL);
2674 }
2675
2676 parent_rate = clk_get_rate(parent);
2677
2678 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2679
2680 if (pll_params->adjust_vco)
2681 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2682 parent_rate);
2683
2684 pll_params->flags |= TEGRA_PLL_BYPASS;
2685 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2686 if (IS_ERR(pll))
2687 return ERR_CAST(pll);
2688
2689 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2690 &tegra_clk_pll_ops);
2691
2692 if (IS_ERR(clk))
2693 kfree(pll);
2694
2695 return clk;
2696 }
2697
2698 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2699 void __iomem *clk_base, void __iomem *pmc,
2700 unsigned long flags,
2701 struct tegra_clk_pll_params *pll_params,
2702 spinlock_t *lock)
2703 {
2704 struct tegra_clk_pll *pll;
2705 struct clk *clk, *parent;
2706 unsigned long parent_rate;
2707
2708 if (!pll_params->pdiv_tohw)
2709 return ERR_PTR(-EINVAL);
2710
2711 parent = __clk_lookup(parent_name);
2712 if (!parent) {
2713 WARN(1, "parent clk %s of %s must be registered first\n",
2714 parent_name, name);
2715 return ERR_PTR(-EINVAL);
2716 }
2717
2718 parent_rate = clk_get_rate(parent);
2719
2720 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2721
2722 if (pll_params->adjust_vco)
2723 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2724 parent_rate);
2725
2726 pll_params->flags |= TEGRA_PLL_BYPASS;
2727 pll_params->flags |= TEGRA_PLLMB;
2728 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2729 if (IS_ERR(pll))
2730 return ERR_CAST(pll);
2731
2732 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2733 &tegra_clk_pll_ops);
2734 if (IS_ERR(clk))
2735 kfree(pll);
2736
2737 return clk;
2738 }
2739
2740 #endif
Linux with added FPC-III support